DATASHEET HS-0548RH, HS-0549RH. Features. Applications. Pinouts. Ordering Information
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1 DATASHEET HS-0RH, HS-0RH Radiation Hardened Single /Differential Channel CMOS Analog Multiplexers with Active Overvoltage rotection F Rev.00 August 00 The HS-0RH and HS-0RH are radiation hardened analog multiplexers with Active Overvoltage rotection and guaranteed r O matching. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 0V peak-to-peak levels with V supplies and digital inputs will sustain continuous faults up to V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur: each input presents k of resistance under this condition. These features make the HS-0RH and HS-0RH ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. Both devices are fabricated with V dielectrically isolated CMOS technology. The HS-0 is an channel device and the HS-0 is a channel differential version. If input overvoltage protection is not needed, the HS-00 and HS-0 multiplexers are recommended. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD -. A hot-link is provided on our homepage for downloading. Ordering Information ORDERIG UMBER ITERAL MKT. UMBER TEM. RAGE ( o C) D0VEA HS-0RH-Q - to D0VEC HSB-0RH-Q - to D0VEA HS-0RH-Q - to D0VEC HSB-0RH-Q - to Features Electrically Screened to SMD # - QML Qualified per MIL-RF- Requirements Gamma Dose x 0 RAD(Si) o Latch-Up o Channel Interaction During Overvoltage Guaranteed r O Matching Maximum ower Supply V Break-Before-Make Switching Analog Signal Range V Access Time s Applications Data Acquisition Systems Control Systems Telemetry inouts HS-0RH GDI-T (CERDI) OR CDI-T (SBDI) TO VIEW AO EABLE -V SULY I I I I A A GD +V SULY I I 0 I I HS-0RH GDI-T (CERDI) OR CDI-T (SBDI) TO VIEW EABLE -V SULY I A I A I A I A A A GD +V SULY I B I B I B 0 I B B F Rev.00 age of August 00
2 HS-0RH, HS-0RH Functional Diagrams HS-0 HS-0 I I R/ DRIVER IA IA IB A B I IB R/ DRIVER V REF SHIFT OVER- VOLTAGE CLAM AD SIGAL ISOLATIO OVER- VOLTAGE CLAM AD SIGAL ISOLATIO V REF SHIFT DIGITAL IUT ROTECTIO DIGITAL IUT ROTECTIO A A E A E HS-0 TRUTH TABLE HS-0 TRUTH TABLE A A E O CHAEL X X X L OE L L L H L L H H L H L H L H H H H L L H A E O CHAEL AIR X X L OE L L H L H H H L H H H H H L H H H H L H H H H H Switching Waveforms /V AH +0V V AH =.0 -V DRIVE (V A ) V AL = 0V UT A -0V V A A A E V AH I I THRU I I GD 0K 0V 0V V V A IUT V/DIV. CH O UT A V/DIV. t A CH O 00ns/DIV. FIGURE. ACCESS TIME F Rev.00 age of August 00
3 HS-0RH, HS-0RH Switching Waveforms (Continued) 0V V AH =.0 DRIVE (VA) V A A A I I THRU I +V VA IUT V/DIV. 0% 0% UT V AH E GD I V CH O CH O UT V/DIV. t OE 00ns/DIV. FIGURE. BREAK-BEFORE-MAKE DELAY (t OE ) 0% V AH =.0 0% t O(E) t OFF (E) 0V UT 0% V A A A E I I THRU I GD +0V CH OFF EABLE DRIVE V/DIV. CH O UT V/DIV. 00ns/DIV. FIGURE. EABLE DELAY t O(E), t OFF(E) Schematic Diagrams TTL REFERECE CIRCUIT R R 0 Q Q D SHIFTER ADD I. OVERVOLTAGE ROTECTIO D R 00 D R R R R R R R SHIFTED TO SHIFTED TO FIGURE. IUT BUFFER AD SHIFTER F Rev.00 age of August 00
4 HS-0RH, HS-0RH Schematic Diagrams (Continued) +V FROM OVERVOLTAGE ROTECTIO Q A OR A OR I R D D D D A OR A Q EABLE V TO -CHAEL DEVICE OF THE SWITCH AIR TO -CHAEL DEVICE OF THE SWITCH AIR FROM FIGURE. R FIGURE. MULTILEX SWITCH Burn-In/Life Test Circuits V F 0 F F F V V D C V D C D C D C V R 0 R 0 HS-0RH DYAMIC BUR-I AD LIFE TEST CIRCUIT V = -V maximum, -V minimum V = +V minimum, +V maximum R = 0k % /W C = C = 0.0 F minimum (per socket) or 0. F minimum (per row) D = D = 00 (or equivalent) F 0 = 00kHz 0% duty cycle; V IL = 0.V Max; V IH =.0V Min. F = F 0/ F = F / F = F / HS-0RH STATIC BUR-I TEST CIRCUIT V = V minimum, V maximum V = -V maximum, -V minimum V = +V minimum, +V maximum R = 0k % /W C = C = 0.0 F minimum (per socket) or 0. F minimum (per row) D = D = 00 (or equivalent) F Rev.00 age of August 00
5 HS-0RH, HS-0RH Burn-In/Life Test Circuits (Continued) F 0 F V F V V V V D C D C D C D C 0 0 R R R R HS-0RH DYAMIC BUR-I AD LIFE TEST CIRCUIT V = +.V,.0.V V = -.V, 0.V R = 0k, % C = 0.0 F minimum (per socket) D = 00 or equivalent (per board) F 0 = 00kHz, 0%; F = F 0/ ; F = F /, 0% duty cycle, V IL = 0.V Max; V IH =.0V Min HS-0RH STATIC BUR-I TEST CIRCUIT V = +.V, 0.V V = +.V, 0.V V = -.V, 0.V R = 0k, 0% C = 0.0 F minimum (per socket) D = 00 or equivalent (per board) Irradiation Circuits +V +V -V +V -V +V +V +V +V +V 0 0 R R R HS-0RH HS-0RH R = R = 0k % R = 0k % F Rev.00 age of August 00
6 HS-0RH, HS-0RH Die Characteristics DIE DIMESIOS: mils x 0 mils x mils ITERFACE MATERIALS: Glassivation: Type: itride Thickness: kå 0.kÅ Top Metallization: Type: Al Thickness: kå kå Substrate: CMOS, DI ASSEMBLY RELATED IFORMATIO: Substrate otential: Floating ADDITIOAL IFORMATIO: Worst Case Current Density:. x 0 A/cm Transistor Count: Metallization Mask Layout HS-0RH HS-0RH I I I I I IB IB B A IA IA I I IB IA +V I IB IA GD -V +V A A E GD A E OTE: ad umbers Correspond to DI in umbers Only F Rev.00 age of August 00
7 HS-0RH, HS-0RH Copyright Intersil Americas LLC 00. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO00 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. o license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see F Rev.00 age of August 00
Features OUT A NC 27 NC IN 8A IN 16 IN 7A IN 15 IN 6A IN 14 IN 5A IN 13 IN 4A IN 12 IN 3A IN 11 IN 2A IN 10 IN 1A IN 9 ENABLE GND ADDRESS A0 V REF
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