Features OUT A NC 27 NC IN 8A IN 16 IN 7A IN 15 IN 6A IN 14 IN 5A IN 13 IN 4A IN 12 IN 3A IN 11 IN 2A IN 10 IN 1A IN 9 ENABLE GND ADDRESS A0 V REF

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1 DATASHEET HS-0RH, HS-0RH Radiation Hardened Single /Differential Channel CMOS Analog Multiplexers with Active Overvoltage rotection F Rev..00 The HS-0RH and HS-0RH are radiation hardened analog multiplexers with Active Overvoltage rotection and guaranteed r O matching. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 0V peak-to-peak levels with V supplies and digital inputs will sustain continuous faults up to V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur: each input presents k of resistance under this condition. These features make the HS-0RH and HS-0RH ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. Both devices are fabricated with V dielectrically isolated CMOS technology. The HS-0 is a channel device and the HS-0 is an channel differential version. If input overvoltage protection is not needed, the HS-00 and HS-00 multiplexers are recommended. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD -. A hot-link is provided on our homepage for downloading. inouts HS-0RH GDI-T (CERDI) OR CDI-T (SBDI) TO VIEW Features Electrically Screened to SMD # - QML Qualified per MIL-RF- Requirements Gamma Dose x RAD(Si) o Latch-Up o Channel Interaction During Overvoltage Guaranteed r O Matching Maximum ower Supply V Break-Before-Make Switch Analog Signal Range V Access Time s Applications Data Acquisition Systems Control Systems Telemetry Ordering Information ORDERIG UMBER ITERAL MKT. UMBER ART MARKIG TEM. RAGE ( C) D0VA HS0-0RH-Q Q-D0VA D0VXC HSB-0RH-Q Q-D0VXC - to D0VA HS0-0RH-Q Q-D0VA D0VXC HSB-0RH-Q Q-D0VXC - to HS-0RH GDI-T (CERDI) OR CDI-T (SBDI) TO VIEW V SULY +V SULY A C -V SULY B -V SULY C I C I A I I I B I A I I I B I A I I I B I A I I I B I A I I I B I A I 0 I I B 0 I A I I I B I A I EABLE I B EABLE GD GD V REF A V REF A A A C A F Rev..00 age of

2 Functional Diagrams HS-0RH HS-0RH I I R/ DRIVER IA IA IB A B I IB R/ DRIVER V REF SHIFT OVER- VOLTAGE CLAM AD SIGAL ISOLATIO OVER- VOLTAGE CLAM AD SIGAL ISOLATIO V REF SHIFT DIGITAL IUT ROTECTIO DIGITAL IUT ROTECTIO VREF A A A E VREF A A E HS-0RH TRUTH TABLE HS-0RH TRUTH TABLE A A A E O CHAEL X X X X L OE L L L L H L L L H H L L H L H L L H H H L H L L H L H L H H L H H L H L H H H H H L L L H H L L H H A A E O CHAEL AIR X X X L OE L L L H L L H H L H L H L H H H H L L H H L H H H H L H H H H H H L H L H H L H H H H H L L H H H L H H H H H L H H H H H H F Rev..00 age of

3 Switching Waveforms 0% +V VAH =.0 -V DRIVE (VA) 0V UT A -V VA VAH A A A E I I THRU I I GD V K V V CH O VA IUT V/DIV. UT A V/DIV. ta CH O 00ns/DIV FIGURE. ACCESS TIME 0V VAH =.0 0% 0% DRIVE (VA) UT VA A A A E VAH I I THRU I I GD +V V VA IUT V/DIV. UT V/DIV. toe 0ns/DIV FIGURE. BREAK-BEFORE-MAKE DELAY (toe) VAH =.0 0% 0% to(e) toff (E) 0V UT 0% VA A A A E I I THRU I GD +V CH OFF CH O UT V/DIV. 0ns/DIV FIGURE. EABLE DELAY to(e), toff(e) F Rev..00 age of

4 Schematic Diagrams TTL REFERECE CIRCUIT R R Q Q D SHIFTER ADD I. OVERVOLTAGE ROTECTIO D R 00 D V- R R R R R R R V- SHIFTED TO SHIFTED TO FIGURE. IUT BUFFER AD SHIFTER +V FROM OVERVOLTAGE ROTECTIO Q A OR A OR I R D D D D A OR A Q EABLE TO -CHAEL DEVICE OF THE SWITCH AIR TO -CHAEL DEVICE OF THE SWITCH AIR V- FROM V FIGURE. R FIGURE. MULTILEX SWITCH F Rev..00 age of

5 Burn-In/Life Test Circuits V C D R R V D C V C D R R V D C 0 0 F F0 F F F V DYAMIC AD LIFE TEST OTES:. The Dynamic Test Circuit is utilized for all life testing.. V = +V minimum, +V maximum.. V = -V maximum, -V minimum.. R, R = k, %, / or /W (per socket).. C, C = 0.0 F minimum (per socket) or 0. F minimum (per row).. D, D = 00 or equivalent (per board).. F0 = 0kHz, %; F = F0/; F = F/; F = F/; F = F/ 0% - 0% duty cycle; VIL = 0.V maximum; VIH =.0V minimum. STATIC OTES:. V = V minimum, V maximum.. V = V minimum, V maximum.. V = -V maximum, -V minimum.. R, R = k, %, / or /W (per socket).. C, C = 0.0 F minimum (per socket) or 0. F minimum (per row).. D, D = 00 or equivalent (per board). Irradiation Circuit k +V C +V -V k 0 +V F Rev..00 age of

6 Die Characteristics DIE DIMESIOS:. mils x mils x mils ITERFACE MATERIALS: Glassivation: Type: itride Thickness: kå 0.kÅ Top Metallization: Type: Al Thickness: kå kå Substrate: CMOS, DI ASSEMBLY RELATED IFORMATIO: Substrate otential: Unbiased (DI) ADDITIOAL IFORMATIO: Worst Case Current Density:. x A/cm Transistor Count: HS-0 - HS-0 - Metallization Mask Layout E HS-0RH A A A V REF GD E HS-0RH A A C V REF GD I I I A I B I I I A I B I I I A I B I I I A I B I I I A I B I I I A I B I I I A I B I I I A I B -V +V C -V A +V B F Rev..00 age of

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