DATASHEET ISL7457SRH. Features. Related Literature. Applications. Radiation Hardened, SEE Hardened, Non-Inverting, Quad CMOS Driver

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1 DATASHEET ISL747SRH Radiation Hardened, SEE Hardened, Non-Inverting, Quad CMOS Driver FN6874 Rev.3.00 The ISL747SRH is a radiation hardened, SEE hardened, high speed, non-inverting, quad CMOS driver. It is capable of running at clock rates up to 40MHz and features 2A typical peak drive capability and a nominal ON-resistance of just 3.Ω. The ISL747SRH is ideal for driving highly capacitive loads, such as storage and vertical clocks in CCD applications. It is also well suited to level-shifting and clock-driving applications. Each output of the ISL747SRH can be switched to either the high (V H ) or low (V L ) supply pins, depending on the related input pin. The inputs are compatible with both 3.3V and V CMOS logic. The Output Enable (OE) pin can be used to put the outputs into a high-impedance state. This is especially useful in CCD applications that disable the driver during power-down. The ISL747SRH also features very fast rise and fall times, which are typically matched to within 1ns. The propagation delay is also matched between rising and falling edges to typically within 1.ns. The ISL747SRH is available in a 16 Ld ceramic flatpack package and specified for operation across the full - C to + C ambient temperature range. Related Literature For a full list of related documents, visit our website ISL747SRH product page Applications CCD drivers, clock/line drivers, level-shifters Features Electrically screened to SMD QML qualified per MIL-PRF-383 requirements Full mil-temp range operation: T A = - C to + C Radiation hardness TID [0-300 rad(si)/s]: krad(si) minimum SEE hardness LET (SEL and SEB Immunity): 40MeV/mg/cm 2 minimum LET [SET = V OUT < 1V, t < 00ns]: 40MeV/mg/cm 2 4 channels Clocking speeds up to 40MHz 11ns/ns typical t R /t F with 1nF Load (1V bias) 1ns typical rise and fall time match (1V bias) 1.ns typical prop delay match (1V bias) Low quiescent current - < 1mA Typical Fast output enable function - ns typical (1V bias) Wide output voltage range 0V V L 8V 2.V V H 16.V 2A typical peak drive current (1V Bias) 3.Ω typical ON-resistance (1V bias) Input level shifters 3.3V/V CMOS compatible inputs OE V H V S+ INx GND LEVEL SHIFTER 3-STATE CONTROL OUTx V S- V L Figure 1. Block Diagram FN6874 Rev.3.00 Page 1 of 16

2 1. Overview 1. Overview 1.1 Ordering Information Ordering SMD Number (Note 1) Part Number (Note 2) Temp. Range ( C) Package (RoHS Compliant) Pkg. Dwg. # 962D QXC ISL747SRHQF - to + 16 Ld Flatpack K16.A 962D VXC ISL747SRHVF - to + 16 Ld Flatpack K16.A 962D V9A ISL747SRHVX - to + Die NA ISL747SRHF/PROTO (Note 3) - to + 16 Ld Flatpack K16.A NA ISL747SRHX/SAMPLE (Note 3) - to + Die Notes: 1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. 2. These Intersil Pb-free Hermetic packaged products employ 0% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the temperature range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE die is capable of meeting the electrical limits and conditions specified in the DLA SMD at +2 C only. The /SAMPLE is a die and does not receive 0% screening across the temperature range to the DLA SMD electrical limits. These part types do not come with a certificate of conformance because there is no radiation assurance testing and they are not DLA qualified devices. 1.2 Pin Configuration ISL747SRH (16 Ld Flatpack) Top View INA 1 16 V S + OE 2 1 OUTA INB 3 14 OUTB V L 4 13 NC GND V H NC 6 11 OUTC INC 7 OUTD IND 8 9 V S - FN6874 Rev.3.00 Page 2 of 16

3 1. Overview 1.3 Pin Descriptions Pin Number Pin Name Function Equivalent Circuit 1 INA Input Channel A V S + V S + INx V S - V S - CIRCUIT 1 2 OE Output enable (Reference Circuit 1) 3 INB Input Channel B (Reference Circuit 1) 4 V L Low voltage input pin GND Input logic ground 6, 13 NC No connection 7 INC Input Channel C (Reference Circuit 1) 8 IND Input Channel D (Reference Circuit 1) 9 V S - Negative supply voltage OUTD Output Channel D V H V S + OUTx V S - V S - 11 OUTC Output Channel C (Reference Circuit 2) V H High voltage input pin 14 OUTB Output Channel B (Reference Circuit 2) 1 OUTA Output Channel A (Reference Circuit 2) 16 V S + Positive supply voltage CIRCUIT 2 V L FN6874 Rev.3.00 Page 3 of 16

4 2. Specifications 2. Specifications 2.1 Absolute Maximum Ratings Parameter Minimum Maximum Unit Supply Voltage (+Vs to -Vs) 18 V Input Voltage -Vs Vs +0.3 V Input Current ma Continuous Output Current per Output 0 ma Power Dissipation (P D T A = +2 C (Derate linearly at.1mw/ C above T A = +2 C) 1.26 W T A = + C (Derate linearly at.1mw/ C above T A = + C) 0.2 W T C = +2 C (Derate linearly at 66.7mW/ C above T C = +2 C) 8.33 W T C = + C (Derate linearly at 66.7mW/ C above T C = + C) 1.66 W ESD Rating Value Unit Human Body Model 1 kv Charged Device Model 1. kv CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. 2.2 Thermal Information Thermal Resistance (Typical) JA ( C/W) JC ( C/W) 16 Ld Flatpack (Notes 4, ) 99 1 Notes: 4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board. See TB379.. For JC, the case temp location is the center of the package underside. Parameter Minimum Maximum Unit Maximum Junction Temperature +10 C Maximum Storage Temperature Range C 2.3 Recommended Operation Conditions Parameter Minimum Maximum Unit Supply Voltage (+Vs to -Vs) V Ambient Operating Temperature Range - + C FN6874 Rev.3.00 Page 4 of 16

5 2. Specifications 2.4 Electrical Specifications Typical values reflect V S + = V H = V, V S - = V L = 0V, OE = V S +, T A = +2 C, unless otherwise specified. Parameter Description Test Conditions Min Typ Max Units Input V IH Logic 1 Input Voltage 1.3 V I IH Logic 1 Input Current INx = V S + na V IL Logic 0 Input Voltage 1.23 V I IL Logic 0 Input Current INx = 0V - na C IN Input Capacitance.7 pf R IN Input Resistance 00 MΩ Output R OH ON-Resistance V H to OUTx INx = V S +, I OUTx = -0mA 8 Ω R OL ON-Resistance V L to OUTx INx = 0V, I OUTx = +0mA 6 Ω I LEAK+ Positive Output Leakage Current INx = V S +, OE = 0V, OUTx = V S + na I LEAK- Negative Output Leakage Current INx = V S +, OE = 0V, OUTx = V S - - na Power Supply I S+ V S + Supply Current INx = 0V and V S ma I S- V S - Supply Current INx = 0V and V S ma I H V H Supply Current INx = 0V and V S µa I L V L Supply Current INx = 0V and V S µa Switching Characteristics t R Rise Time INx = 0V to 4.V step, C L = 1nF 23 ns t F Fall Time INx = 4.V to 0V step, C L = 1nF 20 ns t RF t R, t F Mismatch C L = 1nF 3 ns t D + Turn-On Delay Time INx = 0V to 4.V step, C L = 1nF 20 ns t D - Turn-Off Delay Time INx = 4.V to 0V step, C L = 1nF 22 ns t DD t D +, t D - Mismatch C L = 1nF 2 ns t ENABLE Enable Delay Time INx = V S +, OE = 0V to 4.V step, R L = 1kΩ 21 ns t DISABLE Disable Delay Time INx = V S +, OE = 4.V to 0V step, R L = 1kΩ 46 ns FN6874 Rev.3.00 Page of 16

6 2. Specifications Typical values reflect V S + = V H = 1V, V S - = V L = 0V, OE = V S +, T A = +2 C, unless otherwise specified. Parameter Description Test Conditions Min Typ Max Units Input V IH Logic 1 Input Voltage 1.63 V I IH Logic 1 Input Current INx = V S + na V IL Logic 0 Input Voltage 1.4 V I IL Logic 0 Input Current INx = 0V - na C IN Input Capacitance.7 pf R IN Input Resistance 1. GΩ Output R OH ON-Resistance V H to OUTx INx = V S +, I OUTx = -0mA 3. Ω R OL ON-Resistance V L to OUTx INx = 0V, I OUTx = +0mA 3 Ω I LEAK+ Positive Output Leakage Current INx = V S +, OE = 0V, OUTx = V S + 1 na I LEAK- Negative Output Leakage Current INx = V S +, OE = 0V, OUTx = V S - -1 na Power Supply I S+ V S + Supply Current INx = 0V and V S ma I S- V S - Supply Current INx = 0V and V S ma I H V H Supply Current INx = 0V and V S µa I L V L Supply Current INx = 0V and V S µa Switching Characteristics t R Rise Time INx = 0V to V step, C L = 1nF 11 ns t F Fall Time INx = V to 0V step, C L = 1nF ns t RF t R, t F Mismatch C L = 1nF 1 ns t D + Turn-On Delay Time INx = 0V to V step, C L = 1nF 11. ns t D - Turn-Off Delay Time INx = V to 0V step, C L = 1nF 13 ns t DD t D +, t D - Mismatch C L = 1nF 1. ns t ENABLE Enable Delay Time INx = V S +, OE = 0V to V step, R L = 1kΩ ns t DISABLE Disable Delay Time INx = V S +, OE = V to 0V step, R L = 1kΩ 27 ns FN6874 Rev.3.00 Page 6 of 16

7 3. Typical Performance Curves (Pre-Rad) 3. Typical Performance Curves (Pre-Rad) INPUT VOLTAGE (V) 1.8 T A = ±1 C HIGH LIMIT = 2.4V HYSTERESIS 1.2 SUPPLY CURRENT (ma) T A = ±2 C ALL INPUTS = 0V ALL INPUTS = V S+ LOW LIMIT = 0.8V SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 1 Figure 2. Switch Threshold vs Supply Voltage Figure 3. Quiescent Supply Current vs Supply Voltage 9 8 I OUT = 0mA T A = +2 C 2 ON RESISTANCE (Ω) V L TO OUT V H TO OUT RISE/FALL TIME (ns) 20 1 t F t R SUPPLY VOLTAGE (V) 1 C L = 1nF T A = +2 C 7 SUPPLY VOLTAGE (V) 1 Figure 4. ON-Resistance vs Supply Voltage Figure. Rise/Fall Time vs Supply Voltage RISE/FALL TIME (ns) C L = 1nF V S+ = 1V t F tr PROPAGATION DELAY TIME (ns) t D+ t D- C L = 1nF T A = +2 C TEMPERATURE ( C) SUPPLY VOLTAGE (V) Figure 6. Rise/Fall Time vs Temperature Figure 7. Propagation Delay Time vs Supply Voltage FN6874 Rev.3.00 Page 7 of 16

8 3. Typical Performance Curves (Pre-Rad) PROPAGATION DELAY TIME (ns) C L = 1nF V S+ = 1V t D- t D+ RISE/FALL TIME (ns) V S+ = 1V T A = +2 C t F t R TEMPERATURE ( C) k 2.2k 4.7k LOAD CAPACITANCE (pf) k Figure 8. Propagation Delay Time vs Temperature Figure 9. Rise/Fall Time vs Load Capacitance SUPPLY CURRENT (ma) V S+ = V H = V V S- = V L = 0V f = 0kHz T A = +2 C k 1k LOAD CAPACITANCE (pf) k OPERATING FREQUENCY(MHz) V S+ = 1V.. T J = +10 C.. T J = + C LOAD CAPACITANCE (pf) k Figure. Supply Current Per Channel vs Load Capacitance Figure 11. Operating Frequency vs Load Capacitance Derating Curves 0 V V 1V 00 V V 1V SUPPLY CURRENT (ma) 1 V S+ = V H V S- = V L = 0V C L = pf T A = +2 C SUPPLY CURRENT (ma) 0 V S+ = V H V S- = V L = 0V C L = 1nF T A = +2 C M 0.3M 0.M 1M 3M M 1 0.1M 0.3M 0.M 1M 3M M INPUT SWITCHING FREQUENCY (Hz) INPUT SWITCHING FREQUENCY (Hz) Figure. Supply Current for All 4 Channels vs Voltage and Switching Frequency Figure 13. Supply Current for All 4 Channels vs Voltage and Switching Frequency FN6874 Rev.3.00 Page 8 of 16

9 3. Typical Performance Curves (Pre-Rad) Table 1. Operating Voltage Range Pin Minimum Maximum V S + to V S - 4.V 16.V V S - to GND 0V 0V V H V S V V S + V L V S - V S + V H to V L 0V 16.V V L to V S - 0V 8V V INPUT 2.V 0 OUTPUT 90% % t D + t D - t R t F Figure 14. Timing Diagram V S+ 0.1µF 4.7µF V S+ kω INA OE nF OUTA INB V L 4.7µF 0.1µF nF 0.1µF V H 4.7µF OUTB INC nF OUTC IND 8 9 1nF OUTD Figure 1. Standard Test Configuration FN6874 Rev.3.00 Page 9 of 16

10 4. Application Information 4. Application Information 4.1 Product Description The ISL747SRH is a high performance, high speed quad CMOS driver. Each channel of the ISL747SRH consists of a single P-channel high-side driver and a single N-channel low-side driver. These 3.Ω devices will pull the output (OUTx) to either the high or low voltage, on V H and V L respectively, depending on the input logic signal (INx). It should be noted that there is only one set of high and low voltage pins. A common Output Enable (OE) pin is available on the ISL747SRH. When this pin is pulled low, it will put all outputs in a high impedance state. 4.2 Supply Voltage Range and Input Compatibility The ISL747SRH is designed to operate on nominal V to 1V supplies with ±% tolerance. Table 1 on page 9 shows the specifications for the relationship between the V S +, V S -, V H, V L, and GND pins. The ISL747SRH does not contain a true analog switch and therefore V L should always be less than V H. All input pins are compatible with both 3.3V and V CMOS signals. 4.3 PCB Layout Guidelines (1) A ground plane must be used, preferably located on layer #2 of the PCB. (2) Connect the GND and V S - pins directly to the ground plane. (3) The V S +, V H and V L pins should be bypassed directly to the ground plane using a low-esr, 4.7µF solid tantalum capacitor in parallel with a 0.1µF ceramic capacitor. Locate all bypass capacitors as close as possible to the respective pins of the IC. (4) Keep all input and output connections to the IC as short as possible. () For high frequency operation above 1MHz, consider use of controlled impedance traces terminated into 0 on all inputs and outputs. 4.4 Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the ISL747SRH drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation, die temperature must be kept below T JMAX (+10 C). Power dissipation can be calculated as shown in (EQ. 1): P D = V S I S + C INT V S f + C L V OUT f 1 (EQ. 1) where: P D is the power dissipated in the device. V S is the total power supply to the ISL747SRH (from V S + to V S -). I S is the quiescent supply current. C INT is the internal load capacitance (10pF). f is the operating frequency. C L is the load capacitance. V OUT is the swing on the output (V H - V L ). FN6874 Rev.3.00 Page of 16

11 4. Application Information 4. Junction Temperature Calculation After the power dissipation for the application is determined, the maximum junction temperature can be calculated as shown in (EQ. 2): T JMAX = T SMAX + JC + CS P D (EQ. 2) where: T JMAX is the maximum operating junction temperature (+10 C). T SMAX is the maximum operating sink temperature of the PCB. JC is the thermal resistance, junction-to-case, of the package. CS is the thermal resistance, case-to-sink, of the PCB. P D is the power dissipation calculated in (EQ. 1). 4.6 PCB Thermal Management To minimize the case-to-sink thermal resistance, it is recommended that multiple vias be placed on the top layer of the PCB directly underneath the IC. The vias should be connected to the ground plane, which functions as a heatsink. A gap filler material (for example, a Sil-Pad or thermally conductive epoxy) can be used to ensure good thermal contact between the bottom of the IC and the vias. FN6874 Rev.3.00 Page 11 of 16

12 . Die Characteristics. Die Characteristics Die Information Dimensions Interface Materials Glassivation Table 2. Die and Assembly Related Information 2390µm x 244µm (94.1 mils x 96.3 mils) Thickness:13.0 mils ±0. mil Type: PSG and Silicon Nitride Thickness: 0.µm ±0.0µm to 0.7µm ±0.0µm Top Metallization Type: AlCuSi (1%/0.%) Thickness: 1.0µm ±0.1µm Substrate Type: Silicon Isolation: Junction Backside Finish Silicon Assembly Information Substrate Potential V s - Additional Information Worst Case Current Density < 2x A/cm 2 Transistor Count Metallization Mask Layout INA ISL747SRH V S + OE OUTA INB OUTB V L V H GND OUTC OUTD INC IND V S - FN6874 Rev.3.00 Page of 16

13 . Die Characteristics.2 Layout Characteristics Step and Repeat: 2390µm x 244µm The DELAY pad is not bonded. Pad Name X (µm) Table 3. Layout X-Y Coordinates Y (µm) DX (µm) DY (µm) IND Probes Per Pad V S OUTD OUTC V H OUTB OUTA V S INA OE INB V L GND INC FN6874 Rev.3.00 Page 13 of 16

14 6. Revision History 6. Revision History Rev. Date Description 3.00 Applied new formatting. Updated Related Literature section. Added Note 3. Added Figures and 13. Updated Table 3 to fix V H and V L Y-coordinates and remove DELAY. Added Absolute Maximum Ratings, Thermal Information, Recommended Operation Conditions, Revision History, and About Intersil sections. FN6874 Rev.3.00 Page 14 of 16

15 7. Package Outline Drawing 7. Package Outline Drawing K16.A 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE Rev 2, 1/ 0.01 (0.38) (0.20) PIN NO. 1 ID OPTIONAL 1 2 For the most recent package outline drawing, see K16.A (1.27 BSC) PIN NO. 1 ID AREA (11.18) MAX 0.00 (0.13) MIN (0.6) 0.01 (0.38) TOP VIEW 0.11 (2.92) 0.04 (1.14) 0.04 (1.14) (0.66) (7.24) 0.24 (6.22) -D (0.23) (0.) SEATING AND BASE PLANE 0.13 (3.30) MIN LEAD FINISH (9.40) 0.20 (6.3) 0.03 (0.76) MIN -C- -H- SIDE VIEW NOTES: (0.1) (0.) LEAD FINISH 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. Alternately, a tab may be used to identify pin one. BASE METAL (0.48) 0.01 (0.38) (0.04) MAX (0.6) 0.01 (0.38) SECTION A-A (0.23) (0.) 2. If a pin one identification mark is used in addition to a tab, the limits of the tab dimension do not apply. 3. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 4. Measure dimension at all four corners.. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 6. Dimension shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension minimum shall be reduced by inch (0.038mm) maximum when solder dip lead finish is applied Dimensioning and tolerancing per ANSI Y14.M Controlling dimension: INCH. FN6874 Rev.3.00 Page 1 of 16

16 8. About Intersil 8. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at For a listing of definitions and abbreviations of common terms used in our documents, visit: You can report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN6874 Rev.3.00 Page 16 of 16