Features NUMBER OF RS-232 RECEIVERS

Transcription

1 DATASHEET HIN, HIN, HIN, HIN, HIN, HIN0, HIN V Powered RS- Transmitters/Receivers FN Rev.00 The HIN-HIN family of RS- transmitters/receivers interface circuits meet all ElA RS-E and V. specifications, and are particularly suited for those applications where ±V is not available. They require a single V power supply (except HIN) and feature onboard charge pump voltage converters which generate V and -V supplies from the V supply. The family of devices offer a wide variety of RS- transmitter/receiver combinations to accommodate various applications (see Selection Table on page ). The drivers feature true TTL/CMOS input compatibility, slew-rate-limited output, and 00 power-off source impedance. The receivers can handle up to ±0V, and have a k to k input impedance. The receivers also feature hysteresis to greatly improve noise rejection. Features Meets All RS-E and V. Specifications Requires Only Single V Power Supply - (V and V - HIN) High Data Rate kbps Onboard Voltage Doubler/Inverter Low Power Consumption Low Power Shutdown Function Three-State TTL/CMOS Receiver Outputs Multiple Drivers - ±V Output Swing for V lnput - 00 Power-Off Source Impedance - Output Current Limiting - TTL/CMOS Compatible - 0V/µs Maximum Slew Rate Multiple Receivers - ±0V Input Voltage Range - k to k Input Impedance - 0.V Hysteresis to Improve Noise Rejection Pb-free Available (RoHS compliant) Applications Any System Requiring RS- Communication Ports - Computer - Portable, Mainframe, Laptop - Peripheral - Printers and Terminals - Instrumentation - Modems Selection Table PART NUMBER POWER SUPPLY VOLTAGE NUMBER OF RS- DRIVERS NUMBER OF RS- RECEIVERS EXTERNAL COMPONENTS LOW POWER SHUTDOWN/TTL THREE-STATE NUMBER OF LEADS HIN V Capacitors No/No HIN V Capacitors Yes/Yes HIN V Capacitors No/No HIN V Capacitors No/No HIN V and.v to.v Capacitors No/Yes HIN0 V Capacitors Yes/Yes HIN V Capacitors Yes/Yes FN Rev.00 Page of

2 Pin Descriptions PIN FUTION Power Supply Input V ±%. V Internally generated positive supply (V nominal), HIN requires.v to.v. Internally generated negative supply (-V nominal). GND Ground lead. Connect to 0V. C External capacitor ( terminal) is connected to this lead. C- External capacitor (- terminal) is connected to this lead. C External capacitor ( terminal) is connected to this lead. C- External capacitor (- terminal) is connected to this lead. T IN T OUT R IN R OUT EN SD Transmitter Inputs. These leads accept TTL/CMOS levels. An internal 00k pull-up resistor to is connected to each lead. Transmitter Outputs. These are RS- levels (nominally ±V). Receiver Inputs. These inputs accept RS- input levels. An internal pull-down resistor to GND is connected to each input. Receiver Outputs. These are TTL/CMOS levels. Enable input. This is an active low input which enables the receiver outputs. With EN = V, the receiver outputs are placed in a high impedance state. Shutdown Input. With SD = V, the charge pump is disabled, the receiver outputs are in a high impedance state and the transmitters are shut off. No Connect. No connections are made to these leads. FN Rev.00 Page of

3 Ordering Information PART NUMBER HIBZ* (Note) HIPZ (Note) HINIBZ* (Note) HINIPZ (Note) HIBZ (No longer available or supported recommended replacement part ICLE) (Note) HIBZ* (No longer available or supported recommended replacement part ICLE) (Note) PART MARKING TEMP. RANGE ( C) HIBZ 0 to 0 Ld SOIC HIPZ 0 to 0 Ld PDIP** HINIBZ -0 to Ld SOIC HINIPZ -0 to Ld PDIP** HIBZ 0 to 0 Ld SOIC HIBZ 0 to 0 Ld SOIC HIBZ*(Note) HIBZ 0 to 0 Ld SOIC HINIBZ* (Note) HINCBZ* (Note) HINCPZ (Note) HIN0CNZ* (No longer available or supported) (Note) HIAZ (No longer available or supported) (Note) HIBZ* (No longer available or supported) (Note) HINIBZ (No longer Available or supported) (Note) HINIBZ -0 to Ld SOIC HINCBZ 0 to 0 Ld SOIC HINCPZ 0 to 0 Ld PDIP** HIN0CNZ 0 to 0 Ld MQFP HIAZ 0 to 0 Ld SSOP HIBZ 0 to 0 Ld SOIC HINIBZ -0 to Ld SOIC PACKAGE M. E. M. E. M. M. M. M. M. E. Q.X M.0 M. M. PKG. DWG. # *Add -T suffix for tape and reel. Please refer to TB for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 0% matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-00. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. FN Rev.00 Page of

4 Pinouts HIN ( LD PDIP, SOIC) TOP VIEW HIN ( LD SOIC) TOP VIEW C V C- C C- T OUT R IN GND T OUT R IN R OUT T IN T IN R OUT T OUT T OUT T OUT R IN R OUT T IN T IN GND 0 T OUT R IN R OUT SD EN T IN T IN R OUT R IN C V C- C- C V V NOTE NOTE T IN T IN R OUT C C µf V 00k V 00k V TO V VOLTAGE DOUBLER V TO -V VOLTAGE INVERTER T T R V NOTE NOTE T OUT T OUT R IN µf µf T IN T IN T IN T IN R OUT C- C- C V TO V C- VOLTAGE DOUBLER C V TO -V VOLTAGE INVERTER C- T T V V T 00k V T 00k V 00k V 00k R µf µf T OUT T OUT T OUT T OUT R IN R OUT R R IN R OUT R OUT EN 0 R R R IN R IN SD NOTE:. Either 0.µF or µf capacitors may be used. FN Rev.00 Page of

5 Pinouts (Continued) HIN ( LD SOIC) TOP VIEW HIN ( LD PDIP, SOIC) TOP VIEW T OUT T OUT T OUT T OUT T OUT R IN T OUT R IN T OUT R OUT R IN R OUT R IN T IN R OUT T IN R OUT 0 T OUT T IN 0 T OUT T IN T IN R OUT T IN T IN T IN R IN T IN GND R OUT GND R OUT R IN R IN C C V C- V C- C- C C- C µf µf T IN V 00k T V µf µf T OUT µf µf T IN V C V TO V C- VOLTAGE DOUBLER C V TO -V VOLTAGE INVERTER C- V C V TO V C- VOLTAGE DOUBLER C V TO -V C- VOLTAGE INVERTER V 00k T V µf µf T OUT T IN V 00k T T OUT T IN V 00k T T OUT T IN V T 00k T OUT T IN V T 00k T OUT T IN V T 00k T OUT T IN V T 00k 0 T OUT T IN R OUT R OUT R OUT V T 00k 0 R R R T OUT R IN R IN R IN R OUT R OUT R OUT R OUT R R R R R IN R IN R IN R IN FN Rev.00 Page of

6 Pinouts (Continued) HIN ( LD PDIP, SOIC) TOP VIEW HIN0 ( LD MQFP) TOP VIEW R OUT T IN SD EN R IN T IN GND R OUT V C 0 R IN T OUT T OUT 0 T IN R OUT C- R IN R IN 0 R OUT T OUT R IN R OUT R OUT R IN T IN EN T OUT T OUT T OUT T OUT R IN 0 GND T OUT R IN R OUT T IN T IN R OUT R IN C- C C- V C R OUT T IN T IN R OUT R IN FN Rev.00 Page of

7 Pinouts (Continued) T IN T IN R OUT R OUT R OUT R OUT R OUT EN V 00k T 0 V T 00k R R R R R NOTE: For V > V, use C 0.µF. T OUT T OUT R IN R IN R IN R IN R IN µf µf T IN T IN T IN T IN T IN R OUT R OUT R OUT R OUT R OUT EN V V TO V VOLTAGE DOUBLER V TO -V VOLTAGE INVERTER V 00k V 00k T T V V T 00k V T 00k R R R R R 0 V T 00k 0 SD µf µf T OUT T OUT T OUT T OUT T OUT R IN R IN R IN R IN R IN HIN ( SOIC, SSOP) TOP VIEW 0 V.V TO.V (NOTE) C µf V TO -V V (NOTE) C- VOLTAGE INVERTER µf V T 00k T IN T OUT C C- C C- T OUT T OUT T OUT R IN R OUT T IN T IN R OUT R IN GND C V C- T OUT R IN R OUT SD EN R IN R OUT T IN T IN R OUT R IN C- C FN Rev.00 Page of

8 Pinouts (Continued) µf µf T IN V C V TO V C- VOLTAGE DOUBLER C V TO -V VOLTAGE INVERTER C- V 00k T V µf µf T OUT T IN V 00k T T OUT T IN V T 0 00k T OUT T IN R OUT V T 00k R T OUT R IN R OUT R OUT R R R IN R IN R OUT R R IN R OUT EN R SD R IN FN Rev.00 Page of

9 Absolute Maximum Ratings to Ground (GND -0.V) < < V V to Ground (Note ( -0.V) < V <.V to Ground V < < (GND 0.V) V to V Input Voltages T IN V < V IN < (V 0.V) R IN V Output Voltages T OUT ( -0.V) < V TXOUT < (V 0.V) R OUT (GND -0.V) < V RXOUT < (V 0.V) Short Circuit Duration T OUT Continuous R OUT Continuous Operating Conditions Temperature Range HINxxcx C to 0 C HINxxIx C to C Thermal Information Thermal Resistance (Typical, Note ) JC ( C/W) Ld PDIP Package* 0 Ld PDIP Package Ld SOIC Package Ld SOIC Package Ld SOIC Package Ld SSOP Package Ld MQFP Package Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to 0 C Pb-free Reflow Profile see link below *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE:. Only HIN. For V > V, C must be 0.µF.. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB for details. Electrical Specifications Test Conditions: = V ±%, T A = Operating Temperature Range PARAMETER TEST CONDITIONS MIN (Note ) TYP MAX (Note ) UNITS SUPPLY CURRENTS Power Supply Current, I CC V Power Supply Current, I CC No Load, T A = C No Load, T A = C No Load, T A = C HIN - ma HIN-HIN, HIN0-HIN - ma HIN - 0. ma HIN -.0 ma Shutdown Supply Current, I CC (SD) T A = C - µa LOGIC AND TRANSMITTER INPUTS, RECEIVER OUTPUTS Input Logic Low, V ll T IN, EN, Shutdown V Input Logic High, V lh T IN V EN, Shutdown. - - V Transmitter Input Pull-up Current, I P T IN = 0V - 00 µa TTL/CMOS Receiver Output Voltage Low, V OL I OUT =.ma V TTL/CMOS Receiver Output Voltage High, V OH I OUT = -.0mA.. - V RECEIVER INPUTS RS- Input Voltage Range V IN -0-0 V Receiver Input Impedance R IN V IN = ±V k Receiver Input Low Threshold, V ln (H-L) = V, T A = C V Receiver Input High Threshold, V IN (L-H) = V, T A = C -.. V Receiver Input Hysteresis V HYST V FN Rev.00 Page of

10 Electrical Specifications Test Conditions: = V ±%, T A = Operating Temperature Range (Continued) PARAMETER TEST CONDITIONS MIN (Note ) TYP MAX (Note ) UNITS TIMING CHARACTERISTICS Baud Rate ( Transmitter Switching) R L = k kbps Output Enable Time, t EN HIN, HIN, HIN0, HIN ns Output Disable Time, t DIS HIN, HIN, HIN0, HIN ns Propagation Delay, t PD RS- to TTL µs Instantaneous Slew Rate SR C L = pf, R L = k, T A = C (Note ) V/µs Transition Region Slew Rate, SR T R L = k, C L = 00pF Measured from V to -V or -V to V, Transmitter Switching - - V/µs TRANSMITTER OUTPUTS Output Voltage Swing, T OUT Transmitter Outputs, k to Ground ± ± ± V Output Resistance, T OUT = V = = 0V, V OUT = V RS- Output Short Circuit Current, I SC T OUT shorted to GND - ± - ma NOTE:. Limits established by characterization and are not production tested.. Parameters with MIN and/or MAX limits are 0% tested at C, unless otherwise specified. Temperature limits established by characterization and are not production tested. VOLTAGE DOUBLER VOLTAGE INVERTER S C S V = S C S GND GND - C - C - C - C GND S C- S S C - S = -(V) RC OSCILLATOR FIGURE. CHARGE PUMP Detailed Description The HIN thru HIN family of RS- transmitters/receivers are powered by a single V power supply (except HIN), feature low power consumption, and meet all ElA RS-C and V. specifications. The circuit is divided into three sections: The charge pump, transmitter, and receiver. Charge Pump An equivalent circuit of the charge pump is illustrated in Figure. The charge pump contains two sections: the voltage doubler and the voltage inverter. Each section is driven by a two-phase, internally generated clock to generate V and -V. The nominal clock frequency is khz. During phase one of the clock, capacitor C is charged to. During phase two, the voltage on C is added to, producing a signal across C equal to twice. During phase one, C is also charged to, and then during phase two, it is inverted with respect to ground to produce a signal across C equal to -. The charge pump accepts input voltages up to.v. The output impedance of the voltage doubler section (V) is approximately 00, and the output impedance of the voltage inverter section () is approximately 0. A typical application uses µf capacitors for C-C, however, the value is not critical. Increasing the values of C and C will lower the output impedance of the voltage doubler and inverter, increasing the values of the reservoir capacitors, C and C, lowers the ripple on the V and supplies. During shutdown mode (HIN, HIN0 and HIN), SHUTDOWN control line set to logic, the charge pump is turned off, V is pulled down to, is pulled up to GND, and the supply current is reduced to less than µa. The transmitter outputs are disabled and the receiver outputs are placed in the high impedance state. FN Rev.00 Page of

11 Transmitters The transmitters are TTL/CMOS compatible inverters which translate the inputs to RS- outputs. The input logic threshold is about % of, or.v for = V. A logic at the input results in a voltage of between -V and at the output, and a logic 0 results in a voltage between V and (V -0.V). Each transmitter input has an internal 00k pullup resistor so any unused input can be left unconnected and its output remains in its low state. The output voltage swing meets the RS-C specifications of ±V minimum with the worst case conditions of: all transmitters driving k minimum load impedance, =.V, and maximum allowable operating temperature. The transmitters have an internally limited output slew rate which is less than 0V/µs. The outputs are short circuit protected and can be shorted to ground indefinitely. The powered down output impedance is a minimum of 00 with ±V applied to the outputs and = 0V. Receivers The receiver inputs accept up to ±0V while presenting the required k to k input impedance even if the power is off ( = 0V). The receivers have a typical input threshold of.v which is within the ±V limits, known as the transition region, of the RS- specifications. The receiver output is 0V to. The output will be low whenever the input is greater than.v and high whenever the input is floating or driven between 0.V and -0V. The receivers feature 0.V hysteresis to improve noise rejection. The receiver Enable line EN, when set to logic, (HIN, HIN, HIN0, and HIN) disables the receiver outputs, placing them in the high impedance mode. The receiver outputs are also placed in the high impedance state when in shutdown mode. V T XIN GND < T XIN < 00k 00 T OUT < V TOUT < V R XIN -0V < R XIN < 0V GND R OUT GND < V ROUT < FIGURE. TRANSMITTER FIGURE. RECEIVER T IN OR R IN T OUT OR R OUT V OL V OL t PHL t PLH AVERAGE PROPAGATION DELAY = t PHL t PLH FIGURE. PROPAGATION DELAY DEFINITION FN Rev.00 Page of

12 Typical Performance Curves SUPPLY VOLTAGE µf 0.µF 0.µF SUPPLY VOLTAGE ( V ) T A = C TRANSMITTER OUTPUTS OPEN CIRCUIT ( =.V) V ( = V) ( = V) V ( =.V) I LOAD (ma) 0 FIGURE. SUPPLY VOLTAGE vs, VARYING CAPACITORS FIGURE. V, OUTPUT VOLTAGE vs LOAD (HIN) Test Circuits (HIN) k µf C µf C - µf C µf C GND T OUT R IN R OUT T IN T IN.V TO.V INPUT k T OUTPUT RS- 0V INPUT TTL/CMOS OUTPUT TTL/CMOS INPUT TTL/CMOS INPUT C V C- C C- T OUT C V C- C C- T OUT R IN GND T OUT R IN R OUT T IN T IN R OUT T OUTPUT RS- 0V INPUT R IN R OUT TTL/CMOS OUTPUT R OUT = V IN /T OUT T OUT V IN = V A FIGURE. GENERAL TEST CIRCUIT FIGURE. POWER-OFF SOURCE RESISTAE CONFIGURATION FN Rev.00 Page of

13 Applications The HINxx may be used for all RS- data terminal and communication links. It is particularly useful in applications where V power supplies are not available for conventional RS- interface circuits. The applications presented represent typical interface configurations. A simple duplex RS- port with CTS/RTS handshaking is illustrated in Figure. Fixed output signals such as DTR (data terminal ready) and DSRS (data signaling rate select) is generated by driving them through a resistor connected to V. In applications requiring four RS- inputs and outputs (Figure ), note that each circuit requires two charge pump capacitors (C and C) but can share common reservoir capacitors (C and C). The benefit of sharing common reservoir capacitors is the elimination of two capacitors and the reduction of the charge pump source impedance which effectively increases the output swing of the transmitters. V C µf - C µf - TD TTL/CMOS RTS INPUTS AND OUTPUTS RD CTS R T HIN R T - - DTR (0) DATA TERMINAL READY DSRS () DATA SIGNALING RATE SELECT RS- INPUTS AND OUTPUTS TD () TRANSMIT DATA RTS () REQUEST TO SEND RD () RECEIVE DATA CTS () CLEAR TO SEND SIGNAL GROUND () FIGURE. SIMPLE DUPLEX RS- PORT WITH CTS/RTS HANDSHAKING TTL/CMOS INPUTS AND OUTPUTS C µf - TD RTS RD CTS HIN T T R R C - µf TD () TRANSMIT DATA RTS () REQUEST TO SEND RD () RECEIVE DATA CTS () CLEAR TO SEND C - µf V C µf - V RS- INPUTS AND OUTPUTS TTL/CMOS INPUTS AND OUTPUTS C µf - DTR DSRS DCD R HIN T T R R C - µf DTR (0) DATA TERMINAL READY DSRS () DATA SIGNALING RATE SELECT DCD () DATA CARRIER DETECT R () RING INDICATOR SIGNAL GROUND () FIGURE. COMBINING TWO HINs FOR PAIRS OF RS- INPUTS AND OUTPUTS FN Rev.00 Page of

14 Die Characteristics SUBSTRATE POTENTIAL V Metallization Mask Layout HIN0 TRANSISTOR COUNT T OUT T OUT T OUT T OUT R IN R OUT T IN R IN SHUTDOWN R OUT EN T IN T IN T OUT R OUT R IN R IN R OUT GND T IN T IN R OUT R IN C C V C- C- FN Rev.00 Page of

15 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN. Added Rev History beginning with Rev. Added About Intersil Verbiage Updated Ordering Information Table on page. Updated POD M. to most current version change is as follows: Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing. Added Land Pattern. Updated POD M. to most current version change is as follows: Added land pattern About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at FN Rev.00 Page of

16 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M-.. Symbols are defined in the MO Series Symbol List in Section. of Publication No... Dimensions A, A and L are measured with the package seated in JE- DEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.0 inch (0.mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.0 inch (0.mm).. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ ) for E., E., E., E., E. will have a B dimension of inch (0. -.mm). -B- A 0.0 (0.) M C A A L B S A e C E C L e A C e B E. (JEDEC MS-00-BB ISSUE D) LEAD DUAL-IN-LINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C D D E E e 0.0 BSC. BSC - e A 0.00 BSC. BSC e B L N Rev. 0 / FN Rev.00 Page of

17 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M-.. Symbols are defined in the MO Series Symbol List in Section. of Publication No... Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.0 inch (0.mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.0 inch (0.mm).. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ ) for E., E., E., E., E. will have a B dimension of inch (0. -.mm). -B- A 0.0 (0.) M C A A L B S A e C E C L e A C e B E. (JEDEC MS-00-AF ISSUE D) LEAD NARROW BODY DUAL-IN-LINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D D E E e 0.0 BSC. BSC - e A 0.00 BSC. BSC e B L N Rev. 0 / FN Rev.00 Page of

18 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B A 0.(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.0 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only.. The lead width B, as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x C M. (JEDEC MS-0-AA ISSUE C) LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC. BSC - H h L N Rev. /0 FN Rev.00 Page of

19 Package Outline Drawing M. LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev, / INDEX AREA.0 (0.).0 (0.). (0.).00 (0.) DETAIL "A" TOP VIEW SEATING PLANE. (0.00) 0.0 (0.0).0 (0.).0 (0.). (0.). (0.0) 0. (0.0) 0. (0.0) x. (0.00) SIDE VIEW A 0.0 (0.0) 0. (0.00) 0. (0.00) 0. (0.0) 0. (0.0) 0. (0.00) 0 SIDE VIEW B. (0.0). (0.) NOTES:. Dimensioning and tolerancing per ANSI Y.M-.. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side.. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.0 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. Terminal numbers are shown for reference only.. The lead width as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions in ( ) are not necessarily exact.. This outline conforms to JEDEC publication MS-0-AD ISSUE C.. (0.00) 0. (0.0) TYPICAL RECOMMENDED LAND PATTERN FN Rev.00 Page of

20 Small Outline Plastic Packages (SOIC) N INDEX AREA D e B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B A a 0.(0.00) L M h x o C M. (JEDEC MS-0-AE ISSUE C) LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.0 BSC. BSC - H h L N 0 o o 0 o o - Rev., / TYPICAL RECOMMENDED LAND PATTERN (.0mm) (.mm) (.mm TYP) (0.mm TYP) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.0 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only.. The lead width B, as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN Rev.00 Page 0 of

21 Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA e D B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B A 0.(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.0mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.0mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only.. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.mm (0.00 inch) total in excess of B dimension at maximum material condition.. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. GAUGE PLANE A M L C M.0 (JEDEC MO-0-AH ISSUE B) LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC - H L N Rev. /0 FN Rev.00 Page of

22 Metric Plastic Quad Flatpack Packages (MQFP) D D -D- Q.x (JEDEC MS-0AB ISSUE B) LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A- -B- A E E b b D D , e E E , PIN L N MIN 0 o MIN 0 o - o L o - o A A o - o M C 0./ /0.00 A A-B S D S b b SEATING PLANE -C BASE METAL WITH PLATING 0./ /0.00 -H- e 0.0 BSC 0.0 BSC - Rev. / NOTES:. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.. All dimensions and tolerances per ANSI Y.M-.. Dimensions D and E to be determined at seating plane -C-.. Dimensions D and E to be determined at datum plane -H-.. Dimensions D and E do not include mold protrusion. Allowable protrusion is 0.mm (0.0 inch) per side.. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.0mm (0.00 inch) total.. N is the number of terminal positions. Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO00 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN Rev.00 Page of