DATASHEET HS-2420RH. Features. Applications. Functional Diagram. Radiation Hardened Fast Sample and Hold

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1 Radiation Hardened Fast Sample and Hold OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 888INTERSIL or DATASHEET FN3554 Rev 4.00 The HS40RH is a radiation hardened monolithic circuit consisting of a high performance operational amplifier with its output in series with an ultralow leakage analog switch and MOSFET input unity gain amplifier. With an external hold capacitor connected to the switch output, a versatile, high performance sampleandhold or trackandhold circuit is formed. When the switch is closed, the device behaves as an operation amplifier, and any of the standard op amp feedback networks may be connected around the device to control gain, frequency response, etc. When the switch is opened the output will remain at its last level. Performance as a sampleandhold compares very favorably with other monolithic, hybrid, modular, and discrete circuits. Accuracy to better than 0.0% is achievable over the temperature range. Fast acquisition is coupled with superior droop characteristics, even at high temperatures. High slew rate, wide bandwidth, and low acquisition time produce excellent dynamic characteristics. The ability to operate at gains greater than frequently eliminates the need for external scaling amplifiers. The device may also be used as a versatile operational amplifier with a gated output for applications such as analog switches, peak holding circuits, etc. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD LEAD METALSEALED SIDEBRAZED CERAMIC DIP MILSTD835, CDIPT4 TOP VIEW IN IN+ OFFSET ADJUST 3 4 SAMPLE/HOLD 3 GND NC Features Electrically Screened to SMD # QML Qualified per MILPRF38535 Requirements Maximum Acquisition Time Step to 0.% s Step to 0.0% s Maximum Drift Current nA (Maximum Over Temperature) TTL Compatible Control Input Power Supply Rejection dB Total Dose krad(si) (Max) No LatchUp Applications Data Acquisition Systems D to A Deglitcher Auto Zero Systems Peak Detector Gated Op Amp Functional Diagram + SAMPLE/ HOLD 4 OFFSET ADJUST V GND + 5 V HOLD CAPACITOR HS40RH 7 OUTPUT OFFSET ADJUST 4 HOLD CAPACITOR V 5 0 NC NC 6 9 V+ OUTPUT 7 8 NC FN3554 Rev 4.00 Page of 0

2 Ordering Information ORDERING SMD NUMBER (Note ) PART NUMBER (Note ) TEMPERATURE RANGE ( C) PACKAGE (RoHS Compliant) PKG. DWG. # 596R95669CC HSB40RHQ 55 to +5 4 Ld SBDIP D4.3 HSB40RH/PROTO HSB40RH/PROTO 55 to +5 4 Ld SBDIP D4.3 NOTES:. These Intersil Pbfree Hermetic packaged products employ 00% Au plate e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pbfree soldering operations.. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the Ordering Information table must be used when ordering. FN3554 Rev 4.00 Page of 0

3 Test Circuits V DC ALL RESISTORS = % ALL CAPACITORS = 0% 00k 0k +V CC V CC S S S 6 S7 S 7 CH = 000pF + DUT A GND S 3 50pF 3 +V CC M OPEN 3 S 5 k S 4 00k + NULL AMP X X BUFFER V AC 50 + I LOAD AOUT 4 3 EOUT S 8 FIGURE. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S S 8 DETERMINE CONFIGURATION) +5V SINEWAVE IN IN IN3 IN4 IN5 IN6 IN7 IN8 A A EN A0 OUT +5V 5V + DUT k V IN CH = 000pF V OUT 50pF 50 +5V 5V DUT + k CH = 000pF V OUT 50pF SAMPLE/HOLD NOTE: Compute Hold Mode Feedthrough Attenuation from the Formula: FeedthroughAttenuation 0 log V OUT HOLD = V IN HOLD Where V OUT HOLD = PeakPeak Value of Output Sinewave during the Hold Mode. FIGURE. HOLD MODE FEEDTHROUGH ATTENUATION NOTE: GBWP is the Frequency of V at which: V OUT 0 log = 3dB V FIGURE 3. GAIN BANDWIDTH PRODUCT FN3554 Rev 4.00 Page 3 of 0

4 Test Circuits (Continued) SEND SAMPLE COMMAND SET t TO 7 s INITIALLY COURSE t ACQ MEASUREMENT LOOP FINE t ACQ MEASUREMENT LOOP DIGITIZE V AT t ( 0 s) INCREMENT t BY 50ns (50ns LONGER DELAY) DIGITIZE V AT t DECREMENT t BY 50ns CALCULATE V V IS V 0.0%? YES DIGITIZE V AT t ( 0 s) DIGITIZE V AT t NO DECREMENT t BY 50ns RECORD t ACQ YES CALCULATE V V IS V 0.0%? NO NOTE: See Test Diagram, Timing Diagram FIGURE 4. ACQUISITION TIME (t ACQ TO 0.0% IS SHOWN, t ACQ TO 0.% IS DONE IN THE SAME MANNER) t HS40RH V DIGITIZER V k 50pF V DIGITIZER V COMPUTER LER 000pF OR t 0 s DELAY t VARIABLE DELAY t DELAY FIGURE 5. FN3554 Rev 4.00 Page 4 of 0

5 Timing Waveforms V IN (POS t ACQ CASE) V 0.0% OR 0.% ENVELOPE DUT OUTPUT (POS t ACQ CASE) (t DIGITIZER COMMAND) t 0 s t (t DIGITIZER COMMAND) t t FIGURE 6. TIMING DIAGRAM FOR ACQUISITION TIME, (POSITIVE t ACQ CASE) +V V PEAK V FINAL 90% 0% V +OS, t R OS, t F 0% 90% t R t F V FINAL V PEAK FIGURE 7A. FIGURE 7B. FIGURE 7. OVERSHOOT, RISE AND FALL TIME WAVEFORMS +V +V +V +V 75% 5% 5% 75% V +SL SL V V V t t FIGURE 8A. FIGURE 8B. FIGURE 8. SLEW RATE WAVEFORMS FN3554 Rev 4.00 Page 5 of 0

6 Typical Performance Curves V SUPPLY = 5V DC, T A = +5 C, CH = 000pF, Unless Otherwise Specified DRIFT DURING HOLD AT 5 o C mv/s UNITY GAIN PHASE MARGIN (DEG) UNITY GAIN BANDWIDTH (MHz) MIN SAMPLE TIME FOR 0.% ACCURACY SWINGS (ms) SLEW RATE/ CHARGE RATE V/(ms) HOLD STEP OFFSET ERROR (mv) 0.0 0pF 00pF 000pF 0.0µF 0.µF.0µF CH VALUE mv RMS LOWER 3dB FREQUENCY = 0Hz EQUIV. NOISE SAMPLE MODE 00K SOURCE RESISTANCE OUTPUT NOISE HOLD MODE EQUIV. NOISE SAMPLE MODE 0K SOURCE RESISTANCE 0 00 K 0K 00K M BANDWIDTH FIGURE 9. TYPICAL SAMPLE AND HOLD PERFORMANCE vs HOLDING CAPACITOR FIGURE 0. BROADBAND NOISE CHARACTERISTICS ID (pa) TEMPERATURE ( o C) FIGURE. DRIFT CURRENT vs TEMPERATURE OPEN LOOP VOLTAGE GAIN (db) 00 CH = 0.0 F 80 CH = 00pF CH = 000pF CH =.0 F CH = 0. F K 0K 00K M 0M 00M FREQUENCY (Hz) FIGURE. OPEN LOOP FREQUENCY RESPONSE ATTENUATION (db) K 0K 00K M 0M SINUSOIDAL FREQUENCY (Hz) OPEN LOOP PHASE ANGLE (DEGREES) CH = 0.0 F CH =000pF CH 00pF CH =.0 F CH = 0. F 0 00 K 0K 00K M 0M 00M FREQUENCY (Hz) FIGURE 3. HOLD MODE FEEDTHROUGH ATTENUATION CH = 000pF FIGURE 4. OPEN LOOP PHASE RESPONSE FN3554 Rev 4.00 Page 6 of 0

7 BurnIn Circuit HS40RH CERDIP Irradiation Circuit IN +IN CTL GND 4 3 R 4 3 5V R C D OFF ADJ OFF ADJ V NC NC HOLD CAP NC 0 +V 9 +5V GND V V GND 7 OUT NC 8 D C 7 8 NOTES: R = 00k 5% (per socket) C = C = 0. F (one per row) or 0.0 F (one per socket) D = D = N400 or equivalent (per board) NOTES: V = +5V V = 5V R = 00k HOLD STEP VOLTAGE (V) CH V DC VOLTAGE (V) CH = 0. F CH = 0,000pF CH = 000pF + + HS40RH 5 IN +IN V OUT CH = 00pF 00k OFFSET TRIM ( 5mV RANGE) FIGURE 5. HOLD STEP vs VOLTAGE FIGURE 6. BASIC SAMPLEANDHOLD with OFFSET TRIM 0.00RF R F +IN HS40RH OUTPUT IN HS40RH RI OUTPUT IN R F OUT +IN OUT R I GAIN ~ R F R I 0.00RI GAIN ~ I + R F R I FIGURE 7. INVERTING CONFIGURATION with GAIN ADJUST FIGURE 8. NONINVERTING CONFIGURATION WITH GAIN ADJUST FN3554 Rev 4.00 Page 7 of 0

8 HS40RH Offset and Gain Adjustment Offset Adjustment The offset voltage of the HS40RH may be adjusted using a 00k trim pot, as shown in Figure 6. The recommended adjustment procedure is:. Apply to the sampleandhold input, and a square wave to the control.. Adjust the trim pot for output in the hold mode. Gain Adjustment The linear variation in pedestal voltage with sampleandhold input voltage causes a 0.06% gain error (CH = 000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sampleandhold. Figures 7 and 8 illustrate how to implement gain error adjust on the sampleandhold. The recommended procedure for adjusting gain error is:. Perform offset adjustment.. Apply the nominal input voltage that should produce a + output. 3. Adjust the trim pot for + output in the hold mode. 4. Apply the nominal input voltage that should produce a output. Measure the output hold voltage (V0 NOMINAL). Adjust the trim pot for an output hold voltage of: V0 NOMINAL + FN3554 Rev 4.00 Page 8 of 0

9 Die Characteristics DIE DIMENSIONS: 97 mils x 6 mils x 9 mils METALLIZATION: Type: Al Thickness: 6kÅ kå GLASSIVATION: Type: Silox Thickness: 4kÅ kå Metallization Mask Layout HS40RH WORST CASE CURRENT DENSITY:.0 x 0 5 A/cm TRANSISTOR COUNT: 78 PROCESS: BipolarDi FN3554 Rev 4.00 Page 9 of 0

10 Ceramic DualInLine Metal Seal Packages (SBDIP) BASE PLANE SEATING PLANE S b ccc M bbb S b C A B S C A B D A A e D S S D S NOTES:. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (, N, N/, and N/+) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S at all four corners. 7. Measure dimension S from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 0. Dimensioning and tolerancing per ANSI Y4.5M 98.. Controlling dimension: INCH. E M c L ea/ LEAD FINISH BASE METAL b M (b) SECTION AA D A S Q C A ea Baaa M C A B S D S c (c) D4.3 MILSTD835 CDIPT4 (D, CONFIGURATION C) 4 LEAD CERAMIC DUALINLINE METAL SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e 0.00 BSC.54 BSC ea BSC 7.6 BSC ea/ 0.50 BSC 3.8 BSC L Q S S o 05 o 90 o 05 o aaa bbb ccc M N Rev. 0 4/94 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3554 Rev 4.00 Page 0 of 0

DATASHEET HS Features. Pinouts. ARINC 429 Bus Interface Line Driver Circuit. FN2963 Rev 3.00 Page 1 of 7. May 30, FN2963 Rev 3.

DATASHEET HS Features. Pinouts. ARINC 429 Bus Interface Line Driver Circuit. FN2963 Rev 3.00 Page 1 of 7. May 30, FN2963 Rev 3. DATASHEET ARI 429 Bus Interface Line Driver Circuit FN2963 Rev 3.00 The is a monolithic dielectric ally isolated bipolar differential line driver designed to meet the specifications of ARI 429. This device