Sallen-Key Low Pass Filter Design Routine

Transcription

1 Sallen-Key Low Pass Filter Design Routine v v x i v R o C R C G V noa Fig. : Single-ended Sallen-Key filter Note: This routine is a reduction of a more complex version. This reduction is still taking place, so please excuse the current mess. R C R C R v x v C V o π π G(V π ) C C R s*i C *τ F I R C R V x V y V C π I G(V π ) V o Fig. : Single-Ended Sallen-Key Filter w/ Emitter Follower R R C / R R C C Fig. 3: Dferential Voltage-Driven Sallen-Key Filter useful functions and identities Units Constants Units/Constants/Model File V o = C = ω = R R C C R C V i + R + R s + R R C C s = s A = g m R s + + Q Ideal Transfer Function Q =

2 Q = C R + R := A ( s) k = q A max = + g m R Q ω + + s Q = mv s s ω s + A ω A ω + Den( s) I C g m = Maximum Attenuation with a fast transistor Den = + Q s + s f notch = A A notch := A Frequency of the Notch Attenuation of the Notch Equivalent Noise Bandwidth H LPF s, G,, Q := NoiseBW( Q) 0000 := 0 num:= 00 Number of Points for Plotting i :=.. num Index Vector for Plotting i Q vali := ( 0 0.) + 0. num 40 s G s + + Q ( H LPF ( π f,, π, Q) ) df Frequency Response - General LPF Representation (no zeros): NoiseBW( Q vali ) π Q vali Q vali Derivation First Use KCL to solve for the transfer functions for the system V o V V i V x + V n x G Node Vx = + V x V o R R C s Node Vo/G V x V o + V n G R = V o G + V n C s C R

3 R C R C s C R C R R C s + V o = G V n... R C R C s C R G C R R C s + G V i + R C R C s C R G C R R C s + = R C R C Q = Q = G + + R C R C R C V neq = R + R + V n V oeq = V neq ( ) H LPF s, G,, Q What is important is the integrated noise. V oeq = V neq f0 NoiseBW G V oeq V neq = f 0 NoiseBW G C R + + G C R R C Inputs.7MHz f 0 := f 0 = 63.5 khz Center Frequency Q := Desired Q SNR := 80 Minimum Signal to Noise Ratio V DD :=.7V Supply Voltage := 300K erature Range G := Gain P jammer := 30m Power of the Jammer P signal := 80m Power of the Desired Signal f jammer := 900kHz Frequency of Jammer f jammer := 700kHz Frequency of Second Jammer (for Two-Tone Analysis) Optional Inputs V DSsat := 0.3V V DSsat of Op-Amp Input R maxdes := 400kΩ Maximum Desired Resistor Calculations := π f 0 NoiseBW( Q) =. Effective Noise Bandwidth V inswing := V DD V DSsat V inswing =. V V outswing := V inswing H LPF j π f jammer, G,, Q V outswing = V V inswing V rms := V rms = 0.74 V 3

4 V rms V neq := V neq = nv SNR f 0 NoiseBW( Q) Hz 0 Q r := Q r = G + + R r C r R r C r R r C r The following current should be sized much higher to reduce the distortion of the amplier. Voutswing_ t := V outswing π f jammer Crude Estimate of Load Capacitance C Leff := C r C Leff = pf Estimated Load Capacitance I slewr := C Leff Voutswing_ t I slewr = 0.08 ma Required Current to Slew Output 0 V oeq := V neq f0 NoiseBW( Q) G V oeq = µv V neq V n := V n = nv 4 Hz Solving Assumption Number : R =R G thresh := 8 Q + G thresh =.5 G should be less than or equal to one valid r := G 4 k I noiser := I noiser = 0.06 µa V n (, ) I r := I slewr > I noiser, I slewr, I noiser I r = 0.08 ma I r := I r < I min, I min I r 8 Q + valid r = R := R = kω 4 k R := R > 00kΩ, 00kΩ, R R = 00 kω R r := R R r := R + 8 Q ( G ) C r := C r =.834 pf 4 Q R Problem with the R =R architecture. C blows up for large Q's. C r := C r = pf R C r ω r ω r := = khz R r C r π r := r R r R r C r C = 63.5 khz r π I r g mr := g mr = ma V A r := g mr R r A r =

5 A r := g mr R r A r = A maxr := 0 log( A maxr ) = Maximum Attenuation with a fa + g mr R r Q ω r Solving Assumption Number : C =C Gthresh =.5 G should be greater than G thresh := + Q Q Problem with C=C architecture: Cannot be used with an emitter follower unless Q</. valid c := G + Q Q valid c = 0 All G's can be used with Q < 5 8 Q + ( G) Q R + R R = 0 T Q ( G) R c := ( G) Q + Q Q ( G) R c = i kω R c := R c R c = i kω C := C c := C C c := C Q R c + R c + ( G) R c c := c R c R c C c C = 63.5 khz c π Q c := Q c = G + + R c C c R c C c R c C c f notchr := A r f notchr = 5.65 MHz Frequency of the Notch π A notchr := 0 log( A notchr ) = 37.0 A r ( R r + R r ) W min area Rr := W min area Rr = 0 µm cost Rr := cost_mm area Rr cost Rr =. 0 3 cent area Cr := ( C_area C r + C r ) area Cr = µm cost Cr := cost_mm area Cr cost Cr = cent area r := area Cr + area Rr area r = 89.8 µm cost powerr := cost power I r V DD cost powerr = 0.4 cent cost r := cost Cr + cost Rr + cost powerr cost r = 0.36 cent C =.004 pf C Leff := C c C Leff =.004 pf 5

6 C Leff := C c C Leff =.004 pf I slewc := C Leff Voutswing_ t I slewc = 5.0 µa Required Current to Slew Output 4 k I noisec := I noisec = 0.06 µa V n (, ) I c := I slewc > I noisec, I slewc, I noisec I c = 5.0 µa I c := I c < I min, I min I c ω c := R c C c ω c π = i khz I c g mc := g mc = ma V A c := g mc R c A c = i A maxc := 0 log( A maxc ) = Maximum Attenua with a fast transist + g mc R c Q ω c f notchc := A c f notchc = i MHz Frequency of the π A notchc := 0 log( A notchc ) = i Depth of Notch A c + W min R c R c area Rc := W min cost Rc := cost_mm area Rc cost Rc = cent area Cc := ( C_area C c + C c ) area Cc = µm cost Cc := cost_mm area Cc cost Cc = cent area c := area Cc + area Rc area c = 55.7 µm cost powerc := cost power I c V DD cost powerc = cent cost c := cost Cc + cost Rc + cost powerc cost c = 0.3 cent Solving Assumption Number 3: R C =R C =τ. G thresh := G thresh = Q valid t := G > G thresh valid t = area Rc = 3.5 µm R t := R t = kω Q G R t := Q G R t R t = kω C t := R t C t =.43 pf C t := R t C t =.004 pf t := t R t R t C t C t π 6 = 63.5 khz

7 R t R t C t C t π Q t := Q t = G + + R t C t R t C t R t C t Solving Assumption #4: C =C max or C min. First solve for maximum Capacitance by setting the cost of the internal capacitor to that of an external capacitor. This upper limit is set when extra pins are available to put a capacitor off-chip. C_area C max := cost_mm cost Cext C max = pf C max Area Cmax := Area Cmax = 5.64 µm C_area If the pins are not available to put the capacitor off-chip, the maximum capacitor size must be re-evaluated using marketing estimates for the amount the chip can sell for, and yields given the larger chip size, and package limits on the die size. C max := 00pF Maximum Desired On-Chip Capacitance C max Area Cmax := Area Cmax = 5.64 µm C_area Given the center frequency, maximum capacitor size, and desired SNDR the needed capacitance is given by the following equation to prevent a complex resistor sizing. Q 4 C maxm := C maxm =.007 pf C maxm Area Cmaxm := Area Cmaxm = µm C_area Now Solve for Variables C m := C maxm.05 C m =.07 pf valid m := Q < C m 4 valid m = ( ) 4 Q R m := + ω V neq V 0 C m n R m =.683 kω R m := R m R m = kω C m := C m =.004 pf Rm R m C m m := m R m R m C m C = 63.5 khz m π Q m := Q m = G + + R m C m R m C m R m C m Q maxm := C m Q maxm = C Leff := C m C Leff =.07 pf Estimated Load Capacitance I slewm := C Leff Voutswing_ t I slewm = µa Required Current 4 k to Slew Output 7

8 I noisem := I noisem = 0.06 µa V n cost Cm := cost_mm area Cm cost Cm = cent area m := area Cm + area Rm area m = 68.0 µm cost powerm := cost power I m V DD cost powerm = 0.08 cent cost m := cost Cm + cost Rm + cost powerm cost m = 0.36 cent Solving Assumption #4.5: Other Solution to Quadratic of 4. C m := C maxm.05 C m =.07 pf valid m := Q < C m 4 valid m = ( ) 4 Q R m := ω V neq V 0 C m n R m = kω R m := R m R m =.683 kω C m := C m =.004 pf Rm R m C m m := m R m R m C m C = 63.5 khz m π Q m := + R m C m R m C m I m := I slewm > I noisem, I slewm, I noisem I m := I m < I min, I min, I m I m = µa ω m := ω m R m C m = khz π I m g mm := g mm = ma V A m := g mm R m A m = A maxm := 0 log( A maxm ) = Maximum Attenuation with a fast transistor + g mm R m Q ω m f notchm := A m f notchm = 4.68 MHz Frequency of the Notch π A notchm := 0 log( A notchm ) = Depth of Notch A m + W min R m R m area Rm := W min + G R m C m area Rm = 3.5 µm cost Rm := cost_mm area Rm cost Rm = cent area Cm := ( C_area C m + C m ) area Cm = µm Q m = Q maxm := C m Q maxm =

9 Q maxm := C m Q maxm = C Leff W min R m + R m area Rm := W min area Rm = 3.5 µm cost Rm := cost_mm area Rm cost Rm = cent area Cm := ( C_area C m + C m ) area Cm = µm cost Cm := cost_mm area Cm cost Cm = cent area m := area Cm + area Rm area m = 68.0 µm cost powerm := cost power I m V DD cost powerm = 0.08 cent cost m := cost Cm + cost Rm + cost powerm cost m = 0.36 cent Solving Assumption #5: R =R max. cost Rext R max := R max = MΩ cost_mm W min R max := R max < R maxdes, R max, R maxdes R max = 400 kω R max W min Area Rmax := W min Area Rmax = 4.4 µm R n := R max R n := R n C n := + R n R n Q G = R n := C m C Leff =.07 pf Estimated Load Capacitance I slewm := C Leff Voutswing_ t I slewm = µa Required Current to Slew Output 4 k I noisem := I noisem = 0.06 µa V n I m := I slewm > I noisem, I slewm, I noisem I m := I m < I min, I min, I m I m = µa ω m := ω m R m C m = khz π I m g mm := g mm = ma V A m := g mm R m A m = A maxm := 0 log( A maxm ) = Maximum Attenuation with a fast transistor + g mm R m Q ω m f notchm := A m f notchm = 9.36 MHz Frequency of the Notch π A notchm := 0 log( A notchm ) = 39.5 A m 9 R n = 400 kω R n = kω Depth of Notch

10 R n + Q ( G) R R n n 4 ( G) Q G C n = 4.87 pf G thresh := G thresh = Q R n + R n ( R n 0) valid n := G > G thresh > valid n = 0 C n := C n =.004 pf Rn R n C n n := n R n R n C n C = 63.5 khz n π G must be greater than for C to be real Q n := Q n = G + + R n C n R n C n R n C n C Leff := C n C Leff = 4.87 pf Estimated Load Capacitance I slewn := C Leff Voutswing_ t I slewn = 4.38 µa Required Current to Slew Output 4 k I noisen := I noisen = 0.06 µa V n (, ) I n := I slewn > I noisen, I slewn, I noisen I n := I n < I min, I min I n I n = 0 µa ω n := ω n R n C n = 8.67 khz π I n g mn := g mn = ma V A n := g mn R n A n = A maxn := 0 log( A maxn ) = Maximum Attenuation with a fast transistor + g mn R n Q ω n f notchn := A n f notchn = 7.64 MHz Frequency of the Notch π A notchn := 0 log( A notchn ) = Depth of Notch A n W min R n + R n area Rn := W min area Rn = 3.5 µm cost Rn := cost_mm area Rn cost Rn = cent area Cn := ( C_area C n + C n ) area Cn = i µm cost Cn := cost_mm area Cn cost Cn = cent area n := area Cn + area Rn area n = i µm cost powern := cost power I n V DD cost powern = cent 0

11 cost n := cost Cn + cost Rn + cost powern cost n = 0.0 cent Solving Assumption #6: Minimize Area This doesn't work for G<. It spits out unrealistically sized values for G's close to one. Lets set a threshold of a G of about.3. In general the area is dominated by the capacitor R g := 0.6MΩ Guess at R valid a := G >.3 valid a = 0 R a := root Required Current to Slew Output 0 log A maxc = Maximum Attenuation with a fast transistor f notchc = i MHz Frequency of the Notch 0 log A notchc = i Depth of Notch cost c = 0.3 cent Cost of c method Implementation, where R =R =R valid r = Are these Coefficients Valid? 0=no, =yes R r R r C r C r = 00 kω Resistor Value = 00 kω Resistor Value = pf Capacitor Value =.834 pf Capacitor Value I r = µa Required Current to Slew Output 0 log A maxr = Maximum Attenuation with a fast transistor f notchr R a = kω R a := R a = 5.65 MHz Frequency of the Notch + R g R g W min C_area Q + ( G) R g, R g R W min C_area sq R g R a = kω W min C_area C a := R a C a = pf C a := C a = 0pF Outputs R W min C_area a R a Implementation, where C =C =C valid c = 0 Are these Coefficients Valid? 0=no, =yes R c = i kω Resistor Value R c = i kω Resistor Value C c C c =.004 pf Capacitor Value =.004 pf Capacitor Value I c = 0 µa 0 log A notchr = 37.0 Depth of Notch cost r = 0.36 cent Cost of r method

12 0 log A maxm = f notchm = 4.68 MHz Required Current to Slew Output 0 log A maxm = Maximum Attenuation with a fast transistor f notchm = 9.36 MHz Frequency of the Notch 0 log A notchm = 39.5 Depth of Notch cost m = 0.36 cent Cost of m method Implementation, where R =R max. valid n = 0 Are these Coefficients Valid? 0=no, =yes R n r Implementation, where C =C max. valid m = R m = kω R m =.683 kω C m =.07 pf C m =.004 pf I m = µa = 400 kω Resistor Value R n = kω Resistor Value C n = 4.87 pf C n =.004 pf I n = 0 µa 0 log A notchm = cost m = 0.36 cent nd Implementation, where C =C max. valid m = R m =.683 kω R m = kω C m =.07 pf C m =.004 pf I m = µa 0 log A maxn = f notchn = 7.64 MHz 0 log A notchn = cost n = 0.0 cent architecture := valid r valid c 3 valid m Resistor Value Resistor Value Capacitor Value Capacitor Value Capacitor Value Capacitor Value Frequency of the Notch Depth of Notch Cost of n method ( valid c ) error ("none are valid" ) valid m valid r Are these Coefficients Valid? 0=no, =yes Required Current to Slew Output Maximum Attenuation with a fast transistor Frequency of the Notch Depth of Notch Cost of m method Are these Coefficients Valid? 0=no, =yes Resistor Value Resistor Value Capacitor Value Capacitor Value Required Current to Slew Output Maximum Attenuation with a fast transistor architecture = 3 R := R r valid r R c valid c

13 C := C r valid r C =.004 pf I := I r valid r I c I m R c R m R := R r valid r R c R m C := C r valid r C c C m C =.07 pf C c C m R = kω R =.683 kω valid c valid c valid c valid c valid m valid m error ("none are valid" ) Ω valid m valid c valid m error ("none are valid" ) Ω valid m valid m error ("none are valid" ) F valid m valid m error ("none are valid" ) F valid m error ("none are valid" ) A valid m ( valid c ) ( valid r ) ( valid c ) ( valid r ) ( valid c ) ( valid r ) ( valid c ) ( valid r ) ( valid c ) ( valid r ) I = 0.0 ma A max := A maxr valid r 0 log( A max ) = I g m := A := g m R A maxc A maxm f notch := ( ω ) f notchguess A := π valid c valid m error ("none are valid" ) valid m valid r ω ( ) ( valid c ) f notch = MHz f notchguess = 4.68 MHz A notch := 0 log A A, ω, j π f notch A notch = A jammer := 0 log( A ( A, ω, j π f jammer ) ) A jammer = 0 log( A ( A, ω, j π f notchguess ) ) = f A π g m = ma V A = Useful bandwidth

14 f 0 f start := 0 Starting Frequency for Plotting f stop := f 0 00 Stopping Frequency for Plotting i f := i f stop f start num f start ω i := π f s := j ω i i i Filter Response vs. Frequency A jammer Attenuation () g( A max ) 80 f start Frequency (MHz) f stop MHz f jammer f notch MHz MHz MHz Functions sallenkey( f 0, Q, SNR, G) := errval G > 8 Q choice G 8 Q R choice, (, ) R > R max, R max R + < +, 0, G < + Q Q,, 0 Q ( G) ( G) Q + R choice V neq V n, R, R C choice, C choice, errval R Ω R Q Q + 8 Q ( G ) R + R + ( G) R ω, 0 4 Q R R + R + ( G) R Q ω, 0 R C 4 Q ( G), 4 k

15 R Ω C F C F Example f 0 = 63.5 khz Center Frequency Q = Desired Q SNR = 80 Minimum Signal to Noise Ratio G = Gain x:= sallenkey f 0, Q, SNR, G errval := x errval = 0 Error? (0=error, =no error) R := x Ω R = kω Resistor Value R := x Ω 3 R = kω Resistor Value C := x F C 4 = pf Capacitor Value C := x F C 5 =.834 pf Capacitor Value 0 0 ( ) 0 log H LPF s i, G, π f 0, Q Analysis yields: R, R, C, C := R R C C f i R, R, C, C π = MHz = R R C C Q G, R, R, C, C H SK s, G, R, R, C, C R R C C := Q G, R, R, C, C G + + R C R C R C = := H LPF ( s G (, ), (, )),, R, R, C C Q G, R, R, C C Q = C R R C R + R = ( C R + R 0 0 log H SK s i, G, R, R, C, C 50 5

16 0 log G 50 "small" variations f i 0 0 log 0 log H SK s i, G, R, R, C, C G H SK s i, G, R., R, C, C G (, ) Q G,. R, R, C, C Q G, R, R, C C Sensitivity Version : = S QR ( Q) := Q f i (, ). R, R, C, C R, R, C C S QR ( 5) = 4.5 = R := 0. R QbyQ S QR ( 5) R := R QbyQ = 0.45 Version : S QR ( Q) := 0 Conclusions choose G= for minimum sensitivity! Other benefits of G=: - simplicity, low sensitivity of G... - good linearity: voltage accross R is zero in passband Other Problems: - sensitive to top/bottom plate parasitics - sensitive to RC time constant variations Use only in non-critical applications: - low pole Q (hence restrict order to 4 or so) - where large variations of cutoff frequency can be accepted (typical variation of untrimmed RC time constants: +/- 30%) Copyright Information Note: true only for very small variations... large (e.g. 0%) changes of R will still change Q. 6

17 Copyright Information All software and other materials included in this document are protected by copyright, and are owned or controlled by Circuit Sage. The routines are protected by copyright as a collective work and/or compilation, pursuant to federal copyright laws, international conventions, and other copyright laws. Any reproduction, modication, publication, transmission, transfer, sale, distribution, performance, display or exploitation of any of the routines, whether in whole or in part, without the express written permission of Circuit Sage is prohibited. 7