# Lecture 04: Single Transistor Ampliers

Size: px
Start display at page:

Transcription

1 Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37

2 Single-Transistor Ampliers Common Source Common Drain Common Gate Dr. Ryan Robucci Lecture IV 2 / 37

3 Common Source Aplier (1) sat cutoff nonsat When leave sat? Approach: Use equation V D = V G V TH V OUT = V IN V TH Must nd unknown voltage V OUT in terms of input Assume Saturation V DD V out R D = k W L 2 V GS V }{{ T } V ov 2 V out = R D k W L 2 V GS V }{{ T V } DD V ov 2 Dr. Ryan Robucci Lecture IV 3 / 37

4 Common Source Aplier (2) V IN V TH = V out = R D k W L 2 V IN V }{{ TH } V ov 0 = R D k W L 2 V IN = 1± k = R W L D 2 V GS V }{{ T V } DD V ov V GS V }{{ T } V DD V ov 2 V GS V }{{ T } V IN V TH V }{{} DD V ov V ov 1+4R D k W L 2 R D k W L 2 2 = V in,sat (pos. answer is the obvouis choice) Dr. Ryan Robucci Lecture IV 4 / 37

5 Common Source Aplier (3) For V in > V in,sat k V out = V DD R W ( L D 2 2Vov V out Vout) 2 For linear region (V out 2V ov ): k V out V DD R W L D 2 (2V ov V out ) V out V DD R D k W L V ov V ( out V out 1 + RD k W L V ) ov VDD V out V DD (1+R D k W L V ov) = ( V DD ) 1 1+R D R ON Now let R ON = 1 V out V out V DD k W L V ov ( V DD ) 1 1+R D R ON R ON (R ON +R D ) (a simple voltage divider) Dr. Ryan Robucci Lecture IV 5 / 37

6 Common Source Aplier (4) However the highest gain is in the sat region: k d R W L D 2 V GS V }{{ T } Vov A V = dv out,sat dv in = dv in A V = g m R D Compare with Small Signal Approach: 0 v o R D v o vi = g m v i = g m R D (same as before) 2 V DD What happens when λ 0 v o vi = g m (R D r d ) What is the limit as R D is increased? Note (R D r d ) R D and (R D r d ) r d If R D r d, R out r d, A v g m r d If r d R D, R out R D, A v g m r d = R D k W L V ov Dr. Ryan Robucci Lecture IV 6 / 37

7 Ideal Current-Source Load (1) With R D replaced with in the small signal model, the gain is: A v = g m r ds To set these values in a design, we must choose the bias current. The value of the current source, I b, becomes the the transisor bias current, I bias, in the design. Choose I bias based on desired values for the input voltage bias, g m, power(current),etc.. Dr. Ryan Robucci Lecture IV 7 / 37

8 Ideal Current-Source Load (2): Design of the input bias point Note: In practice, high-gain circuits have a very limited input range Some intuative nessisity for for this is as follows: Output range is practically limited by the supply rails. Input range size is output range size A v Bias Point? Output Range Input Range Therefore, if output range size is <5 V and gain is A v = 100, the input range size is <50 mv For high gain circuits, we conceptually design an input bias point, V in,bias, rather than an input range dened by two values, V in,min and V in,max Typically start by assumming I bias I D,sat Then, V in,bias is dened by the decided bias current, I bias, 2I and the relation V ov = bias k W L Dr. Ryan Robucci Lecture IV 8 / 37

9 Ideal Current-Source Load (3): Output Range V out,max : The ideal current source presents no maximum on the output voltage, though if we are approximating a practical circuit we expect V out < V DD = V out,max V out,min : The transistor presents a lower bound on V out to maintain saturation V out > V in V th V out,min = V in,bias V TH = V ov What parameters aect V ov? V ov = 2I bias k W L Dr. Ryan Robucci Lecture IV 9 / 37

10 Ideal Current-Source load (4): Ex. Design Modication Take a situation in which after simulation you are satised with the gain but need to lower the input bias point to make it compatible with another circuit. How can you lower V out,min without sacracing gain ( g m r d )? A v = g m r d = 2I 1 V ov λi = 1 λv ov now, λ 1 L and V ov = 2I k WL 2I k W L so, A v input bias determined by V ov = 2IL k W You'll nd that to maintain A v and lower the input bias, more than one free design parameter must be changed. L and I may be decreased proportionally so that L I is constant The cost of this solution is more size and lower bandwidth W = more parasitics I = R = (RC out ) = B.W. Dr. Ryan Robucci Lecture IV 10 / 37

11 PFET (less-ideal) current source (1) To design for the PFET choose V bias such that I sat for PFET is the same as the desired I bias To approximate a current source, the L for the PFET can be made large so that R out is large Model for saturated PFET acting as current source is shown. (Optional in-class sidebar current and voltage sources) Dr. Ryan Robucci Lecture IV 11 / 37

12 PFET (less-ideal) current source (2) Gain Finding Gain: (done as example in-class) R out = r d,p r d,n G m = g m,n A v = g m,n ( rd,p r d,n ) Dr. Ryan Robucci Lecture IV 12 / 37

13 PFET (less-ideal) current source (3) Why not just use a resistor with value of r d,p? Take example: [ λ p = V 1 ] for a 1-µm eective length device I bias = 1 [µa] r d,p = 1 = 100M For a resistor of 100M, the voltage drop with 1 µa would be 100V! Furthermore, the PFET L eff can be modied to alter the relationship. Transistor loads allow exibility in terms of designing the small-signal resistance and bias point. λi bias = 100 Dr. Ryan Robucci Lecture IV 13 / 37

14 PFET (less-ideal) current source (4): Output range However, this active load limits output range as compared to an Ideal current source as V out > V bias + V Tp, PFET leaves saturation and rd,p is replaced with 1 β(v SG V Tp ) So V out,max = V dd V sd,sat Output Range: V ds,sat,n < V out < V dd V sd,sat,p V ov,n < V out < V dd V ov,p OUTPUT RANGE is a key concept in Analog Design Dr. Ryan Robucci Lecture IV 14 / 37

15 Source Follower (Common Drain, Level Shifter) (1) sat cutoff nonsat A grounded bulk implies V GB = V G and V SB = V S A xed bulk implies v gb = v g and v sb = v s for the small-signal model As V i increases when does the transistor leave saturation? Ans: V i > V DD + V TH As V i decreases, when is cut-o achieved? Dr. Ryan Robucci Lecture IV 15 / 37

16 Source Follower (Common Drain, Level Shifter) (2) g m v in = v o R s + g s v o + v o v o r ds 1 R v in = g m 1 Rs +g = g s r ds S + r 1 m ds if g s R s 1 and g s r ds 1 v o v in g m gs g m gs = 1 n = κ = c ox c ox +c dep = 1 1+η 1 in strong inversion g S r ds R S +R s +r ds Dr. Ryan Robucci Lecture IV 16 / 37

17 Source Degenerated Amplier (1) As V in increases I will increase as V out decreases V s increases (as in source follower) When V OUT < V G V TH FET LEAVES SAT At what rate does Vout drop in the high gain region? To answer, can use small signal analysis. Dr. Ryan Robucci Lecture IV 17 / 37

18 Source Degenerated Amplier (2) (R out ) R out = R up R down R up = R D R down : Set V i xed (0): R down : v s = i t R S v x = v s + (i t + g s v s )r ds v x = i t R s + (i t + g s R s )r ds v x it v x it = R s + (1 + g s R s )r ds = R s + r ds + g s r ds R s ****This result we will want to utilize often: resistance looking into drain*** R eq = R s + r ds + g s r ds R s g s R s 1 may ignore r ds g s r ds 1 may ignore R S If both assumptions apply : R eq g s r ds R s R out R D (g s r ds R s + R s + r ds ) Dr. Ryan Robucci Lecture IV 18 / 37

19 Source Degenerated Amplier (3) (G m ) Set ouput to 0V A G m = i o vi =? Dr. Ryan Robucci Lecture IV 19 / 37

20 Source Degenerated Amplier (4) (G m ) Solve for unknown v s ) (1a) g m v i = v s (g S + 1 r ds + 1 R s g (1b)v s = v m i g S + 1 r ds + 1 Rs (2a) note i o = i x = v s R s (or just proceed with standard brute-force KCL) i o = v i g m r ds using (1b) i o v i = g S r ds R S +R S +r ds g m r ds g S r ds R S +R S +r ds g m G m = ( g s + Rs 1 + r )R 1 s ds as before, if g s R s r ds R s,r ds G m g mr ds g S r ds = g m 1 gs R s above threshold κ 1 G m 1 R s Dr. Ryan Robucci Lecture IV 20 / 37

21 Source Degenerated Amplier (5) (A v = G m R out ) g A v = G m R out = ( m R s g s )(R D (g s r ds R s + R s + r ds )) }{{} R r ds R D s }{{} gs Under some assumptions: A v g m R D gs Rs R D Rs (make sense?) R out R D BW = 1 C out R out Dr. Ryan Robucci Lecture IV 21 / 37

22 Source Degenerated Amplier (6) (source node) Take source node as output instead: R out = R up R down R down = R s Dr. Ryan Robucci Lecture IV 22 / 37

23 Source Degenerated Amplier (7) (source node) Set v i = 0 R eq = v x it =? v d = i z R D = i t R D (simplest equation that is in terms of input) v y = v d + v ds = v d + i rds r ds = v d + (i t v y g s )r ds (KVL using resistors) v y = i t R D + (i t v y g s )r ds Looking into source equation R eq = v y i t = R D+r ds 1+r ds g s Dr. Ryan Robucci Lecture IV 23 / 37

24 Resistance Looking into Source R eq = R D+r ds 1+g s r ds You will sometimes see R eq = R D+r ds 1+g m r ds if g mb is ignored note the following approximations (assuming g s r ds 1) if then R D r ds R D r ds R D r ds R eq R D g s r ds R eq 2 g s R eq = 1 g s Dr. Ryan Robucci Lecture IV 24 / 37

25 Common Gate Amplier (Current Buer) As V in increases, current decreases and V o increases V DD V o sat ~g s R D V G -V TH FET Leaves SAT V G -V TH V G FET is "off" I is nearly 0 In sat region: G m = g s + 1 r ds g s R out = R D r ds R in (input resistance) is low (looking into source equation) V i Dr. Ryan Robucci Lecture IV 25 / 37

26 Common Gate Amplier Output Range Transistor saturation condition limits ouput: V out > V B V TH Bias point of input is tied to V B and current: V B = V in + V ov + V TH = V in + 2I + V k W TH L Dr. Ryan Robucci Lecture IV 26 / 37

27 Common Gate, AC-Coupled An issue with the previous circuits is that DC current is drawn from the input. This can be resolved with an AC-coupled input: DC operating point is independant of the input DC level DC current is not drawn from input, though AC current is drawn Input impedance still low at most frequencies (though DC input resistance is ) Output resistance is high (R D casaded resistance) Dr. Ryan Robucci Lecture IV 27 / 37

28 Common Gate Amplier (Current Buer) Pseudo Small-Signal Here we'll assume the capacitor can be treated as a short Pseudo-Small Signal Drawing: For this class is a small-signal drawing using a transistor symbol as a shorthand for the transistor's small signal equivalence. If we include a source resistance R S between the input voltage source and source terminal: R out = R D (g m r ds R s + R s + r ds ) R D }{{} 1 G m = ( 1 R s + ) g s + 1 r }{{ ds } 1/gs if gs r ds 1 g s R s g s +1 if (g m r ds R s +R s +r ds ) R D If 1 g s R s, G m 1 R s Dr. Ryan Robucci Lecture IV 28 / 37

29 Common Gate Current Buer The original circuit: Current-Output Device Transimpedance (I-to-V) Amplifier Current Buffer The common-gate transistor can preferably be thought of as a current buer. In the circuit shown: looking into the source, the equivelent resistance R SS is lower than the added output load resistance R D. Looking into the drain, the equvilent resistance R DD, is higher then R s. In the common-gate voltage amplier we use R D to generate an output voltage. Dr. Ryan Robucci Lecture IV 29 / 37

30 Common Gate Current Buer Example (1) Sensor-Circuit (Pseudo) Small-Signal Model Resistor Alone as I-to-V Transimpedance (I-to-V) Amplifier Using Common-Gate Transimpedance (I-to-V) Amplifier Current Buffer Transimpedance (I-to-V) Amplifier Current Buffer Assume a sensor with the following characteristics: 100 µa on top of 1 ma bias current with a x output voltage, and an output resistance of 100K Assume the sensor parasitic capacitance, c S, is 1pF Assume we want 1 V output modulation and bandwith 100 Mhz Dr. Ryan Robucci Lecture IV 30 / 37

31 Common Gate Current Buer Example (2) Ideally we want v o is = R D and we might choose R D to be 10k. However, the actual gain is less because the actual sensor current is sensitive to the voltage. In this case the output voltage swing, which we require, is seen by the sensor. v o is = R D r s = 10k 100k 10k+100k 9.09k. An alternative intuition from the small-signal model is that ( the ideal signal current i s is divided between r s and R D. i in = i rs s (OPTIONAL SIDEBAR ON CURRENT DIVIDER) r s +R D ) Dr. Ryan Robucci Lecture IV 31 / 37

32 Common Gate Current Buer Example (3) An alternative using the common-gate conguration is shown. We'll assume the transistor along with V G is designed to obtain V ov = 0.5V at 1mA and λ = In this circuit the sensor sees resistance of R eq 1 g s = V on 2I = 250Ω if R D r ds. The output resistance is R D (r ds g s R S + r ds + R S ) = 10k (4m 100k 100k + 100k + 100k) 10k But what about the current i y I s? 100k 100k+250 now vs 100k 100k+10k berfore The current split is much better. The sensor sees a lower resistance yet the output resistance generating the output voltage swing is still high. The current buer has shielded the sensor from the voltage swing. Dr. Ryan Robucci Lecture IV 32 / 37

33 Common Gate Current Buer Example (4) Good Current-Current buer characteristics: Small input resistance, R IN R SOURCE : Input voltage does not uxuate with current and all intended current uxuations at the node are drawn into the buer. Large output resistance, R OUT R LOAD : Output current delivered to the load does not strongly depend on the output voltage (which means it is not sensitive to the load resistance). The ideal intended current is delivered to the load. However, there is one more advantge, even more critical...bw Resistor Current Buer Sensor Node Resistance 9.09 kω 250 Ω Sensor Node Time Constant τ = 9.09ns τ = 250ps Sensor Node BW 110 Mrad/s 4 Grad/s Sensor Node BW 17.5 MHz 637 MHz Dr. Ryan Robucci Lecture IV 33 / 37

34 Common Gate Current Buer Example (5) The lower impedance that the capacitor sees in parallel to it prevents the capacitor from drawing as much current. Therefore, the sensing circuit draws a larger percentage of the current. The -3dB frequency tells us when the capacitor draws an equal current to the resistance path it parallels. Transimpedance (I-to-V) Amplifier Current Buffer Dr. Ryan Robucci Lecture IV 34 / 37

35 Finding Time Constant of a Capacitor (1) We can nd the time constant of a capacitor by 1 replacing capacitor with a current source i t 2 nding the voltage v y created 3 R eq = v y i t 4 τ = R eq C Transimpedance (I-to-V) Amplifier Current Buffer + - Dr. Ryan Robucci Lecture IV 35 / 37

36 Finding Time Constant of a Capacitor (2) At ω = ω 3dB : R = 1 and i R = i C jωc The time constant provides us the frequency ω 3dB = 1 τ. At this frequency, the capacitor draws an equal magnitude of sinusoidal current to the resistance in parallel with it, though at a dierent 1 A 3dB = v x /i x = R = A = ω 3dB v x /i x = ( R 2 + R 2 + (R) 2 = A 3dB ) 2 1 ω 3dB C = 2 A DC Note log 10 ( 1 2 i C i R ) 3 Half Power Frequency: Also note 3dB 2 ) = A 3dB 2 = 1 A 2 DC 2 Dr. Ryan Robucci Lecture IV 36 / 37

37 Reminder Some hints discussed in solving small signal circuits Identify variables to eliminate (node voltages or currents) and try to choose and expression simplilest, most directly related to the input or output At times if there is a resistor between a node you have an expression for and another, nding the voltage accross the resistor can create a simple expression for the unknown voltage in terms of the known voltage When λ = 0 don't both with r ds throughout your work When calculating G m and consider the short a t the output, it is typical that a branch of your circuit can be quickly ignored Dr. Ryan Robucci Lecture IV 37 / 37

### Lecture 06: Current Mirrors

Lecture 06: Current Mirrors Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture VI 1 / 26 Lowered Resistance Looking into

### 3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

### ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

### Lecture 37: Frequency response. Context

EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

### ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

### ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

### Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

### Homework Assignment 09

Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

### Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)

### ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

### Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

### Homework Assignment 08

Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

### EECS 141: FALL 05 MIDTERM 1

University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

### and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

### Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14

Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS \$ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,

### ECE315 / ECE515 Lecture 11 Date:

ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)

### Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

### Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

### Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

### ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of

### ECE 6412, Spring Final Exam Page 1

ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.

### Figure 1: MOSFET symbols.

c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between

### ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

### Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

### Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

### CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

### Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

### P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

### Biasing the CE Amplifier

Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

### MOS Transistor Theory

MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

### UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam

### EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

EE05 Fall 205 Microelectronic Devices and Circuits Frequency Response Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Amplifier Frequency Response: Lower and Upper Cutoff Frequency Midband

### Electronic Circuits Summary

Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

### Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller

EECS 105 Spring 2017, Module 4 Frequency Response Prof. Ali M. Niknejad Department of EECS Announcements l HW9 due on Friday 2 Review: CD with Current Mirror 3 Review: CD with Current Mirror 4 Review:

### Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open

### 6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

### University of Toronto. Final Exam

University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

### MOS Transistor I-V Characteristics and Parasitics

ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

### EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

### Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers

6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,

### Systematic Design of Operational Amplifiers

Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 061 Table of contents Design of Single-stage OTA Design of

### Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at

### Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

### Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

### Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005

6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 23 Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier December, 2005 Contents:. Introduction 2. Intrinsic frequency response

### Lecture 4: CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

### The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

### CE/CS Amplifier Response at High Frequencies

.. CE/CS Amplifier Response at High Frequencies INEL 4202 - Manuel Toledo August 20, 2012 INEL 4202 - Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3

### Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

### ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

### EECS 105: FALL 06 FINAL

University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

### 55:041 Electronic Circuits The University of Iowa Fall Exam 2

Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.

### MOS Transistor Theory

CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

### Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace

### Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is

### ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

### Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to

### EE105 Fall 2014 Microelectronic Devices and Circuits

EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

### Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

### 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)

HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn

### CMOS Inverter (static view)

Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

### ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

### MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

### Lecture 12 CMOS Delay & Transient Response

EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

### EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time

### Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

### DC Biasing. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE230 Electronics I 15-Mar / 59

Contents Three States of Operation BJT DC Analysis Fixed-Bias Circuit Emitter-Stabilized Bias Circuit Voltage Divider Bias Circuit DC Bias with Voltage Feedback Various Dierent Bias Circuits pnp Transistors

### V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs

ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant

### EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced

### Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output

### High-to-Low Propagation Delay t PHL

High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to

### CHAPTER.4: Transistor at low frequencies

CHAPTER.4: Transistor at low frequencies Introduction Amplification in the AC domain BJT transistor modeling The re Transistor Model The Hybrid equivalent Model Introduction There are three models commonly

### Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

### Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

### CMOS Technology for Computer Architects

CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) 1 2 Recap Threshold Voltage

### MOSFET: Introduction

E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

### Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

### Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

### EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

### Time Varying Circuit Analysis

MAS.836 Sensor Systems for Interactive Environments th Distributed: Tuesday February 16, 2010 Due: Tuesday February 23, 2010 Problem Set # 2 Time Varying Circuit Analysis The purpose of this problem set

### Switching circuits: basics and switching speed

ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V

### EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2

### Electronics II. Final Examination

The University of Toledo f17fs_elct27.fm 1 Electronics II Final Examination Problems Points 1. 11 2. 14 3. 15 Total 40 Was the exam fair? yes no The University of Toledo f17fs_elct27.fm 2 Problem 1 11

### The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

### SOME USEFUL NETWORK THEOREMS

APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem

### EEE 421 VLSI Circuits

EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

### Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

### Voltage AmpliÞer Frequency Response

Voltage AmpliÞer Frequency Response Chapter 9 multistage voltage ampliþer 5 V M 7B M 7 M 5 R 35 kω M 6B M 6 Q 4 100 µa X M 3 Q B Q v OUT V s M 1 M 8 M9 V BIAS M 10 Approaches: 1. brute force OCTC -- do

### 1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

### CMOS Analog Circuits

CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100

### At point G V = = = = = = RB B B. IN RB f

Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F

### Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC

ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o

### 6.012 MICROELECTRONIC DEVICES AND CIRCUITS

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6.012 MICROELECTRONIC DEVICES AND CIRCUITS Answers to Exam 2 Spring 2008 Problem 1: Graded by Prof. Fonstad

### LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter

Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation

### ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

### Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

### Electronics II. Midterm II

The University of Toledo f4ms_elct7.fm - Section Electronics II Midterm II Problems Points. 7. 7 3. 6 Total 0 Was the exam fair? yes no The University of Toledo f4ms_elct7.fm - Problem 7 points Given in