Class E Design Formulas V DD

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1 Class E Design Formulas V DD RFC C L+X/ω V s (θ) I s (θ) Cd R useful functions and identities Units Constants Table of Contents I. Introduction II. Process Parameters III. Inputs IV. Standard Class E Design Procedure V. Alinikula Class E Design Procedure VI. Choi's Class E Design Procedure VII. References VIII. Copyright and Trademark Notice Introduction This file is a modification of the routine class-e.mcd. The modifications include:. The addition of finite Q component losses in the overall efficiency of the amplifier.. The effects of a finite device output capacitance. Later the effects of the nonlinearity of this capacitance is also added. This derivation is from reference []. 3. Units are added. 4. The overall format of the routine is modified for easier use. A problem with this analysis is that it doesn't take into account overall transmitter chain efficiency due to finite gain loss of the power amplifier. This may set an upper limit on the device size, which will in turn make the drain capacitance part linear capacitance and part nonlinear capacitance. The design also does not take into account the input power back-off required to meet ACPR (adjacent channel power ratio) requirements. This will also degrade efficiency.

2 Process Parameters C j C jsw Bottom Plate Capacitance for Zero-Biased Reverse Biased.4 ff Q 7 Q of Matching Network (Optimum Value can be found: Higher value leads to narrower band and more dependence on process variations and finite Q elements. Lower value degrades efficiency directly) f.9ghz Center Frequency t r.ns Rise Time Standard Class-E Synthesis Procedure ω f ω Grad sec.577( V dd V sat ) R s R s.496 ohm P a QR s L s L s.85 nh ω C p C p.77 pf ωr s µm Sidewall Capacitance for Zero-Biased Reverse Biased Diod.4 ff µm m j.77 Exponent for Reverse Biased Diode Capacitance V bi V Fermi Potential for Reverse Biased Diode µ N 3 cm V sec C OX Device Effective Mobility ma_µm Device Gate Capacitance per Unit Area ff µm Electromigration Limition on Line Width.5 ma µm L min.5µm Minimum Line Width V TN.7V Threshold Voltage Inputs V dd V Supply Voltage V sat.v Minimum Device Drain to Source Voltage P a.5watt Power Available at Drain C s C p + C s =.767 pf Q Q.8 V p 3.56V dd.56v sat V p 6.6 V.8 A + f tr A =. = Center Frequency = Device Load Resistance = Matching Inductance = Matching Capacitances = Peak Output Voltage

3 .8 A + Q f t r A =. v Dmax atan V dd v Dmax 7.4 V η R η.83 R.365 V sat + I dc Solution Assuming a Nonlinear Capacitor = V bi ωc j V bi z = V bi ( n + ) v D θ v D θ v D θ, z v out I DC θ ( n + ) + R cos( θ + φ) cos( φ) + v out θ + ( cos( θ + φ) cos( φ) ) + RI DC Device Output Capacitance = Load Resistance = Load Reactance = Maximum Drain Voltage = Drain Efficiency z V bi θ n + + cos( θ) + sin( θ) n+ + Drain Voltage Using Root Finder to solve for z A P a I dc V dd ( A) V sat ( 6 V dd + A A ) I dc ma 6.5 I p I dc +.86 I p.986 amp Q P dc V dd I dc P dc.456 watt P a η η P dc = DC Current = Peak Current = DC Power = Efficiency Alinikula's Class E Design Analyis and Synthesis Solution Assuming a Linear Capacitor m j n n m j P a C D C D = 7.59 pf ωv dd 8 V dd R R.846 Ω P + 4 a ( X 4) V dd X.7 Ω P + 4 a = Substitute parameter for mj n+ n

4 V dd v D ( θ, z guess ) dθ 5 5 z guess V dd z I DCguess z.64 R I DC z ωc j V bi I DC ma X L L.49 nh ω C C pf ω X C res C res pf QωR QR L res L res.85 nh ω n+ z v Dmax V bi atan + v Dmax V n + N I DCguess z guess ωc D V bi root V dd I DC v D θ, z guess dθ, z guess v D ( θ, z) cos( θ) dθ φ atan φ 8.9 deg v D ( θ, z) sin( θ) dθ a v D ( θ, z) cos( θ) dθ + v θ D ( θ, z) sin( θ) d a V 8 V dd R R.846 ohm P + 4 a X Rtan φ atan X.3 Ω 3.56V dd C j z atan C D V bi 4 C j = Variable used for more efficient calculation. = Fundamental Frequency Phase Angle at node A = Fundamental Frequency Amplitude at node A = Load Resistance = Load Reactance = pf Drain Capacitance = DC Current = Load Inductance (if X is positive) = Load Capacitance (if X is negative) = Resonant Capacitance = Resonant Inductance = Maximum Drain Voltage

5 N I DC ma_µm 3L min N = Number of Devices in Parallel The following equation for the drain capacitance is based on a layout, where the drain is layed out C j N C j3l min W + C jsw W + 3L min = C j 3L min C jsw N W C j 3L min + C jsw W W N W mm Length L min + 3L min N Length.5 mm Area W 4L min N Area.8 mm R on R on.9 Ω W µ N C OX ( V dd V TN ) L min R η η = % R +.365R on W = µm Width of Each Segment = Width of Overall Device = Length of N Devices = Overall Area of Device = On Resistance of Device Drain Efficiency Choi's Class E Design Procedure Notes about this design procedure:. It does not include the effects of inductive source degeneration, but instead models it as a resistive source degeneration. The paper does not say what the degeneration is, but it implies it is the same as the gate impedance. It does not calculate the input impedance, which is necessary for matching to the driver amplifier. This impedance changes during the cycle, so what value do you use for the input matching network? The average value? 3. It does not calculate the required input signal swing, Vs, to generate the required output power. It is possible to use the equations in reverse to find the required Vs, but will surely be non-linear, so iterative technques must be used. Since iterative techniques must be used it might be more appropriate not to solve the equations in reverse, but instead use constraint-based optimization to meet the two conditions of output power and maximize PAE. 4. It does not include parasitic losses of the output matching network. This should be a simple addition. ω = 9 MHz Center frequency of oscillator R 5ohm P out P a P a =.5 watt Designed output power at the drain. P out watt P out C d C d 4.7 pf ωv dd = Drain capacitance µ N 546 cm V sec Device mobility K n µa r m Instrinsic transconductance V Metal resistance 5.7 Ω sq gatefinger

6 r m Metal resistance.7 sq Ω r c.8 gatefinger Metal-poly contact resistance r c R s ( n) r m + n Resistance in the source R s n =.68 Ω ρ gate Polysilicon sheet resistance.9 Ω sq C GD 3 farad m Gate to drain overlapp capacitance W 5µm Width of one finger L.5µm Length of one finger r g c gs c gd ρ gate W 3 L K n W L µ N C GD W + r c r g r g = 6.33 Ω R g ( n) r m + n c gs =.9 pf c gd C gs ( n) nc gs =.38 pf C gdo ( n) nc gd Gate resistance Gate to source capacitance Gate to drain capacitance I d ( ) K n W = V gs ( ) V ds ( ) V ds ( ) L = I DC V gsmag ( n, ) ( C gs ( n) + C gd ( n) ) + ω R g ( n) + R s ( n) C gd ( n) C gdo ( n) + C gs ( n) 4.3V V gsmag ( n, ) = 4.59 V χ( n) atan ω R g ( n) + R s ( n) C gs ( n) + C gd ( n) χ( n) =.337 V gs θ V gsmag n V gs θ, n, sin θ + χ( n) I d θ R s n V gsmag ( n, ) sin θ + χ n ( ) V gs, n, =.34 V V gs (,, V) V gs (,, V) V gs (,, 5V) ( ) ωr s ( n) C d V dd V gs, n, ωc d L K n W V gs, n, =.4 kg m s -3 A - a( n) ωc d R s ( n) a( n) =.696 6

7 a( n) ωc d R s ( n) a( n) = ωr s ( n) C d =.34 a( n) ωr s ( n) C d b n, a( n) =.696 ( ) ωr s ( n) C d V dd V gs, n, ωc d L K n W V gs, n, =.79 b n, b n, =.79 b n, c( n) 4ωC d V dmin ( n, ) V V gsmag n, sin + χ( n) + ωr s ( n) C d kg m s -3 A - L K n W V dd b n, + c( n) = 4 V 4a n b n, a( n) c( n) + 4ωC d V dd R s ( n) c( n) 4ωC d V dd W K n L V dmin ( n, ) = 3.94 V 4ω C d W K n L c( n) = 4 V 3 V dmin (, ) V dmin ( n, val ) I DC ( n, ) P DC = I DC V DD 4 ( ) ωc d V dd V dmin n, + ωr s ( n) C d P DC ( n, ) val.5v V dmin n, ( ) ωc d V dd V dmin n, + ωr s ( n) C d I DC ( n, ) =.374 amp V dd P DC ( n, ) =.748 watt 7

8 P DC (, ).5 ifθ V d θ 5 5 <, I DC ( n, ) R s ( n) + sin( θ) cos θ + V dmin ( n, ) I DC n,..., θ ωc d + V dmin n, + 3 cos θ I DC ( n, ) sin θ R s ( n)... ifθ I d θ <, I DC ( n, ) + sin( θ) cos( θ), V V d ( θ) V dmin ( n, ) θ I d ( θ) 4 6 θ.3 I DC( n, ) V dmax n, ωc d + V dmin n, + I DC n, R s ( n) V dmax (, ) P ( n, V ) ω r g c gs + c gd V ( 8c + c ) + V n, V c

9 P in ( n, ) P in ( n, ) ω 4 ω 4 r g c gs + c gd c gs + c gd + V dmax n, + ωr g c gs + c gd n nr m + r g c gs + c gd + ω nr m + r g c gs + c gd c gd c gd c gs + c gd + V dmax n, P in (, ).5 P out ( n, ) I DC n, R + ωr s ( n) C d P out (, ) Efficiency( n, ) 5 5 R I DC n, V dd ωr s ( n) C d Efficiency(, ) 5 P out Gain = Gain(, ) P in 5 5 R I DC n, ωr s ( n) C d ω R g ( n ) ( C gs ( n) + C gdo ( n) ) ω R g ( n) C gs ( n) + C gdo ( n) C gs ( n) + C gdo ( n) + V dmax ( n, ) C gdo 4 9

10 Gain, 4 4 PAE n, Efficiency P in P DC References [] "Design of a Class E Power Amplifier with a Nonlinear Parasitic Output Capacitance," by Petteri Alinikula et. al., IEEE Transactions on Circuits and Systems II, vol. 46, no., February 999. [] "Class E CMOS Power Amplifier," by Martin Tsai. [3] "The use of parasitic nonlinear capacitors in class E amplifiers," by M. J. Chudobiak, IEEE Transactions on Circuits and Systems, vol. 34, pp December 994. [Sokal] N.O. Sokal and A. D. Sokal, "Class E-A new class of high-efficiency tuned single-ended switching power amplifiers," I.E.E.E. Journal of Solid State Circuits, vol. SC-, pp , June 975. [Li] C. Li and Y. Yam, "Analysis and design of the class E amplifier with non-zero ON resistance," Microwave Opt. Technology Letters. vol. 7, pp , May 994. [Choi] David K. Choi and Stephen Long, "A Physically Based Analytic Model of FET Class-E Power Amplifiers--Designing for Maximum PAE." Copyright and Trademark Notice All software and other materials included in this document are protected by copyright, and are owned or controlled by Circuit Sage. The routines are protected by copyright as a collective work and/or compilation, pursuant to federal copyright laws, international conventions, and other copyright laws. Any reproduction, modification, publication, transmission, transfer, sale, distribution, performance, display or exploitation of any of the routines, whether in whole or in part, without the express written permission of Circuit Sage is prohibited.

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