Impact of Supply and Threshold Voltage Scaling on Performance of Cu and CNT Interconnects

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Volume 118 No. 5 018, 117-16 ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu ijpam.

1 Volume 118 No , ISSN: (printed version); ISSN: (on-line version) url: ijpam.eu Impact of Supply and Threshold Voltage Scaling on Performance of Cu and CNT Interconnects 1 C. Venkataiah, K.Satyaprasad and 3 T. Jayachandra Prasad 1 RGMCET, JNTUK, Kakinada, A.P, India. venki.challa@gmail.com JNTUK, Kakinada, A.P., India. prasad_kodati@yahoo.co.in 3 RGMCET, Nandyal, A.P., India. jp.talari@gmail.com Abstract In VLSI sub-micron interconnects, the internal parasitic creates the problems like power dissipation and propagation delay along the line.thisproblems leads the motivation towards design of high speed and low power interconnects. The present work reflects the impact of threshold and supply rail scaling on power dissipation and delay in interconnects. Further, repeater insertion leads to delay minimization in global interconnects, but consequently power and area will increase. Therefore, the best substitute technique is supply rails scaling, thatreduces the power dissipation and number of repeater requirement for reduction of delay in global interconnects. Thus, the cirit performance parameters such as power and delay are analyzedby the insertion of voltage scaled repeaters in copper and CNT interconnects.it is observed that CNT interconnects provides better performance than copper in terms of power and delay. All the simulation has done at 3nm technology node. Key Words:Copper (Cu), carbon nanotube (CNT), global interconnects, repeaters. 117

2 1. Introduction In recent days, it is much needed to deal with low power and high speed devices in integrated cirit, but in deep submicron technology interconnect performance is important parameter than cirit performance. In lower technologies, the delay in interconnects is due to parasitic elements and it is dominant than gate delays [1]. The propagation delay in interconnects is mainly due to resistance of the interconnect material. In practice, interconnect not only contains resistors but also contains parasitic inductance and capacitance []. Based on functionality, the chip size and density is increased as a result the resistance and capacitance of interconnects also increases. In digital systems, many methods are proposed to achieve low power dissipation from process level to algorithm level. In lowering the power consumption and delay, device characteristics and interconnect properties are the key constraints to deal with. Further, cirit design styles, scaling in power supply and threshold voltages are also considered as to reduce power consumption at lower transistor level [3-5]. Architecture-level measures include smart power management of various system blocks, utilization of pipelining and parallelism, and design of bus structures [4]. In this paper, a voltage scaling method has done with number of repeaters for reduction of power and delay and simulation has observed with different interconnect materials such as copper and CNT. Basically interconnects are used in routing the clock and process the logic signal to various other blocks. Interconnects are classified based on its parasitic elements and length such as local, global and semi global interconnects [6]. Local interconnects are very small in size, having less parasitics and cover small distance in the chip. Semi-global are large than local interconnects and they provide high parasitic than local. This are basically used to connect input and output ciritry with large modules. Global interconnects are the one provides larger parasitics because of large in size and generally used to route the clock, power supply and other long distance communications in various functional blocks. Normally used interconnect materials are copper and aluminium because they have high melting point, low resistivity, ease of deposition and good adhesion to dielectrics.as technology is scaling down the resistivity of copper also increases and this imparts propagation delay on the line. Therefore, the better alternative to copper as the size shrinking is done is carbon nanotube (CNT). CNT are the most promising materials used to work in high speed and low power interconnects. These are classified as Single-walled Carbon Nanotubes (SWCNTs) and Multi-walled Carbon Nanotubes (MWCNTs). Generally, a single SWCNT has large resistance due to its high quantum resistance and not suitable for interconnect applications. Hence, a bundle of SWCNT interconnects are best suit for dealing with high speed interconnects. SWCNT interconnects achieve better performance than copper interconnects in IC technology [7-9]. 118

3 In copper and CNT interconnects, repeaters are used at intermediate and global level to reduce time delays. One observation is done on using CNT interconnects, that total time delay is reduced by larger extent when compared to copper interconnects and total repeater requirement also diminished by one third than copper. While considering inductance effect, the time delay dependency is super-linear on interconnect length [10-1]. In this paper, repeaters are inserted in CNT interconnects to reduce time delays and repeaters are assumed to be CMOS inverters. The rest of the paper is organized as follows, section deals with extraction of RLC parameters and its cirit simulations. The performance analysis to minimize delay and power is disssed in section 3. Finally section 4 concludes the work.. RLC Parameter Extraction for Cu and CNT Interconnects The parameter extraction for copper and CNT is reported in following sections A) RLC Parameter Extraction for Cu Interconnect Generally, the empirical relations used to callate the parasitic values of copper interconnect based on [,13] are: The resistance of the interconnect is given by l R (1) d t The self and mutual inductance of the interconnect is given by d t. l l L () l ln d t. l w l LMCu 1 ln (3) l w The capacitances like ground capacitance and coupling capacitance are given as 3. d.3 1 h 1 0.7( h / s ) Cgd 1 1.5( h / s ) (4) ( h/ t) 119

4 Near-end Farr-end International Journal of Pure and Applied Mathematics C t s 1.07( s / h) ( s / d ) ( s / d ) ( s/ h) 0.09 (5) cc 0.16 wherer is resistance of Cu interconnect, L is the inductance of Cu wire, L MCu is mutualinductance between any two interconnects, Cgd is the ground capacitance, Ccc is the coupling capacitance, l is the length of the line, d is the line width, t is the thickness, ρ is the resistivity of copper wire, h gnd height above from ground level, spacing is s, d is diameter. B) RLC Parameter Extraction for CNT Interconnect In this work, we considered the ESC model of acnt bundle for RLC parameters and it has been reported in many works [], [14-16]. The resistance is expressed by considering the quantum resistance (R q ), contact resistance (R mc ) and scattering resistance (R). Here R is considered as line resistance, R q and R mc are considered as lumped resistances placed at the contacts terminals. R lump Rdz dz L K dz L M dz R lump C Q dz C E dz l Fig. 1: ESC Model of CNT Bundle 1 Rq R lump, ESC N 4 Rmc (6) where Rq h / e 5.8k Rq R ESC = 4N λ (7) mfp where 3 10 d mfp with T K T / T 0 10

5 whereh, e and N are the Planck s constant, electron charge and number of conducting shells in bundle respectively. The capacitance is modeled by considering the quantum capacitance (C Q ). It is given by q C Q = hvf (8) For N conducting shells, the equivalent quantum capacitance C Q,ESC is given by 4 q C Q,ESC = N hvf (9) Inductance is modeled by considering the kinetic inductance (L K ). It is given by L = K h q v F (10) For N conducting shells, the equivalent kinetic inductance (L K,ESC )is expressed as L = K,ESC 1 h (11) N 4 q v F where v F is the Fermi velocity considered as m/s for CNT. C). Repeater Insertion for Delay Minimization The CMOS repeater insertion along with the interconnect line is shown in Fig. Where the interconnect is driven by CMOS driver which is practical and nonlinear, the load is terminated with capacitance and the buffers at the intermediate stage is used to sharpen the transient time delay.the interconnect materials is basically made of copper and SWCNT. The response at the far-end is analyzed with various test cases disssed in section 3. The RLC parameters for the interconnect configuration shown in Fig is reported in section. 3. Results and Disssions In this section, a detailed analysis is reported to analyze the performance of VLSI interconnects in terms of far-end delay, crosstalk noise, power dissipation. In Fig 3(a), a transient input pulse of 0.7V is given at the input of first interconnect and at far-end of second interconnect with respect to first interconnect a noise peak is observed due to crosstalk, shown in Fig 3(a). Further, in Fig 3(b) the effect of repeater insertion on far-end delay is analyzed for both copper and CNT interconnects. V g Rct Rct Cdd z=0 SWCNT Interconnects with CMOS repeaters z=l C Ld SWCNT Interconnects Repeaters Fig. : Non-linear Driver, Interconnect with Buffer and Capacitive Load System 11

6 (a) (b) Fig. 3: (a) Crosstalk Noise on Interconnect with Respect to Interconnect 1 (b) delay Minimization Using Repeater Insertion Table 1: Far-end delay of Cu with Respect to Supply Voltage Variation for a Fixed Threshold Voltage with Repeaters Cu Delay(ps) SupplyVoltage -Rep 4-Rep 6-Rep 8-Rep 10-Rep Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Table : Far-end Delay of CNT with Respect to Supply Voltage Variation for a Fixed Threshold Voltage with Repeaters CNT Delay(ps) SupplyVoltage -Rep 4-Rep 6-Rep 8-Rep 10-Rep Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Repeaters are often used to minimize the delay to propagate a signal through the interconnect lines. The repeaters divide the interconnect into smaller subsections thus making the time delay reduction. It is worth noted that copper interconnects have high far-end delay when compared with CNT interconnects. The delay of CNT interconnects is effectively decreases on increasing the number of repeaters at the intermediate stage of the interconnects.due to the domination of interconnect delay on gate delay in the deep sub micrometer VLSI cirits there is an increase in the delay. Moreover, optimum voltage scaling is an interesting choise to work with VLSI interconnects and the effect is graphically shown in Fig 4. Where the supply voltage is scaled on absicca and delay on ordinate, as the magnitude of voltage increases there exists a drastic rate of change in far end delay and it is high for copper interconnects. However for CNT interconnects, 1

7 this effect is negligible. A clear observations is done on far-end dealy analysis for both copper and CNT interconnects with scaling in threshold is reported in table 1 and table, respectively. It is observed that, as we decrease the threshold voltage, the dealy in copper interconnect is also decreses and this shows the direct dependancy of threshold voltage on delay. Therefore, less threshlod in interconnects is an additional advantage to reduce the delay in VLSI interconnects. Fig. 4: Variation of Far-end Delay with Respect to Supply Voltage Table 3: Power Dissipation in Cu Interconnects with Respect to Supply Voltage Variation for an Arbitary threshold Voltage with Repeaters Cu Power Consumption(mW) SupplyVoltage -Rep 4-Rep 6-Rep 8-Rep 10-Rep Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Table 4: Power Dissipation in CNT Interconnects with Respect to Supply Voltage Variation for an Arbitary Threshold Voltage with Repeaters CNT Power Consumption(mW) SupplyVoltage -Rep 4-Rep 6-Rep 8-Rep 10-Rep Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Vt=0.5V Vt=0.V Fig. 5: Variation of Far-end Delay with Respect to Supply Voltage 13

8 Another important design constrait that specifies the figure of merit of an interconnect system is power dissipation. From Fig 5, it is evident that supply voltage effect on power dissiaption is high for copper interconnect and for CNT interconnect this effect is less than that of copper. Further, the power dissipation in copper interconnects is almost linear against supply, this provides the information that CNTs have very enhanced performance as supply rail concern. Further, the variation in power dissipation with respect to supply voltage for an arbitary variation in threshold voltage is reported in table 3 and table 4 for copper and CNT interconnects, respectively. 4. Conclusion The impact of threshold voltage and supply voltage scaling on power dissipation and delay in interconnects is analyzed, the tabular and graphical observations are reported. The repeater insertion at the intermediate stage is reduced the delay in global interconnects. It is proved that the best technique to reduces power dissipation is supply voltage scaling and usage of optimum number of repeaters in global interconnects. Further, the cirit performance parameters such as power and delay are also analyzed by the insertion of voltage scaled repeaters in copper and CNT interconnects. Finally, it is evident that CNT interconnects provides better performance than that of copper in terms of power and delay. References [1] Naeemi A., Sarvari R., Meindl J.D., Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI), IEEE Electron Device Letters 6() (005), [] Debaprasad Das, HafizurRahaman, Analysis of Crosstalk in Single- and Multiwall Carbon Nanotube Interconnects and Its Impact on Gate Oxide Reliability, IEEE Transactions on nanotechnology 10(6) (011). [3] Kang S.M., Yusuf Leblebici, CMOS Digital Integrated Cirits (Analysis and Design), 3rd ed. McGraw-Hill (013). [4] Michael Opoku Agyeman, Wen Zong, Alex Yakovlev, Kin-Fai Tong, TerrenceMak, Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity, J. Low Power Electron. Appl 7() (017). [5] Venkataiah C., Tejaswi M., A Comparative Study of Interconnect Cirit Techniques for Energy Efficient on-chip Interconnects, International Journal of Computer Applications 109(4) (015). [6] Rajeevan Chandel, Sarkar S., Repeater insertion in global interconnects in VLSI cirits, Emerald Group Publishing Limited, Microelectronics International (005). 14

9 [7] Li H., Xu C., Srivastava N., Banerjee K., Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects, IEEE Trans. Electron Devices 56(9) (009) , Sep [8] Venkataiah C., Satya Prasad K., Jaya Chandra Prasad T., Effect of Interconnect parasitic variations on cirit performance parameters, IEEE International conference on communication and electronics systems(016). [9] Manoj Kumar Majumder, Nisarg D. Pandya, Kaushik B.K., Manhas S.K., Analysis of MWCNT and Bundled SWCNT Interconnects: Impact on Crosstalk and Area, Electron Device Letters (01). [10] Majumder M.K., Das P.K., Kaushik B.K., Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects, Microelectron. Reliab. 54(11) (014), [11] Kumar V.R., Kaushik B.K., Patnaik A., Crosstalk noise modeling of multiwall carbon nanotube (MWCNT) interconnects using finite-difference time-domain (FDTD) technique, Microelectron. Reliab. 55(1) (015), [1] Dhiman R., Chandel R., Delay analysis of buffer inserted sub threshold interconnects, Analog IntegrCirc Sig Process, Springer (016). [13] Li H., Yin W.Y., Banerjee K., Mao J.F., Cirit modelling and performance analysis of multi-walled carbon nanotube interconnects, IEEE Trans. Electron Devices 55(6) (008). [14] Srivastava N., Li H., Kreupl F., Banerjee K., On the applicability of single-walled carbon nanotubes as VLSI interconnects, IEEE Transactions on Nanotechnology 8 (009), [15] Amore M.D., Sarto M.S., Tamburrano A., Fast transient analysis of next-generation interconnects based on carbon nanotubes, IEEE Trans. Electromagnetic Compatibility 5 (010), [16] Lamberti P., Tucci V., Impact of the Variability of the Process Parameters on CNT-Based Nanointerconnects Performances: A comparison between SWCNTs bundles and MWCNT, IEEE Transactions on Nanotechnology 11 (01),

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COMPARATIVE ANALYSIS OF CARBON NANOTUBES AS VLSI INTERCONNECTS

International Journal of Science, Engineering and Technology Research (IJSETR), Volume 4, Issue 8, August 15 COMPARATIVE ANALYSIS OF CARBON NANOTUBES AS VLSI INTERCONNECTS Priya Srivastav, Asst. Prof.