Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations

Transcription

1 Chinese Journal of Electronics Vol.4, No.1, Jan. 015 Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations LI Jianwei 1,,DONGGang 3, WANG Zeng 4 and YE Xiaochun (1.Faculty of Automation and Information Engineering, Xi an University of Technology, Xi an 71004, China) (.State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing , China) (3.Microelectronics Institute, Xidian University, Xi an , China) (4.College of Physics Sicence, Qingdao University, Qingdao 66071, China) Abstract When operating frequency is over several gigahertz, the effect of inductance plays an important role and should be included for accurate and speed crosstalk noise analysis. And for new generation IC (Integrated circuit) design tools, the crosstalk noise analysis tools should consider the influence of process variations. In this paper, we propose coupled RLC crosstalk noise distributed parameter model with capacitive load termination. And we develop the framework that how to use the crosstalk noise model for process variations. Our results show that compare with HSPICE, the critical data errors of proposed model are within 1% and the relative errors occurred between calculated values for process variations and HSPICE Monte Carlo simulation values are less than 5%. The key features of the new model include: (1) The impact of inductance on crosstalk noise is considered; () The model can be used for process variations analysis; (3) The model reflect the effects of load capacitance directly; (4) The numerical inversion of Laplace transform is introduced for improving speed. So the proposed model meets the needs of future IC design both in speed and accuracy. Key words Crosstalk noise, Interconnect, Inductance, Process variation, Statistical. I. Introduction The International technology roadmap for semiconductor (ITRS) released in 011 predict that the feature size of ASIC will continue to scale down to 1nm by 00 [1]. Technology scaling deepens unresolved parasitic effects and increases the density of interconnects as well []. Some challenges will be dominant in future IC design. On the one hand, the effect of inductance plays an important role when operating frequency is over several gigahertz [3,4], and the effect can t be ignored [5,6], on the other hand, for continued scaling of feature sizes, the influence of process variations is one of the most important factors on performance of VLSI [7]. So it is important to focus on modeling the impact of process variation on interconnect performance on reliability designs and optimization designs of VLSI [,9]. At present, some research has been developed in interconnect crosstalk and process variation [10]. In Refs.[6, 11 13], some distributed RLC interconnect models were built, which include single line model and coupled line model. The expressions of these models in time domain were derived in these papers. For they are difficult to be solved, these models can t be directly used in simulation of interconnect. Furthermore, the influence of process variations is not considered in these models. In Ref.[3], the coupled RLC interconnects model with capacitance load is built. The influence of process variations is considered in this model, but the model expressions are independent of load capacitance. The model can t reflect the effects of load capacitance. And the effects of line-width variation and line-space variation on crosstalk are mutually independent, which is discrepancy with the reality. In this paper, firstly, we propose coupled RLC crosstalk noise model with capacitive load termination. The effect of capacitive load is considered in this model. The waveforms of voltage and current at any point along the couple lines can be gotten by the proposed model, which is different from lumped parameter model. Compare with HSPICE, the critical data errors of proposed model are within 1%. And then, the framework that how to use the proposed model for process variations is developed. The relative errors occurred between calculated values and HSPICE Monte Carlo simulation values are less than 5%. Furthermore, the numerical inversion of Laplace transform is introduced successfully in math operation course to improve operation speed. So the proposed model achieves Manuscript Received Apr. 013; Accepted June 013. This work is supported by the Opening Project of State Key Laboratory of Computer Architecture (No.CARCH01109), the National Natural Science Foundation of China (No ), and the Key Discipline Project in Shaanxi Province (No ).

2 4 Chinese Journal of Electronics 015 the needs both speed and accuracy for future IC design. II. Coupled Crosstalk Noise Model 1. Coupled-transmission-line model The two distributed coupled RLC lines are show in Fig.1. One line is switching and the other is quiet. The driver for aggressor line is replaced with a voltage ramp V s in series with a Thevenin resistance R tr. To simplify the calculation, our hypothesis is that victim line and aggressor line with the same structure, but the driver is modeled as the resistance connected to ground. Receivers at the far end of the lines are modeled Fig. 1. Coupled-line configuration as lumped capacitive loads C L. As shown in Fig.1, r, c g,c m,l s and l m are the line resistance, ground capacitance, coupling capacitance, self-inductance and mutual inductance per unit length of the line, respectively. At any point x along the line, V A,I A,V Q and I Q are the voltage and current waveforms on aggressor line and victim line, respectively. According to transmission line theory, the coupled-transmission-line satisfy the following set of differential equations VA VQ IA IQ = ria + lssia + lmsiq = riq + lssiq + lmsia = cgsva + cmsva cmsvq = cgsvq + cmsvq cmsva To simplify the calculation, sum-mode (V +,I +) and difference-mode (V,I ) are defined as follows V + = V A + V Q, V = V A V Q (1) I + = I A + I Q, I = I A I Q () Getting the second-order partial derivative of the first two equations in Eq.(1) and making the substitution of last two equations in Eq.(1) into them gives V + =(ls + lm)cgs V + + rc gsv + V =(l s l m)(c g +c m)s V + r(c g +c m)sv The two equations in Eq.(3) can be expressed as a unified equation. V uni =(lcs + rcs)v uni (4) where V uni,r,cand l are the sum- and difference-mode voltage, resistance, capacitance and inductance, respectively. In summode V uni = V +, c = c g, l = l s + l m and in difference-mode V uni = V, c = c g +c m, l = l s l m. (3) The general solution to Eq.(4) in the Laplace domain is V uni = C uni1e γx + C unie γx (5) where γ = lcs + rcs. So, the current in sum-mode and difference-mode is given by I uni = 1 V uni (6) (r + l)s The current in the Laplace domain can be expressed as I uni = 1 Z ( Cuni1eγx + C unie γx ) (7) r r + ls where Z = cs. So, the voltage and current in sum-mode and differencemode are given by V + = V uni(l = l s + l m,c= c g) I + = I uni(l = l s + l m,c= c g) () V = V uni(l = l s l m,c= c g +c m) I = I uni(l = l s l m,c= c g +c m) Based on the definition of sum-mode and difference-mode, the voltage and current waveforms on aggressor line and victim line are V+ + V I+ + I V A =, I A = V+ V I+ I V Q =, I Q = (9). Coupled-transmission-line model with capacitive load termination Generally, the driver and receiver for interconnect in typical CMOS design are CMOS gates. Equivalent circuit of CMOS gates mainly include output resistance (R tr), output capacitance (C p) and input capacitance (C L). In general, the percentage error caused by neglecting both C p and C L,and C L is about three times that caused by neglecting C p alone for different driver size [1]. For the increasingly prevalent CMOS technology, the development trend of output parasitic capacitance is decreases continuously. Therefore, the output capacitance of the driver is neglected in this analysis (Fig.1). The victim line and aggressor line satisfy the following set of equations under these boundary conditions x =0and x = L. V s R tri A(x =0)=V A(x =0) R tri Q(x =0)=V Q(x =0) V A(x = L) = 1 I Q(x = L) (10) V Q(x = L) = 1 I Q(x = L) On the basis of the sum-mode and difference-mode, Eq.(10) can be expressed as set of unified equations < V s R tri uni(x =0)=V uni(x =0) : V uni(x = L) = 1 (11) I uni(x = L) So C uni1 and C uni in Eq.(5) are given by C uni1 = ZV s(1 Z)e γl (R tr + Z)(1 + Z)e γl (R tr Z)(1 Z)e γl

3 Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations 5 C uni = ZV s(1 + Z)e γl (R tr + Z)(1 + Z)e γl (R tr Z)(1 Z)e γl After applying these boundary conditions, the voltage and current in sum-mode and difference-mode are given by V + = C 1+e γ +x + C +e γ +x where V = C 1 e γ x + C e γ x I + = 1 ( C 1+e γ +x + C +e γ +x ) Z + I = 1 ( C 1 e γ x + C e γ x ) Z C 1+ = C uni1(z = Z +,γ = γ +) C + = C uni(z = Z +,γ = γ +) C 1 = C uni1(z = Z,γ = γ ) C = C uni(z = Z,γ = γ ) Z + = Z(l = l s + l m,c= c g) Z = Z(l = l s l m,c= c g +c m) γ + = γ(l = l s + l m,c= c g) γ = γ(l = l s l m,c= c g +c m) (1) (13) According to Eq.(9), it will be easy to get the results for the voltage and current at any position x along the victim line and aggressor line. III. Framework for Process Variations 1. Extracting parameters of process variation In general, process variations of interconnect consist of four components: metal thickness (T &T ), Inter-layer dielectric (ILD) thickness (H&H ), linewidth (W &W ) and linespace (S&S ) as shown in Fig.. Process variations of interconnect result in some changes in their electrical properties. For the structure shown in Fig., the line resistance (r), line-to-ground capacitance (c g), line-to-line capacitance (c m), self-inductance (l s) and mutual inductance (l m) per unit length can be expressed as Eq.(14) [14,15] 1 r =ρ ef f WT «c g W T = +4.0 ε ox H T H «1.773 S S H c m = T «ε ox S exp 4S S +.014H «0.574 W W S exp S «S +6H» l s = μ0 L ln π W + T «0.071 H H +.961S « W + T L «, « L (W + T )» «l m = μ0 L ln 1+ S, π S L L > S (14) Fig.. Cross-section of coupled-line Here, ρ ef f is effective resistivity. ε ox is effective dielectric constant. μ 0 is permeability of vacuum.. Statistical modeling of crosstalk noise For modeling the impact of process variability on crosstalk noise, we need to capture the effect of process variations on the electrical parameters. In order to wider applicability, the relative values are used to capture the variability of geometric dimensions instead of absolute values. So we define Δw = ΔW W, Δs = ΔS S ΔT ΔH, Δt =, Δh = T H (15) where ΔW, ΔS, ΔT and ΔH are the absolute values of the variability of geometric dimensions, and Δw, Δs, Δt and Δh are the relative values of the variability of them. So the electrical parameters, which effect by process variations can be expressed as r =[1+f r(δw, Δt)]r nom c g =[1+f cg (Δw, Δs, Δt, Δh)]c g nom c m =[1+f cm (Δw, Δs, Δt, Δh)]c m nom l s =[1+f ls (Δw, Δt)]l s nom l m =[1+f lm (Δs)]l m nom (16) Here, r nom,c g nom,c m nom,l s nom and l m nom are the electrical parameters which don t effect by process variations. f r,f cg,f cm,f ls and f lm are the relation functions of the change rates about the physical dimensions and the electrical parameters. 3. Modeling procedure In Section IV, the approach will be test on a variety of test cases. The overall modeling flow is summarized below. Need the following information: (1) A couple of wires; () Process variation in geometric dimensions. Perform the follow steps for computing crosstalk noise distribution. Step 1 Extract nominal resistance, capacitance and inductance of the couple wires (see Eq.(14)); Step Compute C nui1 and C nui, and then we can get V +,V,I + and I finally the voltage and current (V A,I A,V Q and I Q) at any point along these lines can be gotten by the numerical inversion of Laplace transform (see Eqs.(1), (13) and ()); Step 3 To speed up the computation, the relation functions f r,f cg,f cm,f ls and f lm are linear functions or quadratic functions, which can be obtained by least squares method;

4 6 Chinese Journal of Electronics 015 Step 4 Resistance, capacitance and inductance distribution as Gaussian distribution (see Eq.(16)); Step 5 Repeat Step, we can get the voltage and current distribution at any point along these lines (see Eqs.(15) and (16)). IV. Experimental Results In this section, the model proposed in this paper is verified by comparing with HSPICE. The verification is conducted in two sections: the coupled crosstalk noise model with and without the effect of process variations. The study data are derived from ITRS007 (See Table 1). And the coupled-line configuration is shown in Fig.1. For further verify the precision of the model prosed in Section II, the voltages of far end, near end and middle on the couple lines are chosen to compare with HSPICE. The results are shown in Fig.4. We can observe that the obtained data of proposed model good agreement with the simulation results of HSPICE, and the errors of critical data are within 1%.. Statistical crosstalk noise model verification In this section, we verify statistical crosstalk noise model proposed in Section III. According practice, we used the Gaussian assumption to verify the proposed model when the variations in physical dimensions are large. We consider a threesigma tolerance of 10% in W, T, H, S. Fig.4 compares the voltage waveforms distribution at far end using statistical crosstalk noise model with HSPICE Monte Carlo simulations. And the detailed quantitative comparison is listed in Table. The results show that the relative errors occurred between calculated values and HSPICE simulation values are less than 5%. V. Conclusion In this paper, we proposed coupled RLC crosstalk noise Table 1. Interconnect technology parameters [1] Technology node 45 Minimum global wiring pitch (nm) 135 Conductor effective resistivity (µω-cm) 3.10 Effective dielectric constant Coupled crosstalk noise model verification In this section, we verify the couple crosstalk noise model proposed in Section II. A couple of global wires are taken as analysis object for representativeness. Each line is 4mm long. Linewidth of both wires is 1.05µm. Both metal thickness and Inter-layer dielectric thickness are 0.55µm. And the spacing between them is 0.55µm. The output resistance is 133.3Ω, and the input capacitance is 00fF. We can get the waveforms of voltage and current at any point along these lines by the model prosed in Section II. As the distributed parameter model replaces lumped parameter model, the model has wider scope of application. And these observations are summarized in Fig.3. Fig. 4. Waveforms use HSPICE and the analytical model Fig. 3. The waveforms on aggressor line and victim line Table. Compare with HSPICE Monte Carlo simulations Peak Trough Time Voltage Time Voltage (ps) (mv) (ps) (mv) Hspice Mean Model Error (%) Hspice Max Model Error (%) Hspice Min Model Error (%) model with capacitive load termination. The proposed model is based on coupled-transmission-line theory and the impact of inductance on crosstalk noise is considered. And the proposed

5 Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations 7 model is distributed parameter model, which can get the waveform of voltage and current at any point along the couple lines. In particular, we develop the framework that how to use the crosstalk noise model for process variations. Our results show that compare with HSPICE, the critical data errors of proposed model are within 1% and the relative errors occurred between calculated values for process variations and HSPICE Monte Carlo simulation values are less than 5%. To improve the speed of computation, the numerical inversion of Laplace transform is introduced. So the proposed model achieves the needs both speed and accuracy for future IC design. References [1] International technology roadmap for semiconductors (ITRS)., Interconnect, /011Chapters/011Interconnect.pdf, 01. [] A. Atghiaee and N. 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LI Jianwei received the B.S., M.S. and Ph.D. degrees in microelectronics and solid state electronics from Xidian University, Xi an, China, in 001, 007 and 010, respectively. From 001 to 004, he worked at Xi an SWIP Co., Ltd., where he performed digital IC design of digital signal processor, master control unit and communication interface. Since 011, he has worked at Xi an University of Technology, His research interest is modeling of interconnect lines with process variations. ( lijw@xaut.edu.cn) DONG Gang received the B.S., M.S., and Ph.D. degrees in microelectronics and solid state electronics from Xidian University, Xi an, China, in 000, 003, and 004, respectively. Since 005, he has been with the School of Microelectronic, where he is currently an associate professor. From 00 to 009, he was with the Department of Electrical Engineering and Computer Science, Northwestern University, as a visiting scholar. His research interests include system integration technology and ICCAD. WANG Zeng received the B.S. and M.S. degrees in microelectronics and solid state electronics from Xidian University, Xi an, China, in 001 and 007, respectively. From 001 to 004, he worked at ASIC Lab of Hisense Research and Development Center, Shanghai, where he performed digital circuit design of the digital video signal processor. Since 007, he has been with the School of Microelectronic as a doctoral candidate. Since 011, he has worked at Qingdao University. His research interest is modeling of interconnect lines with temperature distribution. YE Xiaochun received the Ph.D. degree in computer science from the Institute of Computing Technology, Chinese Academy of Sciences. He is an assistant professor in the State Key Laboratory of Computer Architecture of China at ICT. His research interests include high performance processor design and parallel computing.