Luis Manuel Santana Gallego 100 Investigation and simulation of the clock skew in modern integrated circuits. Clock Skew Model

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1 Luis Manuel Santana Gallego 100 Appendix 3 Clock Skew Model Xiaohong Jiang and Susumu Horiguchi [JIA-01] 1. Introduction The evolution of VLSI chips toward larger die sizes and faster clock speeds makes clock distriution an increasingly important issue. Clock skew modelling is important in the performance evaluation and prediction of clock distriution networks, ecause at high speeds clock skew ecomes a very significant prolem. Clock skew may arise mainly from unequal clock path lengths to various modules and process variations that cause clock path delay variations. There are worst-case and statistical skew models not suitale for modelling the clock skews of general clock distriution networks in which clock paths are not identical. The worst-case approach (Kung and Fisher model) can usually cause an unnecessarily long clock period. The statistical models handle the prolem from the po of view that all clock paths are assumed to e identical and independent. Kugelmass and Steiglitz model predicts an upper ound of expected clock skew. Zarkesh-Ha, Mule and Meindl model is too conservative for estimating the clock skew of a well-alanced clock network that has identical ut strongly correlated clock paths (for example, a well-alanced H-tree). In order to provide a more accurate and more general statistical skew model for general clock (in which clock paths can e not identical), these authors propose a new approach to estimate the mean value and variance of clock skew of general clock distriution networks. Based on the new approach, a closed-form model is also otained for well-alanced H-tree clock distriution networks. The paths delay correlation caused

2 Luis Manuel Santana Gallego 101 y the overlapped parts of path lengths is considered in the new approach, so the mean value and the variance of clock is accurately estimated for general clock distriution networks.. Clock skew modelling For a given CDN (clock distriution network), let t(l o, l i ) denote the signal propagation time on the unique path from the clock source l o to the sink l i. The maximal clock delay ξ and the minimal clock delay η of the CDN can e defined as: { t ( l0, l i )} ξ= max (1) i { t ( l0, l i )} η= min () i The clock skew etween two sinks l i and l j is the delay difference t(l 0, l i ) - t(l 0, l j ) and clock skew χ of the CDN is in general defined as the maximum value of t(l 0, l i ) - t(l 0, l j ) over all sink pairs l i and l j and in the CDN. Thus, χ is given y ( 0 i ) t ( l0 l j ) χ = max t l, l, = ξ η (3) i j Process variations are suject to two sets of factors: systematic factors, like power supply fluctuations, which can e controlled y proper techniques and factors that are random, and therefore uncontrollale y improved techniques. Therefore, the random factors determine the achievale performance of a circuit. We want to model the clock skew of general CDNs when the random factors are considered. When random process variations are considered, variations of paths delay are modelled y normal distriutions. To model the clock skew χ, random variales ξ and η should e first characterized. The model is ased on the following two assumptions: Assumption 1: A CDN can in general e represented y a inary tree. We assume that oth the maximal clock delay and the minimal clock delay in each sutree (and

3 Luis Manuel Santana Gallego 10 also the whole inary tree) of the CDN can e modelled y normal distriutions when process variations are considered. The assumption makes it easy to analyze the correlation that exists etween the maximal and the minimal delay in a sutree. This correlation analysis is critical in determining the variance of skew in each sutree (and also the whole inary tree) of the CDN. Assumption : The delay along a clock path is the sum of the uncertain independent delays of the ranches along the given path. Correlation etween the delay of any two paths is determined only y the overlapped parts of their length. The clock paths of a CDN usually have some common ranches over their length, and these common ranches cause correlation among the delays of these paths. The aove assumption enales a complete analysis of this kind of correlation. In addition to the delay correlation descried in Assumption, the correlation among paths delay may also e caused y the correlated ra-die variations of these parameters involved in that delay (e.g., threshold voltages, resistances, etc.). However, finding the correlation coefficient of these parameters is, in practice, quite uncomfortale and difficult. So authors neglect these kinds of correlation in as indicated in Assumption. In general, the ra-die process parameters correlation will lead to the paths delay in the same chip tending to e positive dependent. In this case, Assumption will guarantee that the expected value of clock skew will still e upper ounded y the corresponding values estimated using our approach. Compared to the old upper ound of expected skew of a well-alanced CDN where all the clock paths are assumed completely independent, our estimates are enhanced significantly, ecause the paths delay correlation caused y the common ranches of paths length are completely considered. Furthermore, the new approach is applicale to general CDNs, whereas the old models is only applicale to the well-alanced CDNs in which clock paths are identical. From (3), the mean value and the variance of χ are given y:

4 Luis Manuel Santana Gallego 103 E( χ) = E( ξ ) E( η) (4) D( χ) = D( ξ ) + D( η) ρ D( ξ ) D( η) (5) Here, E( ) and D( ) represent the mean value and the variance of a random variale, respectively, and ρ is the correlation coefficient of ξ and η. The parameters E(ξ), E(η), D(ξ), E(η) and ρ should e accurately estimated for a CDN to allow the accurate modelling of clock skew. 3. Parameter estimation A recursive approach for evaluating the parameters E(ξ), E(η), D(ξ), D(η) and ρ of general CDNs is presented here. Based on this algorithm, closed-form expressions of clock skews and the maximal clock delay of well-alanced H-tree CDNs are also developed Algorithm for general CDNs A CDN can generally e represented y a inary tree, so a simplified inary tree shown in Figure 1 is taken as an example to illustrate the evaluating process of these parameters. The evaluating process is then applied to general CDNs. All the paths in Figure 1 are partitioned o independent ranches s 0, s 1, s, y the ranch split pos in the clock tree, where d i is the actual delay of s i. The ranch split po (i, j) in the clock tree is associated with a set of random variales (ξ ij, η ij, χ ij ), here ξ ij, η ij and χ ij are the maximal clock delay, the minimal clock delay and the clock skew of the sutree starting from the split po, respectively. Each random variale here is characterized y oth its mean value and its variance.

5 Luis Manuel Santana Gallego 104 Figure 1: Binary clock tree. To illustrate that the parameters E(ξ), E(η), D(ξ), D(η) and ρ of the simplified inary clock tree can e evaluated recursively, we egin with the evaluating process of (ξ 00,η 00,χ 00 ). Let ranch s i also e associated with a set of random variales, (ξ i, η i, ρ i ), with ξ i eing the maximal clock delay and η i eing the minimal clock delay of the sutree starting from ranch s i, and eing ρ i the correlation coefficient of ξ i and η i. Thus ξ = ξ + d, ξ = ξ + d η = η + d, η = η + d ρ ρ 1 ( ξ1 ) + ( η1 ) ( χ11) D( ξ1 ) D( η1 ) ( ξ ) + ( η ) ( χ1 ) D ( ξ ) D( η ) D D D = D D D = (6) (7) Then we have: ξ η ξ + ξ + ξ ξ = max { ξ, ξ } = η + η η η = min { η, η } = (8) χ00 = ξ00 η00 (9)

6 Luis Manuel Santana Gallego 105 Equations (6) (9) indicate that the results of ranch split po (0, 0) are determined y and can e evaluated from oth the corresponding results [(ξ 11, η 11, χ 11 ) and (ξ 1, η 1, χ 1 )] of the next lower level split pos (1, 1), (1, ), and the delay of the ranches [s 1 and s ] connecting the po to those next lower level split pos. So once the results of (ξ ij, η ij, χ ij ) are otained for each lowest-level split po (i.e., the split po from which no further ranch split pos can e found in the sutree starting from that split po pos (n, 1), (n, ), ), the process aove can e used recursively to evaluate the mean values and the variances of clock skew, the maximal clock delay and the minimal clock delay of a general CDN in a ottom-up manner. In fact, the results of (ξ n1, η n1, χ n1 ) of one lowest-level split po in Figure 1 can e otained as follows: The mean values and the variances of ξ n1 and η n1 can e evaluated y using their distriution functions, respectively. The mean value and the variance of χ n1 are given y: ( χn 1) = ( ξn 1 ηn 1) = ( sink1 sin k ) E E E d d Esin k Dsin k D sin 1 k E E sin k sin k 1 = exp + exp t dt π D sink π 0 (10) ( χ ) = ( ) = + ( χ ) D n1 D dsink1 dsin k Esin k Dsin k E n1 (11) where ( ) ( ) ( ) ( ) E = E d E d sin k sin k1 sin k D = D d + D d sin k sink1 sin k (1) Based on the results of (ξ 00,η 00,χ 00 ), the parameters, E(ξ), E(η), D(ξ), D(η) and ρ of the whole inary tree are then given y: ( ξ ) = ( ξ00 ) + ( 0 ), ( η ) = ( η00 ) + ( 0 ) ( ξ ) = ( ξ ) + ( ), ( η ) = ( η ) + ( ) E E E d E E E d D D D d D D D d ( ξ ) + ( η ) ( χ00 ) D( ξ ) D ( η ) D D D ρ = (13) (14)

7 Luis Manuel Santana Gallego 106 The pseudocode for the parameter estimation algorithm is the following: - Parameter estimation for general CDNs { Initialization: for each L p V do { ξ d 1 η d ρ } Algorithm: while (V not empty) do { for each L p V do { ξ η ( ) = ( ξ1 < ) ( ξ < ) ( ) = 1 ( η1 > ) ( η > ) p x p x p x p x p x p x ( ) ( ξ ) = ( ) ξ E x d p x ( ) ( ξ ) = ( ) ξ ( ) ξ D x E d p x ( ) ( η ) = ( ) η E x d p x ( ) ( η ) = ( ) η ( ) η D x E d p x Cov ξ + ξ + ξ ξ η + η η η, = Cov, ( ξ η ) ( χ ) = ( ξ ) ( η ) ( χ ) = ( ξ ) + ( η ) ( ξ, η ) E E E D D D Cov Remove G = (V, E ) from G = (v, E)

8 Luis Manuel Santana Gallego 107 } } } ξ η ξ + d η + d ( ξ ) ( ξ ) + ( ) ( η ) ( η ) + ( ) ( ξ ) ( ξ ) + ( ) ( η ) ( η ) + ( ) D ( ξ ) + D( η ) D( χ ) D( ξ ) D( η ) E E E d E E E d D D D d D D D d ρ In the pseudocode, a CDN is represented y graph G = (V, E) with vertex (split po) set V and edge (ranch) set E. The lowest level split po L P of the graph is associated with random variales (ξ,η,χ ), as defined aove. (ξ,η,χ ), are the random variales associated with the ranches starting from a lowest level splitting po, with (ξ 1,η 1,χ 1 ) and (ξ,η,χ ) representing the random variales associated with the two ranches starting from L P, respectively. For a CDN, the initial values of ξ and η are just the actual delay d of the ranches that support sinks. d Lp is the actual delay of the ranch L P connecting to its parent splitting po, and G Lp = (V, E ) is the sugraph starting from L P. Since the algorithm carries out the same amount of computation for each split po, the following conclusion can e otained: Theorem 1: The parameter estimation algorithm given aove computes a network G=(V, E) in O( V ) time. The theorem indicates that the parameter estimation algorithm is computationally effective in estimating the parameters, E(ξ), E(η), D(ξ), D(η) and ρ of a general CDN.

9 Luis Manuel Santana Gallego Clock skew estimation for H-tree CDNs The H-tree technique is widely used to reduce the clock skew. Due to the very symmetric structure of H-tree CDNs, it is possile for us to get a closed form model for clock skew and the maximal clock delay of H-tree CDNs. Before developing the models, the H-tree itself must first e defined. Without loss of generality, a well-alanced H-tree has n hierarchical levels, where n denotes the tree depth. The level 0 ranch corresponds to the root ranch, and level n ranches to the ranches that support sinks. A level i ranch egins with a level split i po and ends with level i+1 split po. The H-tree illustrated in Figure is drawn for n=6, which is used to distriute the clock signals to 64 processors. Figure : A well-alanced H-tree clock distriution network for 64 processors For a n level well-alanced H-tree, let d i, i=0,, n e the actual delay of ranch i of a clock path. The mean values and the variances of the maximal clock delay ξ and the minimal clock delay, η, of the H-tree are then given y following equations: n n i k π E E di D d i= 0 π i= 1 k = 1 π (15) n i+ k ( ξ ) = ( ) + ( )

10 Luis Manuel Santana Gallego 109 n n i k π E E di D d i= 0 π i= 1 k= 1 π (16) n i+ k ( η ) = ( ) ( ) n π 1 i i i= 0 π (17) ( ξ ) = ( η ) = ( ) D D D d Results (15) (17) and (3) indicate that the expected clock skew E(χ) and skew variance D(χ) of the n level well-alanced H-tree are given y: n i π 1 ( ) ( ) ( ) k E χ = E ξ E η = D ( dn i+ k ) π i= 1 k = 1 π (18) ( χ ) ( ξ ) ( η ) ρ ( ξ ) ( η ) D = D + D D D = n π 1 = 1 i= 0 π ( ρ ) D( d ) i i 1 (19) where ρ is the correlation coefficient of ξ and η, and ρ can e recursively evaluated for a network as discussed in Section 3.1. The closed-form expressions (15) (19) indicate clearly how the clock skew is accumulated along the clock paths and with the increase of H-tree size. This enales a suitale H-tree size to e selected for a specified clock frequency, and also enales minimization of the clock period, improving the speed for a fixed size H-tree network Yield of clock skew model The clock period of a CDN is in general determined y the clock skew of the network. With the estimates of mean values and variances χ in hand, it is possile for us to estimate its yield. Here, the yield of a random variale means the proaility that the variale is less than a specified value. For general CDNs, ξ and η are positively correlated (i.e., ρ>0) normal variales, and clock skew χ can e modelled y log-normal distriution as verified y availale extensive simulation results. The clock skew yield, i.e., the proaility that the actual skew of the network, χ, is less than a skew specification x (P(χ<x)), can then e evaluated as:

11 Luis Manuel Santana Gallego 110 < = exp (0) 0 π δ1 t δ 1 x log e 1 logt µ 1 P x dt ( χ ) where parameters µ 1 and δ 1 are given y: µ 1 = log D E ( χ ) ( χ ) E ( χ ) + (1) δ ( χ ) ( χ ) E ( χ ) log e log D + E = 1 () Once the algorithm developed in Section 3 estimates the mean value of χ of a CDN, the yield of χ can e approximated y a lognormal distriution. 4. Clock skew calculation in function of its components 4.1. Calculation The delay of a ranch may then e otained y averaging the rise and fall times. Using Sakurai s model for erconnection delays (90 % of time delay), the delay of a stage composed of a wire erconnecting two uffers (inverters) is: ( ) T =1.0R C +.30 R C + R C + R C (3) Delay Here R 0 is the output resistance of the driving transistor of minimum size inverter, C 0 is the input capacitance of the driven minimum size inverter, C and R are the capacitance and resistance of the erconnection line in the ranch. Their expressions are given y:

12 Luis Manuel Santana Gallego µ Cox W ε R0 =, K =, Cox = K V V L t 0 ox ( ) C = C W L R C = ε ILD TILD DD T eff ox eff ρ = L W t W L ox (4) where: W and L eff : width and effective length of the transistor. C ox : gate unit area capacitance. t ox : gate oxide thickness. µ: charge carrier moility. V T : threshold voltage. ρ: metal resistivity. ε ox : oxide dielectric constant. ε ILD : erlevel dielectric constant. W, L and t : width, length and thickness of the erconnection line. T ILD : Interlevel dielectric thickness. In the C expression, we don t take o account the contriution of fringing fields. The process parameters and their standard deviations used here are ased on the 0.5 µm CMOS technology predicted y the International Technology Roadmap for Semiconductors (ITRS) and the MOSIS parametric test results of a typical 0.5 µm technology. The mean values and ra-die standard deviations (SD) of these process parameters are presented in Tale 1. Parameters Mean SD L eff (µm) V DD (V).5 0 V TN (V) V TP (V)

13 Luis Manuel Santana Gallego 11 t ox (Aº) µ n (cm /V s) µ p (cm /V s) 1.44 t (µm) T ILD (µm) Tale 1: 0.5 µm Process parameters (mean and standard deviation). Here, V DD is not considered as a random variale since the power supply in a system is gloally controlled. Furthermore, the standard deviation of the width of a transistor is 0.0 µm for n-mos and 0.05 µm for p-mos as estimated from MOSIS. The n-mos transistor and p-mos transistor in the minimum inverter of the technology are assumed to have the gate width/length of 0.37 µm /0.5 µm and 1.1 µm /0.5 µm, respectively. As indicated in Assumption, the ra-die parameters correlations are neglected in this model. Thus, R 0 in (4) will e independent from C 0. One approach to calculating the delay variance of a ranch due to the variations of process parameters is to first express the relations (4) in terms of independent variales. The delay variance of the ranch can then e determined in terms of variances of these independent random variales. For example, the variance, σ z, of a random variale z that is a function of independent random variales, z=f(x,y, ), may e otained from: f f z x y σ =... x σ + y σ + (5) We are going to consider the following variales to calculate the variance of T delay : V T, µ, t ox, L eff, W, T ILD, W, t. Therefore, the variance of the delay in a ranch is the following: T T T T T σ = σ + σ + σ + σ + σ Delay Delay Delay Delay Delay TDelay VT µ t ox Leff W VT µ t ox L eff W T T T + σ + σ + σ T W t Delay Delay Delay T ILD W t ILD (6)

14 Luis Manuel Santana Gallego 113 where: T T R R = =.30( C + C ) Delay Delay VT R0 VT VDD VT TDelay TDelay R R = =.30( C + C ) V R µ µ T T T R T C R C = + =.30( C + C ) +.30( R + R ) Delay Delay 0 Delay tox R0 tox C0 tox tox tox TDelay TDelay R = L R L eff 0 0 eff TDelay C R C + =.30( C + C ) +.30( R + R ) C L L L eff eff eff T T R T C R C = + =.30( C + C ) +.30( R + R ) Delay Delay 0 Delay W R0 W C0 W W W (7) T T C C ( 1.0R.30R ) T C T T Delay Delay = = + 0 ILD ILD ILD T T R T C R C ( 1.0C.30C ) ( 1.0R.30R ) W R W C W W W Delay Delay Delay = + = TDelay TDelay R = t R t R ( ) = + C C0 t Also we have to consider that every ranch has a different length. It doules it length each two levels. Once the mean delay value and the delay variance of each ranch are evaluated for a network, the theoretical approach developed can e used to estimate the mean value, the variance and the yield of the clock skew of the network. 4.. Verification To verify the new approach, transistor level Monte Carlo simulations are also conducted. In the simulation, each asic parameter in (4) is simulated y a normal random variale. To agree with the conditions used in the theoretical approach, the correlation etween K and V T, etween µ and C ox is neglected as discussed aove. The actual delay of a ranch is then evaluated from the random values of these asic parameters using (4). The actual delay of a path is the sum of the actual delays of the

15 Luis Manuel Santana Gallego 114 ranches along that path. The actual maximal clock delay, minimal clock delay and clock skew of the network are then determined y (1) (3). For a specified value, the yield of a parameter (clock skew) is estimated y the ratio of numer of simulations in which the parameter is less than the specified value to the total numer of simulations. The first network considered is well known as the H-tree approach shown in Fig. (for revity, inverters are not illustrated in the following networks). Due to the very symmetrical design of H-tree clock networks, all clock paths within the H-tree are identical, and the old statistical model can e used to get an upper ound of its expected clock skew when all the paths are assumed to e independent. According to the old model, an upper ound of expected clock skew of a well-alanced H-tree is asymptotically given y: upper 4ln N ln ln N ln 4π C 1 E ( χ ) σ + = + O ( ln N ) 1/ log N (8) with the variance of clock skew eing given y: upper D ( χ ) π σ 6ln N 1 log N = + O (9) where: σ: standard deviation of path delay. C 0.577: Euler s constant. N: numer of paths (numer of processing elements). O( ): higher order term. In a n-level H-tree, there are a total of n+1-1 ranches, and it can e used to distriute clock signals to n elements. For two cominations of parameters h and W, in a wide range, and when the numers of processors are 4, 8, 16, 3, and 64, the theoretical results (otained using oth the old and new models) and simulation results of clock skews of corresponding H-trees are summarized in Figure 3.

16 Luis Manuel Santana Gallego 115 Figure 3: Simulation results and theoretical results of clock skew of H-tree networks when different numers of processors are considered. (a) Mean value of clock skew. () Standard deviation of clock skew. The results in Figure 3 show that the new model is accurate in estimating the mean values and standard deviations of the clock skew of H-tree CDNs, where the delay correlation determined y the overlapped parts of path lengths has een considered as indicated in Assumption. Compared to the old estimates of expected clock skew where all the paths in the H-tree are assumed completely independent, the new estimates ased on Assumption are a significant enhancement. For different sized H-trees, the expected clock skews estimated using the old model (6) are at least.6 times the expected clock skews estimated using our approach. This is shown in Fig. 3(a). In cases where clock frequency is limited y skew rather than y the minimum time etween two successive events propagated through the H-tree, an unnecessarily long clock period will result from using the old skew model.

17 Luis Manuel Santana Gallego 116 Based on the aove estimated results of the mean values and the variances of χ, the yields of χ and can e further estimated as discussed in Section4. For the six-level H- tree shown in Figure, the theoretical yield results and the simulation yield results of χ is summarized in Figure 4. For comparison, we also present in Figure 3 the simulation results of yield of clock skew when all paths are assumed independent. Figure 4: Simulation yield results and theoretical yield results of clock skew of an H-tree network for two cominations of parameters h and W. The results in Figure 4 indicates that the old model s independent assumption leads to very conservative estimates of clock skew yields of H-tree CDNs that have identical ut strongly correlated clock paths. The results in Figure 5 also show that when the mean values and the variances of χ of the H-tree CDNs are accurately estimated y our approach, the yields of their χ is further approximated y log-normal distriution. Due to the assumption that all clock paths are identical, the old statistical skew model could not e used to model the clock skews of general clock networks with nonidentical paths. The new model developed, however, can e used to accurately estimate the mean values and the variances of clock skew of these general CDNs. For a wellalanced CDN (e.g., H-tree clock network), the expected clock skews estimated y old model are very conservative ecause correlation among paths delay are completely neglected. On the other hand, the expected clock skews estimated y the new model are enhanced significantly. For the well-alanced H-tree network shown in Figure, the results in Figure 3 show that when parameters h=100 and W =3 µm, the expected clock skew estimated y old model is aout 89.5 ps, a value 5.8 times larger than the actual value. For a traditional clocking mode and when the 10% rule of thum relating the

18 Luis Manuel Santana Gallego 117 skew to the clock period is used, the actual clock period should e dominated y the maximal clock delay, and the mean value of clock period will e 6.96 ns. However, when the old skew model is used in the skew estimate, the clock period should e determined y the clock skew rather than the maximal clock delay, and the mean value of clock period will e 8.95 ns. The old model will thus mislead efforts to reduce the clock period of the network. For a pipelined clocking mode, the clock periods of wellalanced H-tree networks will e dominated y the clock skew rather than y the minimum time etween two successive events propagated through the H-tree, an unnecessarily long clock period will result from using the old skew model. 5. Conclusions The old model (upper ound model) is too conservative in estimating the expected skew of a well-alanced CDN. Also, in not general enough to model the clock skew of a non-alanced CDN. A closed form model (statistical) of clock skew is presented for well-alanced H-tree CDNs. The path delay correlation determined y the overlapped parts of path lengths is completely considered in this approach. Therefore, the mean value and variance of clock skew is accurately estimated for general CDNs. Considering process variations in designing a clock distriution network, mean values and variances of delays for all ranches should carefully e estimated, then the approach presented here will e useful in evaluating and predicting the network s performance of clock skew. Two main assumptions: - Assumption 1: A CDN can generally e represented y a inary tree. We assume that oth the maximal clock delay and the minimal clock delay in

19 Luis Manuel Santana Gallego 118 each sutree (and also the whole inary tree) of the CDN can e modelled y normal distriutions when process variations are considered. The assumption makes it easy to analyze the correlation that exists etween the maximal and the minimal delay in a sutree. This correlation analysis is critical in determining the variance of skew in each sutree (and also the whole inary tree) of the CDN. - Assumption : The delay along a clock path is the sum of the uncertain independent delays of the ranches along the given path. Correlation etween the delays of any two paths is determined only y the overlapped parts of their length. To apply the model in a H-tree CDN, it s necessary to know: - Interconnection resistance: R - Interconnection capacitance: C - On-resistance of the driving transistor: R 0 - Input capacitance of the driving inverter: C 0 - Power supply voltage: V DD - Threshold voltage: V T - Threshold voltage deviation (in %): σ VT - Charge carrier moility deviation (in %): σ µ - Gate oxide thickness deviation (in %): σ tox - Transistor width deviation (in %): σ W - Effective channel length deviation (in %): σ Leff - Wire width deviation (in %): σ w - Wire thickness deviation (in %): σ t - ILD thickness deviation (in %): σ TILD - Lowest level ranch length: L - H-tree levels: n

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