Driver 1. Load 1 AGGRESSOR LINE. V s1. C c Load 2. Driver 2 VICTIM LINE. V s2. Circuit Figure

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1 Noise and Delay Estimation for oupled R Interconnects Andrew Kahng Sudhakar Muddu and Devendra idhani Silicon Graphics Inc. Mountain iew A 9439 ULA omputer Science Department Los Angeles A 995 abk@cs.ucla.edu muddu@mti.sgi.com vidhani@cs.ucla.edu Abstract The performance of high-speed LSI circuits is increasingly limited by interconnect coupling noise. We provide improved easily computable estimates of crosstalk peak noise as well as impact of coupling on aggressor delay for distributed R interconnects. Our approach is based on better modeling of the distributed interconnects as well as more detailed analyses for both the step input and ramp input regimes. We analyze both L and interconnect models in deriving analytic expressions for peak noise and delay. We also handle both step and ramp inputs so that our approach is strictly more general and accurate than previous methods in the literature notably [8] [5]. Noise estimates obtained with the model are within 3% of SPIE simulation results and in practice the L model provides an upper bound and the model provides a lower bound on the peak noise estimation as compared to SPIE simulation results. The substantial accuracy improvements that we obtain can lead to less over-design and guard-banding in high-performance system designs. Introduction Interconnects are an important performance limiting factor in today's high-speed and high-density LSI designs. A major reason for this is the increasing importance of crosstalk between parallel R interconnect lines [] [6]. This crosstalk is due to the capacitive coupling between lines (which increases as the average length of interconnects and the density of interconnect routings increase) and to the faster switching speeds of devices. Today's timing analysis tools employ a simple technique which takes the coupling capacitance to be some multiple of grounded capacitance depending upon the switching conditions. A single eective capacitance value for the interconnect is computed for use in delay and noise estimation. This is multiplied by a switching factor which is taken to be slightly more than zero for a pair of lines switching in the same direction and slightly less than two for a pair of lines switching in the opposite direction. The downside of this simple technique is that it can lead to highly optimistic or pessimistic analyses of noise. This motivates the development of more accurate predictors of noise and coupling-induced delay based on coupling capacitance values and switching activity (slew times osets).

2 Several notable previous works model the eects of interconnect fringing and coupling capacitance on delay and crosstalk. ittal et al. [8] useanl model for R interconnects and obtain delay and noise bounds for the case of a step input only. Also their model does not take into account the interconnect resistance while deriving noise expressions. Kawaguchi and Sakurai [5] use the diusion equations for analyzing capacitively coupled interconnects but also analyze only the case of a step input. In addition they make several assumptions while deriving the nal expressions for the noise and delay. E.g. they assume R driver << R int and load << int. The results of [5] are a special case of results of [8] and the equations from [5] reduce to those of [8] when the driver resistance is made zero. Also they evaluate dierent cases of possibilities of ratios of resistances capacitances etc. separately and make few assumptions in each derivation. Shepard et al. [7] obtain noise estimates that are dependent on input slew but the interconnect model is again a simple L model. Yee et al. [9] present simulation results that document the magnitude of crosstalk-induced delay. Devgan [] presents a metric for fast estimation of noise based on electrical properties of circuits but the estimation error increases as the rise time decreases. In this paper we present improved estimators for noise and delay phenomena due to coupling capacitance. We use a distributed model for R interconnects which is more accurate than the L model used in [7] [8]. We also derive expressions for ramp inputs in addition to step inputs. Our approach analyzes circuits in the frequency domain and then obtains time domain results by taking the inverse Laplace transform. Forastep input waveform and an L model of the interconnect our expressions reduce to those derived in [8]. Thus in light of the previous literature we are the rst to provide a complete set of analytic estimators for both L and models of the interconnect for both step and ramp inputs and for both peak noise and coupling delay estimation. The improved accuracy of our estimators can (i) be useful in analyzing the sensitivity of circuit performance to various interconnect tuning parameters and (ii) lead to less overdesign and guard-banding in high-performance designs at all stages of a performanceconvergent synthesis and layout methodology. The remainder of this paper is organized as follows. Section describes the circuit model and the notation used in our analysis. Section 3 presents the analysis of noise and delay due to coupling for the L model of interconnect. Section 4 presents the analysis of noise and delay due to coupling for the model of interconnect. Simulation results are presented in Section 5 and Section 6 concludes with directions for future work. Preliminaries and Notation We consider two parallel coupled interconnects with drivers and loads attached as shown in Figure. Equivalent circuits using L and models for the interconnects are shown in Figures and 4 respectively. We analyze noise and delay atnodes and B. Although for simplicity we consider just one aggressor line our analyses extend easily to the case of more than one aggressor line for a given victim line. Our goal is to develop models to estimate peak noise on the victim line and delay on both aggressor and victim lines for three main cases: (i) victim line quiet (ii) victim line active andswitching in the

3 Driver AGGRESSOR LINE Load A B s Driver D c Load ITIM LINE s ircuit Figure Figure : Two parallel coupled interconnects with inverters as drivers and loads. This conguration is used for our analysis of peak noise on the victim and delay on both aggressor and victim. Model State of Line Switching Input Section Type ictim Aggressor Directions on Lines Waveform in Paper Quiet Active - step 3.. Quiet Active ramp 3.. L Active Active opposite step 3.. Active Active opposite ramp 3.. Active Active same step 3.3. Active Active same ramp 3.3. Quiet Active - step 4.. Quiet Active ramp 4.. Active Active opposite step 4.. Active Active opposite ramp 4.. Active Active same step 4.3. Active Active same ramp 4.3. Table : Detailed outline of cases addressed in Sections 3 and 4. opposite direction to the aggressor and (iii) victim line active and switching in the same direction as the aggressor. These cases are addressed in Sections 3 and 4 as outlined in Table. The following notation is used in our discussion (see Figures and 4). aggressor line: interconnect whose switching aects the voltage level on another interconnect parallel to it victim line: interconnect parallel to the aggressor line and whose voltage is aected by the switching of the aggressor line v B (t): voltage at node B in time domain B (s): voltage at node B in transform domain v : supply voltage v peak : peak noise voltage R d : driver on-resistance of aggressor line R d : driver on-resistance of victim line R : resistance of aggressor line R: resistance of victim line : metal to ground capacitance of aggressor line in L model (includes load capacitance) or rst of the two capacitances of the aggressor line in the distributed model 3

4 : metal to ground capacitance of victim line in L model (includes load capacitance) or rst of the two capacitances of the victim line in the distributed model : second of the two metal to ground capacitances in the model of the aggressor line (also includes load capacitance) : second of the two metal to ground capacitances in the model of the victim line (also includes load capacitance) c : coupling capacitance between the lines when the L modelofinterconnect is used or rst capacitance of the distributed model of interconnect c : second capacitance of the distributed model of interconnect t peak : time at which the peak noise voltage is reached TS I : slew time at the input of driver T O S or T S: slew time at the output of driver 3 Noise and Delay Estimation Using the L Model for Interconnect AGGRESSOR LINE R d R B s L c R d R s ITIM LINE L L model for lines Figure : Equivalent circuit (using L model for interconnect) for the conguration of Figure. In this section we use the L model to represent the R interconnect between the driver and the load as shown in Figure. To estimate the noise peak on the victim line due to the aggressor line the rst subsection studies the case when the victim line is quiet and the aggressor line is switching. The second subsection studies the case when both the victim and aggressor lines are switching in opposite directions; this case is used to estimate the worst-case interconnect delays on both the lines. Finally the third subsection studies the case when both the victim and aggressor lines are switching in Note that the notation T S is used exclusively to represent the output slew time of the driver. 4

5 the same direction; this case is used to estimate the best-case interconnect delays on both the lines. Our analyses address both the step and ramp input regimes and we take driver resistance and load capacitance into account when deriving expressions for peak noise and delay. Our noise peak expression for step input reduces to the result obtained in [8] when interconnect resistance is set to zero. 3. ictim Quiet and Aggressor Switching Since noise can cause false switching and incorrect functionality it is essential to predict and correct for noise peaks. We now obtain an analytical expression for peak noise. In practice this noise peak estimated via the L model can be taken as an upper bound when compared with SPIE simulation results. To calculate the noise on the victim line we assume that the victim line is quiet and the aggressor line is switching as shown in Figure 3. In the circuit model of Figure we compute the voltage at the aggressor line output i.e. at node. Using the nodal equations at B and we obtain the following expression for voltage on aggressor and victim line in the frequency domain: where +a s B = S () +sm + s M a s = S () +sm + s M M = [(R d + R )( + c )+(R d + R)( + c )] M = (R d + R )(R d + R)( c + c + ) a = (R d + R)( (3) + c ) a = (R d + R) c We now compute the noise peak on victim line by considering step and ramp inputs at the inputs of the of aggressor line. 3.. Step Input Analysis onsider an aggressor line switching from low to high and a quiet victim line (i.e. input voltage remains constant) as shown in Figure 3(a). For the quiet line the input voltage s = and for the aggressor line with step input we have S = v s. The voltage at node B and in time-domain is given by v B (t) =v +k e st + k e st (4) a v (t) =v e s t e s t (5) M (s s ) where k = +a s s M (s s ) k = +a p s s s M (s s ; = M=M (M =M ) 4=M. The peak noise is computed by dierentiating Equation (5) with respect to t and equating to zero. The time at which peakvoltage is reached is given by t peak = (s s ) ln(s =s ) (6) Note that the capacitances and includes the load capacitances at the end of the line (i.e. L or L). 5

6 s A AGGRESSOR LINE B s c D ITIM LINE (a) Step Input s T R A AGGRESSOR LINE B s D c ITIM LINE (b) Ramp Input Figure 3: ase when the victim line is quiet: (a) step input and (b) ramp input. and the peak voltage is v peak = a v M (s s ) s s s (s s ) s s s (s s ) (7) However by approximating the voltage at node to rst order approximation we get v (t) = v (R d + R) c M e M t and the approximate peak noise amplitude on the victim is v UB = v a M = v (R d + R ) c M (8) Later in the discussion we show thattheabove obtained peak noise expression yields an upper bound on the peak noise values when compared to SPIE results. Hence we refer this model as L UB in our discussion. Now if we do not consider interconnect resistance so that R and R are set to zero the circuit model becomes the same as that of [8] and the peak voltage reduces to v peak = v ( + = c + R d =R d ( + = c )). Hence our derivation of v peak by considering interconnect resistance yields a more general expression for noise peak voltage than that of [8]. 3.. Ramp Input Analysis We now extend the derivation to the case of a ramp input voltage at the source of aggressor line. The ramp input voltage in the transform domain is expressed as S = v s T S e st S where TS is slew time of the ramp input [3]. Substituting for S the frequency domain expression for the voltage at node can be written as (s) = v e st S a s (9) s T S +sm + s M 6

7 The above equation can be reduced further by applying partial fractions i.e. 8 h v a >< T + S M s (s s ) e st M s (s s ) e sti v (t) = h >: v a i T S M s (s s ) e s t e s (tt S ) M s (s s ) e s t e s (tt S ) t T S t>t S () The time at which v (t) reaches peaks is computed using the v (t) expression for t>t S as t peak = (s s ) ln e s T S. The corresponding expression for peak voltage is e sts v peak = v a T S " ( e sts ) e s T S M s (s s ) e sts s=(s s ) ( ests ) M s (s s ) e s T S s=(s s ) # e sts Again we compute the upper bound on the peak noise value by approximating the voltage at node to rst moment as v UB = v (R d + R ) c T S h e TS=M i The noise peak estimation for our L model using Equations (7) and () are compared with SPIE results and other approaches in the literature or various interconnect con- gurations (see Table 3). To compute the interconnect delay on aggressor line we obtained the voltage expression at the node B as 8 >< v B (t) = >: v T S (k + k t + k 3 e st + k 4 e s3t ) v T k T S + k 3 e s t e s (tt S ) + k4 e s 3t e s 3 (tt S ) S t T S () () t>t S (3) where k = a s s + s + s s s k = k 3 = ( + a s ) s (s s ) k 4 = ( + a s ) s (s s ) s ;3 = p M =M (M =M ) 4=M. 3. ictim and Aggressor Switching in Opposite Directions In deep-submicron processes the interconnect coupling capacitance is a major part of total capacitance; hence interconnect delay can vary signicantly depending on switching behavior. When two neighboring lines are switching in the opposite direction then the eective coupling capacitance can be up to twice the nominal coupling capacitance depending on the amount ofoverlap of input waveforms i.e. c (eff) =SF c where the switch factor SF [:; :]. To estimate the worst possible interconnect delay one approach used widely in industry is to assume a worst-case switch factor of SF =: and then scale the coupling capacitance by SF distributing this eective coupling capacitance along with interconnect parallel plate capacitance in the region where the lines overlap. This approach can be too pessimistic forcing suboptimal design decisions. Using the circuit model of Figure wenow compute the voltage at the output of both victim and aggressor lines i.e. voltage at nodes and B. Using the nodal equations at B and and substituting S = S for input voltages we obtain the following 7

8 expressions for voltage in the frequency domain (by approximating to rst moment only): where M and M are same as in Equation (3) and B +a s = (4) S +M s + s M +a s = (5) S +M s + s M a = (R d + R )( + c ) (R d + R ) c a = (R d + R )( + c ) (R d + R ) c (6) Note that the voltage expressions for nodes B and are similar except that they have dierent coecients in the numerator. 3.. Step Input Analysis We now consider step inputs switching opposite directions at the line inputs i.e. S = S = s. onverting the frequency domain voltage expression in Equations (5) and (4) to the time domain we get the expressions similar to (4). In (7) a is used and in (8) a is used for computing correct values of k k andk. v B (t) =v k + k e st + k e st (7) 3.. Ramp Input Analysis v (t) =v k + k e st + k e st (8) For ramp inputs switching in opposite directions at the line inputs we have S = S = v e st S. The time-domain expressions for voltage at nodes B and s T S are similar to Equation (3) except for dierent coecients. 8 >< v B (t) = >: v M T S (k + k t + k e st + k 3 e s3t ) v M T k T S + k e s t e s (tt S ) + k3 e s 3t e s 3 (tt S ) S t T S t>t S (9) 8 >< v (t) = >: v M T S (k + k t + k e st + k 3 e s3t ) v M T S k T S + k e s t e s (tt S ) + k3 e s 3t e s 3(tT S ) t T S t>t S () 3.3 ictim and Aggressor Switching in Same Direction When two neighboring wires are switching in the same direction then the eective coupling capacitance between the lines is c (eff) = SF c where the switch factor SF [; ] again depends on the amount ofoverlap of input waveforms. If both wires switch at exactly the same time with identical slew then the eective coupling capacitance between the lines is zero. This produces a lower bound on the interconnect delay 8

9 with corresponding best-case delay estimates computed by not considering any coupling capacitance between the lines (i.e. using only a given line's R values). Using the circuit model given in Figure and substituting S = S for the input voltages we can compute the voltages on both lines. The analysis for this case is slightly dierent from the remaining cases. Here we have to take the second order moment to avoid the degenerate case when the coupling is not playing any role. This would be the case when the both the interconnects have the same electrical parameters (Resistance apacitance etc.) and the characteristics of the two wires are exactly similar. In that case there is no currentowing due to the coupling capacitance and the correct solution for that case is obtained only by considering the second order moments as well. Thus the expressions for B and for this case are given as: where B +a s = () S +M s + M s ( + a s) = () S +M s + M s a = (R d + R )( + c )+(R d + R ) c a = (R d + R )( + c )+(R d + R ) c (3) and M and M is given by Equation (3) Step Input Analysis As discussed above the time-domain expression for voltage at nodes B and can be obtained similar to Equation (4) except for dierent coecients. v B (t) =v k + k e st + k e st (4) 3.3. Ramp Input Analysis v (t) =v k + k e st + k e st (5) Using the partial fractions the time-domain expressions for voltage at nodes B and can be obtained similar to Equation (3) (3) except for dierent coecients. 8 >< v B (t) = >: 8 >< v (t) = >: v M T S (k + k t + k e st + k 3 e s3t ) v M T k T S + k e s t e s (tt S ) + k3 e s 3t e s 3 (tt S ) S v M T S (k + k t + k e st + k 3 e s3t ) v M T k T S + k e s t e s (tt S ) + k3 e s 3t e s 3 (tt S ) S t T S t>t S (6) t T S t>t S (7) When both lines are switching in the same direction the interconnect delay estimates corresponds to the optimistic delay for coupled lines. Hence we can use our above derived expressions to compute delay uncertainty for various cases of input switching criteria. 9

10 4 Noise and Delay Estimation Using the model for Interconnect AGGRESSOR LINE R d A R B s c L c ITIM LINE R d D R s L Pi Model for lines Figure 4: Equivalent circuit (using model for interconnect) for the conguration of Figure. In this section we apply the model for the interconnect and compute both the noise peak voltage and delay on the interconnects as shown in Figure 4. Our analyses address both the step and ramp input regimes. In the rst subsection we study the same case as in Section 3.: one line switching and other line quiet. In the second and third subsections we study the case when the lines are switching in opposite directions. For these latter cases we also study the impact of noise on delay of the aggressor line. Our basic analysis approach is as follows: We use Figure 4 as the equivalent circuit for analysis purposes. Note that we have distributed the interconnect line capacitance in two parts (ground capacitance and coupled capacitance). We will use the same approach for analysis as we did with the L interconnect model i.e. we transform the time domain circuit equations to frequency domain using Laplace transforms solve the equations then convert the results back to the time domain. To nd the noise voltage at the end of victim line we must solve for v (t) while to nd the impact of crosstalk on delay wemust solve for v B (t). The nodal equations at nodes A B and D in Figure are given in (8). S = A + R d [ A s +( A D )s + B s +( B )s ] A = B + R [ B s +( B )s ] S = D + R d [ D s +( D A )s + s +( B )s ] D = + R [ s +( B )s ] (8)

11 4. ictim Quiet and Aggressor Switching For this case the victim line is quiet at low voltage while the aggressor line is switching from low to high. Therefore S =. Solving the equations (8) with S = yields the following transfer function in frequency domain for noise at node and at node B (we approximate the solution to second moment only). S = a s + a s +b s + b s (9) where B S = +c s + c s +b s + b s (3) a = R + R d + R d a = R d R + R d R + R d R + R d R b = R + R d + R d + R + R d + R d + R + R d + R d + R d + R + R d b = R d R + R d R + R d R + R d R + R d R + R d R d + R d R d + R d R d + R d R d + R d R + R d R + R d R d + R d R d + R d R d + R d R d + R d R + R R + R R + R R d + R d R + R d R + R d R + R d R + R d R + R d R + R d R + R d R + R d R d + R d R d + R d R d + R d R d + R R d + R R d + R R + R R d + R R d + R d R c = R + R d + R d + R + R d + R d c = R d R + R d R + R d R + R d R + R d R (3) We now compute the time-domain solutions voltage on both victim and aggressor lines by applying both step and ramp inputs at the input of the aggressor lines. 4.. Step Input Analysis onsider astepinput at the aggressor i.e. S = v s in the transform domain. The voltage at node of the victim using Equation (9) can be expressed as a + a s (s) = v +b s + b s = v b k s s + k s s Using partial fractions and inverse Laplace transforms the above equation can be written in time-domain as v (t) = v b k e st + k e st (3) where k = s a b a b + a b s b + b k = b (s a + a ) s b + b s s = b ands + s = b b.

12 Similarly using Equation (3) the voltage at node B of the aggressor line can be expressed as B (s) = v s = v b +c s + c s +b s + b s k s + k + k s s s s Applying partial fractions and inverse Laplace transforms the corresponding timedomain expression is v B (t) = v b k + k e st + k st where k = b k = s b + s b c + c b c b s b + k b = b (s b b + s c + c ) s b + b s s = b ands + s = b. The voltage v b B (t) on the aggressor line can be used to study delay uncertainty dueto coupling i.e. the change in delay due to the coupling eect with the victim line. This type of analysis { to compute delay and delay uncertainty on an aggressor line { is also very useful when the victim line is active (see next subsection). The voltage v (t) represents noise on victim line due to the input switching on the aggressor line. To nd the peak noise for this conguration we dierentiate Equation (3) with respect to t and set the derivative to zero. The time at which peak noise is reached is t peak = ln k s s s k s with peak noise given by v c;peak (t) =v (t peak ). 4.. Ramp Input Analysis For ramp input analysis we use the frequency domain expression for a ramp input: S = v e st S and S =. The voltage at node of the victim line in the s T S transform domain can be expressed as (s) = v ( e sts ) a + a s st S +b s + b s = v ( e sts ) k T S b s + k + k s s s s (33) (34) The corresponding time-domain expression is given by 8 >< v (t) = >: v b T S (k + k e st + k e st ) v b T k e s t e s (tt S ) + k e s t e s (tt S ) S t T S t>t S (35) where k = a b k = b (a + s b a ) s b + k b = b (s b a a b + a ) s b + s b s = b and s + s = b and b

13 Again using partial fractions and inverse Laplace transforms allows us to convert Equation (3) into a time-domain expression for the ramp input conguration: 8 v >< (k b T + k t + k e st + k 3 e st ) t T S S v B (t) = >: v (36) k T b T S + k e s t e s (tt S ) + k3 e s t e s (tt S ) t>t S S where k = (b + c ) b k = b k = b b s b + b c b s c b b + c b s + b k 3 = b (b + c b s b + c b s ) b s + s b s = ands b + s = b. b To nd the peak noise we dierentiate Equation (35) and set the result to zero. The expression for peak time is thus t peak = s s ln k s k s t peak = s s ln k s e s T S k s e sts t peak T S t peak >T S (37) from which peak noise voltage can be computed by substituting t peak values into Equation (35) with v (t peak ) = max fv (t peak );v (t peak )g. 4. ictim and Aggressor Switching in Opposite Directions When aggressor and victim are switching simultaneously in opposite directions we have S = S. Solving the set of Equations (8) with S = S yields the following transfer function in the frequency domain (after retaining terms with up to power of two ins): s s A D AGGRESSOR LINE ITIM LINE (a) Step Input c B s T R A AGGRESSOR LINE B T R s D ITIM LINE (b) Ramp Input Figure 5: ircuit for the case when the victim is switching in opposite direction to the aggressor: (a) step input and (b) ramp input. c S = +a s + a s +b s + b s (38) 3

14 where B S = +c s + c s +b s + b s (39) a = (R + R + R d R d + R d + R d + R d R R d ) a = (R d R R d R R d R R d R + R d R + R d R + R d R + R d R R d R ) c = (R R d + R d R d R d R d R R + R d ) c = R d R R d R R d R + R d R + R d R R d R R d R + R d R + R d R (4) and the denominator terms b and b are the same as in Equation (3). As before we these analytical equations for voltage on victim and aggressor lines are useful in computing delay and delay uncertainty with respect to input slew time coupling capacitance etc. With the above derivations we can obtain a complete set of analytical tools to estimate noise peaks and delay uncertainty eects. 4.. Step Input Analysis With a step input for the aggressor S = v s. Using Equation (38) the voltage at node of the victim can be expressed as (s) = v s = v b +a s + a s +b s + b s k s + k + k s s s s Applying partial fractions and inverse Laplace transforms the corresponding timedomain expression is given by v (t) = v b k + k e st + k st where k = b k = s b + s b a + a b a b s b + b k = b (s b + b + s a + a ) s b + b s s = b ands + s = b. b Note that the B (s) expression in Equation (39) is similar to the Equation (3) for the case when the victim line is quiet; the only dierence is that one must substitute correct values of c and c as derived in Equation (4) in the expressions for k k s and s given below the Equation (33). Hence for the sake of completeness the time-domain expression for voltage on aggressor line is v B (t) = v b k + k e st + k st (4) (4) 4

15 4.. Ramp Input Analysis Now we consider a ramp input at the input of the aggressor line i.e. S = v s T S e st S [3]. As discussed before using partial fractions and inverse Laplace transforms the time-domain expression for v (t) isgiven by 8 >< v (t) = >: v b T S (k + k t + k e st + k 3 e st ) v b T k T S + k e s t e s (tt S ) + k3 e s t e s (tt S ) S t T S t>t S (43) where k = (b + a ) b k = b k = b b s b b a b s a b + b + a b s + b k 3 = b (b + a + b s b + a b s ) b s + s b s = ands b + s = b. b As above since the B (s) expression is the same for \victim line is quiet" as it is for \victim line is active" the time-domain expression is the same as in Equation (36) i.e. 8 >< v B (t) = >: v b T S (k + k t + k e st + k 3 e st ) v k T b T S + k e s t e s (tt S ) + k3 e s t e s (tt S ) S t T S t>t S (44) where the expressions for k k s ands are identical to those presented in Equation (36) and values of c and c are substituted according to Equation (4). 4.3 ictim and Aggressor Switching in Same Direction Finally when the aggressor and victim are switching simultaneously in the same direction we have S = S. Solving the set of Equations (8) with S = S yields the the following transfer function in the frequency domain (after retaining terms with up to power of two ins): S = +a s + a s +b s + b s (45) where B S = +c s + c s +b s + b s (46) a = R + R + R d + R d + R d + R d + R d + R +R d a = R d R + R d R + R d R + R d R + R d R + R d R + R d R + R d R + R d R c = R + R + R d + R d + R d + R d + R d + R +R d c = R d R + R d R + R d R + R d R + R d R + R d R + R d R + R d R + R d R (47) and the denominator terms b and b are the same as in Equation (3). 5

16 s A AGGRESSOR LINE B s D ITIM LINE (a) Step Input c s T R A AGGRESSOR LINE B s T R D ITIM LINE (c) Ramp Input Figure 6: ircuit for the case when the victim is switching in same direction to the aggressor: (a) step input and (b) ramp input. c 4.3. Step Input Analysis Note that the (s) expression in Equation (45) is similar to the Equation (3) for the case when the victim line is quiet; the only dierence is that one must substitute a and a from Equation (47) instead of c and c respectively in the expressions for k k s and s given below in the Equation (48). Hence for the sake of completeness the time-domain expression for voltage on aggressor line is v (t) = v b k + k e st + k st Again note that the B (s) expression in Equation (46) is similar to the Equation (3) for the case when the victim line is quiet; the only dierence is that one must substitute correct values of c and c as derived in Equation (47) in the expressions for k k s and s given below the Equation (49). Hence for the sake of completeness the time-domain expression for voltage on aggressor line is v B (t) = v b 4.3. Ramp Input Analysis k + k e st + k st Since the (s) expression is similar to Equation (3) the time-domain expression is again similar to Equation (36) i.e. 8 >< v (t) = >: v b T S (k + k t + k e st + k 3 e st ) v k T b T S + k e s t e s (tt S ) + k3 e s t e s (tt S ) S t T S (48) (49) t>t S (5) where the expressions for k k s ands are same as those presented in the Equation (36) and one must substitute the values of a and a instead of c and c as given in Equation (47). 6

17 5 Experimental Results To validate our new analyses we have considered two adjacent M3interconnects used in a real microprocessor design for.5 m MOS technology. We assume identical interconnects are driven by identical inverters of size (563) m and also assume that the loads at the end of the lines are identically sized inverters. We study various con- gurations of interconnect length width and spacing as shown in Table. The context for this experimentation is to discover how close our proposed L and models compare to SPIE simulations for both noise peak and delay estimation. We now express the resistance and capacitance circuit parameters in Figure and Figure 4 in terms of the interconnect parameters given in Table. For the L interconnect model we consider = = gnd + L and c = coup while for the interconnect model = = gnd = = = gnd =+ L and c = c= coup =. The load capacitance due to the inverter gate capacitance is L = L =53fF. ases width spacing length R int gnd coup (in m) (in m) (in m) (in ) (in ff) (in ff) Table : Interconnect parameters used in various SPIE simulations ( L = 53 ff due to inverter gate capacitance for all cases). We simulate the coupled interconnects by using dierent input slew times ranging from ps to 4ps for the driving inverters. We rst compute the noise peaks for all four test cases under dierent slew times using SPIE simulation and our estimation values for L and models as shown in Table 3. In the table L UB is the upper bound of peak noise when we use the formulas given by Equations (8) and () and L Our for peak noise when we use the formulas given by Equations (7) and () for the L model of the interconnect for the step and ramp input cases (Section 3.). For the model the noise peak ( Our ) is computed using Equations (34) and (37)) for the step and ramp input cases (Section 4.). In Table 3 the noise values are normalized to the supply voltage value i.e. v (t). Peak normalized noise values in Tables 3 and 4 are also compared with the two existing models of [5] and [8] as well as with SPIE simulation results. The L values are the peak noise values obtained using the formula of [8]. For we [8] [5] take the noise formula ofkawaguchi and Sakurai [5] for the -line case when both the victim and aggressor lines are switching in opposite directions and divide it by two to obtain the noise peak when only the aggressor is switching. Our results for the interconnect model as shown in Tables 3 and 4 are within 3% of the values derived by SPIE results for peak noise. Also our new noise estimators are substantially more accurate than previous models of [8] [5]; in terms of design impact we believe that less over-design and guard-banding will be necessary if our new approximations are adopted. Since in the L model all the interconnect resistance (R )is 7

18 loaded with the total interconnect capacitance ( ) the noise peak estimated in this model is an upper bound as compared to SPIE result. Similarly since in the the interconnect resistance (R )is loaded with the half the interconnect capacitance ( =) the noise peak estimated in this model is an lower bound as compared to SPIE result. To make this clear we have plotted the noise peaks in Tables 3 and 4 for all four cases graphically in Figure 7. Hence our L and models can in practice be used as an upper and lower bound estimators for the noise peaks in LSI interconnects. Finally Table 5 shows a comparison of interconnect delays on the aggressor line computed using SPIE and our model for the case when the aggressor line is switching and the victim line is quiet. We use the 5% threshold to compute the interconnect delay from the output of the driver to the next inverter input. Similarly Table 6 gives a comparison of interconnect delays on the aggressor line for the case when both victim and aggressor line are switching in opposite directions. This case yields pessimistic or worst-case interconnect delayvalues between the two coupled interconnects. From Table 6we see that our model delays are { again in practice { a lower bound and our L model delays are an upper bound for the SPIE-computed values. Finally Table 7 gives a comparison of interconnect delay on the aggressor line for the case when victim and aggressor are switching in same direction. This case yields optimistic or best-case interconnect delay values between the two coupled interconnects. From Tables 6 and 7 we can get the delay uncertainty results (Table 8 and Figures 8 and 9). The results shown in above tables indicate that our improved modeling methodology can be used to accurately predict the delay for coupled interconnects. T S =ps ases SPIE L [8] [5] L Our L UB Our Table 3: Normalized peak noise values under step input (T S = ) for two coupled interconnect conguration under various models. Our L UB gives upper bound on noise peak values and our Our generate values close to SPIE results. T S =ps T S =ps T S =4ps ases SPIE L Our L UB Our SPIE L Our L UB Our SPIE L Our L UB Our Table 4: Normalized peak noise values for dierent input slew times for the two coupled interconnect conguration under various models. 8

19 T S =ps T S =ps ases SPIE Our L Our SPIE Our L Our T S =ps T S =4ps Table 5: omparison of aggressor line interconnect delay for 5% threshold delay (in ps) using SPIE and our model for the case when the victim line is quiet. Note that interconnect delay is same for both rise and fall switching. T S =ps T S =ps ases SPIE Our L Our SPIE Our L Our T S =ps T S =4ps Table 6: omparison of aggressor line interconnect delay for 5% threshold delay (in ps) using SPIE and our model and L model for the case when the victim line switching opposite to the aggressor. We assume Line is switching from to and Line is switching from to. Note that delay values are same for both Line and Line as they are identical in this case. 6 onclusions and Future Work In conclusion we have derived improved noise and delay estimates using more accurate circuit modeling techniques. Specically we have derived analytical expressions T S =ps T S =ps ases SPIE Our L Our SPIE Our L Our T S =ps T S =4ps Table 7: omparison of aggressor line interconnect delay for 5% threshold delay (in ps) using SPIE and our model and L model for the case when the victim line switching in the same direction as the aggressor. We assume both Line and Line are switching from to. 9

20 T S =ps T S =ps ases SPIE Our L Our SPIE Our L Our T S =ps T S =4ps Table 8: Delay Uncertainty table for 5% threshold delay (in ps) using SPIE and our model and L model. for noise on a victim interconnect and calculated the impact on delay for the aggressor interconnect for both the step input and ramp input regimes. The approach extends easily to other modes of simultaneous switching phase osets etc. Our results include easily evaluatable expressions for crosstalk amplitude and delay for coupled R interconnects. These expressions are demonstrated to be more general and accurate than previous methods in the literature notably those of [8] and [5] and are for the interconnect model within 3% of SPIE simulation results. We plan to extend our validation experiments to a wider range of data from current microprocessor design projects. References [] H. B. Bakoglu ircuits Interconnections and Packaging for LSI Addison Wesley 99. [] A. Devgan \Ecient oupled Noise Estimation for On-hip Interconnects" IEEE/AM International onference on omputer-aided Design Nov 997 p [3] A. B. Kahng K. Masuko and S. Muddu \Analytical Delay Models for LSI Interconnects Under Ramp Input" Proc. AM/IEEE Intl. onference on omputer- Aided Design Santa lara November 996 pp [4] G. A. Katopis and H. H. Smith \oupled Noise Predictors for Lossy Interconnects" IEEE Transactions on omponents Packaging and Manufacturing Technology- Part B ol. 7 No.4 Nov. 994 pp [5] H. Kawaguchi and T. Sakurai \Delay and noise formulas for capacitively coupled distributed R lines " Proc. Asian and South Pacic Design Automation onference 998 pp [6] K. Rahmat and O. S. Nakagawa and S-Y. Oh and J. Moll \A Scaling Scheme for Interconnect in Deep-Submicron Processes" IEEE International Electron Devices Meeting 995 pp [7] K. L. Shepard S. M. arey E.K.hoB. W. urran R. F. Hatch D. E. Homan S. A. Mcabe G. A. Northrop and R. Seigler \Design methodology for the

21 S/39 Parallel Enterprise Server G4 microprocessors" IBM Journal of Research and Development Jul-Sep 997 vol. 4 no. 4-5 pp [8] A. ittal and M. Marek-Sadowska \rosstalk reduction for LSI" IEEE Transactions on omputer-aided Design of Integrated ircuits and Systems March 997 vol. 6 pp [9] G. Yee R. handra. Ganesan and. Sechen \Wire Delay inthepresence of rosstalk" AM/IEEE International Workshop on Timing Issues in the Specication and Synthesis of Digital Systems Dec. 97 pp

22 . Noise Analysis for ase L_UB L_OUR PI_OUR SPIE L_ITTAL/SAKURAI.3.8 Noise Analysis for ase L_UB L_OUR PI_OUR SPIE L_ITTAL/SAKURAI.5.6 Noise values (in ). Noise values (in ) Slew on input of the inverter for both lines (in ps) Slew on input of the inverter for both lines (in ps).3.8 Noise Analysis for ase3 L_UB L_OUR PI_OUR SPIE L_ITTAL/SAKURAI..8 Noise Analysis for ase3 L_UB L_OUR PI_OUR SPIE L_ITTAL/SAKURAI.6 Noise values (in ).4.. Noise values (in ) Slew on input of the inverter for both lines (in ps) Slew on input of the inverter for both lines (in ps) Figure 7: Plot of peak noise values as given in Table 3 and 4 for dierent input slew times for case. (Note that we have only one sampling point for other approaches in literature.)

23 Delay Uncertainty Analysis for ase SPIE L_OUR PI_OUR 5 45 Delay Uncertainty Analysis for ase SPIE L_OUR PI_OUR Delay Uncertainty values (in ps) 5 5 Delay Uncertainty values (in ps) Slew on input of the inverter for both lines (in ps) Slew on input of the inverter for both lines (in ps) Delay Uncertainty Analysis for ase3 SPIE L_OUR PI_OUR 4 Delay Uncertainty Analysis for ase4 SPIE L_OUR PI_OUR 8 Delay Uncertainty values (in ps) 6 4 Delay Uncertainty values (in ps) Slew on input of the inverter for both lines (in ps) Slew on input of the inverter for both lines (in ps) Figure 8: Plot of delay uncertainty values as given in Table 8 for dierent input slew times for all cases. Delay Uncertainty values (in ps) Delay Uncertainty v/s oupling apacitance pislew= pislew= pislew= pislew=4 spiceslew= spiceslew= spiceslew= spiceslew=4 Delay Uncertainty values (in ps) 5 5 Delay Uncertainty Percentage v/s oupling apacitance pislew= pislew= pislew= pislew=4 spiceslew= spiceslew= spiceslew= spiceslew= Different oupling apacitance alues (in ff) Different oupling apacitance alues (in ff) Figure 9: Plot of delay uncertainty values as obtained from Table 8 for dierent coupling capacitances for Pi-Model and Spice simulations. 3