MC14093B. Quad 2 Input NAND" Schmitt Trigger

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Myron Todd
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MC4093B Quad 2Input NAND" Shmitt Trigger The MC4093B Shmitt trigger is onstruted with MOS Phannel and Nhannel enhanement mode devies in a single monolithi struture.

1 MC4093B Quad 2Input NAND" Shmitt Trigger The MC4093B Shmitt trigger is onstruted with MOS Phannel and Nhannel enhanement mode devies in a single monolithi struture. These devies find primary use where low power dissipation and/or high noise immunity is desired. The MC4093B may be used in plae of the MC40B quad 2input NAND gate for enhaned noise immunity or to square up slowly hanging waveforms. Features Supply Voltage Range = 3.0 Vd to 8 Vd Capable of Driving Two LowPower TTL Loads or One LowPower Shottky TTL Load Over the Rated Temperature Range Triple Diode Protetion on All Inputs PinforPin Compatible with CD4093 Can be Used to Replae MC40B Independent ShmittTrigger at eah Input PbFree Pakages are Available MAXIMUM RATINGS (Voltages Referened to ) Symbol Parameter Value Unit DC Supply Voltage Range 0.5 to +8.0 V V in, V out I in, I out P D Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Pakage (Note ) 0.5 to V ± 0 ma 500 mw T A Ambient Temperature Range 55 to +25 C T stg Storage Temperature Range 65 to +50 C T L Lead Temperature (8Seond Soldering) 260 C Stresses exeeding Maximum Ratings may damage the devie. Maximum Ratings are stress ratings only. Funtional operation above the Reommended Operating Conditions is not implied. Extended exposure to stresses above the Reommended Operating Conditions may affet devie reliability.. Temperature Derating: Plasti P and D/DW Pakages:.0 mw/ C From 65 C To 25 C This devie ontains protetion iruitry to guard against damage due to high stati voltages or eletri fields. However, preautions must be taken to avoid appliations of any voltage higher than maximum rated voltages to this highimpedane iruit. For proper operation, V in and V out should be onstrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logi voltage level (e.g., either or ). Unused outputs must be left open. A WL, L YY, Y WW, W G or PDIP4 P SUFFIX CASE 646 SOIC4 D SUFFIX CASE 5A TSSOP4 DT SUFFIX CASE 948G SOEIAJ4 F SUFFIX CASE MARKING DIAGRAMS MC4093BCP AWLYYWWG 4 = Assembly Loation = Wafer Lot = Year = Work Week = PbFree Pakage 4093BG AWLYWW 4 093B ALYW MC4093B ALYWG (Note: Mirodot may be in either loation) ORDERING INFORMATION See detailed ordering and shipping information in the pakage dimensions setion on page 2 of this data sheet. Semiondutor Components Industries, LLC, 2006 Otober, 2006 Rev. Publiation Order Number: MC4093B/D

2 MC4093B PIN ASSIGNMENT LOGIC DIAGRAM IN A IN 2 A IN 2 D 2 3 OUT A OUT B IN D OUT D IN B IN 2 B OUT C IN 2 C IN C 2 3 = PIN 4 = PIN EQUIVALENT CIRCUIT SCHEMATIC (/4 OF CIRCUIT SHOWN) ORDERING INFORMATION Devie Pakage Shipping MC4093BCP MC4093BCPG MC4093BD MC4093BDG MC4093BDR2 MC4093BDR2G MC4093BDTR2 MC4093BDTR2G MC4093BFEL MC4093BFELG PDIP4 PDIP4 (PbFree) SOIC4 SOIC4 (PbFree) SOIC4 SOIC4 (PbFree) TSSOP4* TSSOP4* SOEIAJ4 SOEIAJ4 (PbFree) 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 2000 Units / Tape & Reel For information on tape and reel speifiations, inluding part orientation and tape sizes, please refer to our Tape and Reel Pakaging Speifiations Brohure, BRD80/D. *This pakage is inherently PbFree. 2

3 MC4093B ELECTRICAL CHARACTERISTICS (Voltages Referened to ) ÎÎ 55 C 25 C ÎÎ 25 C Î Charateristi Î Symbol Vd Min MaxÎ Min Typ (2) Î Max Min Max Unit Î Output Voltage 0 Level Î V OL 0.05Î 0 Î Vd V Î in = or Î Level V OH ÎÎ 4.95 Î V in = 0 or Î Î 9.95 Vd Output Drive Current I Î (V OH = 2.5 Vd) Soure Î OH mad 3.0 Î Î. Î (V OH = 4.6 Vd) 0.64 Î Î 0.36 (V Î OH = 9.5 Vd) (V OH = 3.5 Vd) Î Î 2.4 Î (V OL = 0.4 Vd) Sink Î I OL 0.64 Î (V OL = 0.5 Vd) Î Î 0.9 mad (V OL =.5 Vd) Input Current I in 5 ± 0. ± ± 0. ±.0 Ad Input Capaitane C Î (V in = 0) Î in.5 pf Î Quiesent Current Î I DD Î (Per Pakage) Î Î Î Ad Total Supply Current Î (3) (4) I (Dynami plus Quiesent, Î T I 0 ÎÎ T = (.2 A/kHz) f + I DD Ad I T = (2.4 A/kHz) f + I DD Î Per Pakage) 5 ÎÎ I T = (3.6 A/kHz) f + I DD (C Î L = 50 pf on all outputs, all buffers swithing) Î Hysteresis Voltage Î V H Î Î Vd Threshold Voltage Vd Î PositiveGoing Î V T Î Î NegativeGoing V Î T Vd Î Î Data labelled Typ is not to be used for design purposes but is intended as an indiation of the IC s potential performane. 3. The formulas given are for the typial harateristis only at 25 C. 4. To alulate total supply urrent at loads other than 50 pf: I T (C L ) = I T (50 pf) + (C L 50) Vfk where: I T is in A (per pakage), C L in pf, V = ( ) in volts, f in khz is input frequeny, and k =

4 MC4093B SWITCHING CHARACTERISTICS (C L = 50 pf, T A = 25 C) Î Î Î Charateristi Symbol Vd Min Typ Î (5) Max Unit Output Rise Time t Î TLH ns Î Î Î Î 5 Î Î 40 Î 80 Output Fall Time ÎÎ t THL Î Î Î 00 Î 200 ns Î Propagation Delay Time t PLH, t PHL Î Î Î Î 0 Î Î 50 Î 00 ns 5. Data labeled Typ is not to be used for design purposes but is intended as an indiation of the IC s potential performane ns 20 ns PULSE GENERATOR INPUT 4 VSS C L OUTPUT INPUT t PHL OUTPUT 90% 50% 0% 90% 50% 0% t PLH V OH V OL t THL t TLH Figure. Swithing Time Test Ciruit and Waveforms V H V H V in V in V out V out (a) Shmitt Triggers will square up (a) inputs with slow rise and fall times. (b) A Shmitt trigger offers maximum (b) noise immunity in gate appliations. Figure 2. Typial Shmitt Trigger Appliations 4

5 MC4093B 4 I OH V out V GS 4 I OL V out All unused inputs onneted to ground. V GS All unused inputs onneted to ground. I OH, DRAIN CURRENT (mad) a T A = 55 C b T A = + 25 C b T A = + 25 C V GS = Vd 0 Vd a a V DS, DRAIN VOLTAGE (Vd) b a b b 5 Vd I OL, DRAIN CURRENT (mad) a b b a 5 Vd V GS = 0 Vd a T A = 55 C b T A = + 25 C T A = + 25 C a 2.0 b Vd V DS, DRAIN VOLTAGE (Vd) Figure 3. Typial Output Soure Charateristis Test Ciruit Figure 4. Typial Output Sink Charateristis Test Ciruit V out, OUTPUT VOLTAGE (Vd) 0 0 VDD V T V T+ V H V in, INPUT VOLTAGE (Vd) Figure 5. Typial Transfer Charateristis 5

6 MC4093B PACKAGE DIMENSIONS PDIP4 CASE ISSUE P 4 8 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T N SEATING PLANE A INCHES MILLIMETERS DIM MIN MAX MIN MAX A B F L C D C F G 0.00 BSC 2.54 BSC H J K K J L M 0 0 H G D 4 PL M N (0.005) M 6

7 MC4093B SOIC4 CASE 5A03 ISSUE H T SEATING PLANE G A 4 8 D 4 PL B K P PL C 0.25 (0.00) M T B S A S 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.2 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 45 F DIM MIN MAX MIN MAX A B C D M J F G.2 BSC BSC J K M 0 0 P R SOLDERING FOOTPRINT* 4X 0.58 X.04 4X.52.2 PITCH DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiondutor Soldering and Mounting Tehniques Referene Manual, SOLDERRM/D.

8 MC4093B PACKAGE DIMENSIONS TSSOP4 CASE 948G0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 4X K REF 0.0 (0.004) M T U S V S N (0.00) M B U A V G H N J J F DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION NN DETAIL E NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J W K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH 4X X.26 DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiondutor Soldering and Mounting Tehniques Referene Manual, SOLDERRM/D. 8

9 MC4093B PACKAGE DIMENSIONS SOEIAJ4 CASE 9650 ISSUE A L E 4 8 Q E H E M L Z DETAIL P D VIEW P e A b A 0.3 (0.005) M 0.0 (0.004) NOTES: М. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 982. М 2. CONTROLLING DIMENSION: MILLIMETER. М 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. М 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. М 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b D E e.2 BSC BSC H E L E M Q Z ON Semiondutor and are registered trademarks of Semiondutor Components Industries, LLC (SCILLC). SCILLC reserves the right to make hanges without further notie to any produts herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its produts for any partiular purpose, nor does SCILLC assume any liability arising out of the appliation or use of any produt or iruit, and speifially dislaims any and all liability, inluding without limitation speial, onsequential or inidental damages. Typial parameters whih may be provided in SCILLC data sheets and/or speifiations an and do vary in different appliations and atual performane may vary over time. All operating parameters, inluding Typials must be validated for eah ustomer appliation by ustomer s tehnial experts. SCILLC does not onvey any liense under its patent rights nor the rights of others. SCILLC produts are not designed, intended, or authorized for use as omponents in systems intended for surgial implant into the body, or other appliations intended to support or sustain life, or for any other appliation in whih the failure of the SCILLC produt ould reate a situation where personal injury or death may our. Should Buyer purhase or use SCILLC produts for any suh unintended or unauthorized appliation, Buyer shall indemnify and hold SCILLC and its offiers, employees, subsidiaries, affiliates, and distributors harmless against all laims, osts, damages, and expenses, and reasonable attorney fees arising out of, diretly or indiretly, any laim of personal injury or death assoiated with suh unintended or unauthorized use, even if suh laim alleges that SCILLC was negligent regarding the design or manufature of the part. SCILLC is an Equal Opportunity/Affirmative Ation Employer. This literature is subjet to all appliable opyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiondutor P.O. Box 563, Denver, Colorado 802 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.om N. Amerian Tehnial Support: Toll Free USA/Canada Europe, Middle East and Afria Tehnial Support: Phone: Japan Customer Fous Center Phone: ON Semiondutor Website: Order Literature: For additional information, please ontat your loal Sales Representative MC4093B/D

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