The challenges of Power estimation and Power-silicon correlation. Yoad Yagil Intel, Haifa

Transcription

1 The challenges of estimation and -silicon correlation Yoad Yagil Intel, Haifa Nanoscale Integrated Systems on Chip, Technion, Dec. 006

2 Acknowledgements Yoni Aizik Ali Muhtaroglu

3 Agenda Introduction Can we predict power aurately? Short Circuit power Leakage Estimation vs. silicon Summary 3

4 Introduction is the #1 limiter of Moore s law Heat-sinks cannot cool more than ~130W Systems: limitations of heat dissipation & power consumption Servers, desk tops, small form factor, lap-tops Most systems allow much less than 130W Battery life for portable devices Leakage power - a significant component in deep sub-micron 0-50% of the overall power at active mode Dominates battery time in many usage scenarios 4

5 Design for low power Requires same concepts as design for high frequency budgets estimation and analysis -performance optimization Validation/rollup Aurate power estimation and good power-si correlation are keys for low power design 5

6 How to estimate power Simplistic power model P = C V f AF AF is estimated by some high power test Leakage is roughly liner with total Z / device count This is indeed simplistic! C is not that simple Voltage dependent; Xcap (Miller effect) AF is not straight forward Proper work loads; Glitches Additional power components Short circuit, contention Leakage is sensitive to everything In particular process, temperature, and voltage variations Full blown circuit simulation is far too slow Also useless until the design is mature enough And, still not fully aurate due to Xcap and process variations 6

7 Can we predict power aurately? model: P tot = P lkg + P dyn = P lkg + P sw + P sc + P cont + P glitch Simulation based model on inverters chain 8% gap between min and max C AF, SP, leakage, and SC are directly measured Using max-c result in 3% over-estimation estimation is far harder when applied to Full Chip Circuit includes more gates than just inverters C is estimated by (static) RC extract tools SC depends on slopes; timing only provides min/max slopes Contentions and glitches are hard to predict and model Analog & special circuits require special handling Leakage is sensitive to within-die and die-to-die variations 7

8 components model vs. simulation Simulation: Model is based on simulated inverters chain and measurements AF = 1 Cap, Xcap SC directly measured Auracy: ~3% Real life: Not only inverters C from RC-ext. Xcap estimated AF/SP by logic sim. SC estimated Contention Glitches Auracy:??? E-04.50E-04.00E E E E E E E E E E-04.50E-04.00E E E E-05 Switching power: min and max cap (P164) gap = 8% V V components SW 0.00E V total Lkg SC 5.00E E E E E-04.50E-04.00E E E E-05 Sw itching Pow er Miller=4 (164) Leakage Pow er (164) Total Heat Dissipation (164) Calc total Short Circuit (164) Total Heat Dissipation (164) 0.00E V Calc total Total based on Cmax & MCF=4, gap = 3% Sort-circuit / Switching (%) 0.00% 18.00% 16.00% 14.00% 1.00% 10.00% 8.00% 6.00% 4.00%.00% V 0.00% V V

9 Why Xcap/Miller consumes more power Regular capacitor: = C V f AF Charge Xcap = 4 C V f AF Charge Discharge Voltage swing = V Discharge Voltage swing = V Xcap/Miller cap consumes 4X the power of regular capacitor. De-coupling only provides a factor of. Impact: gate-drain (Miller); IC Xcap 9

10 Sensitivity to irregular waveform Example: marginal set-up time on a latch Waveform within the latch becomes very irregular Causes huge SC on the inverter that drives the output pin and on its receiver (not shown) Bad waveforms / long tails are expected on weak drivers like min-delay buffers and drivers that are down-sized to save power Latch Output Node internal Node 10

11 Short circuit - a simple model Model: unloaded symmetric inverter Current is dominated by device in saturation, Vds > Vgs-Vt > 0 Simple MOS model, Idsat = K/ (V gs -V t ) AF=1 ( transitions per cycle), current is symmetric around V in = V/ Clock period = T, slope = τ I V I P av in av sc = T t t = τ = T = I av V t t1 1 V V K V t / ( V V ) ; K in dv K τ = 1 T ( V V ) dv = ( V V ) in in t V = dt τ ( V V ) 3 t dt τ V t in K τ 1 1 T V Ref.: H.J.M. VEENDRICK, IEEE J. OF SOLID-STATE CIRCUITS, VOL. SC-19, NO. 4, 1984 t 3 11

12 Short circuit model cont. Some re-ordering: = av 3 3 bv ( V V ) T + cv d 3 Psc= ( K/1) Trf f T Psc α ( V Vt) 3 = α { V (6 V ) V + (1V ) V 8V } T 3 T Curve fit enables 3 independent Vt estimates Vt = b/6a ; c/b ; 3d/c It also predicts cube dependency in Vt SC(T) should be explained by Vt(T) Is it applicable for deep sub-micron devices? Possibly integral quantity might not be very sensitive to details 1

13 SC simulations & Fit to theory SC vs. V 164 step B SC Poly. (SC) SC vs. Vt 164 step A 1.40E E E E-05 power (W ) 1.00E E E E-05.00E E E v power (W ) 6.00E E E E-05.00E E E E Vt SC Poly. (SC) Vt (normalized): SC vs. T 1.0E-05 SC power (164 step B) Vt vs. T Vt b/6a =1.000 c/b = d/c=1.01 power (W) 1.00E E E E-06.00E E temp vt ( nm os) temp 13

14 SC model versus simulation Simulations indicate that the model is applicable for deep sub-micron devices Results were fitted to a 3 rd order polynomial No restrictions on the coefficients a, b, c, d All 3 ratios result in almost identical Vt value And the resulted Vt fits the process Vt SC power also fits a 3 rd order polynomial in Vt The temperature dependence of the SC power is is fully explained by Vt(T) So now let s compare with Si data 14

15 Cdyn with SC correction Measured Cdyn Measured Cdyn (nf) Cdyn vs Voltage (Tsoak=-5C) Cdyn w/o SC correction Estimated Cdyn (nf) Estimated Cdyn Measured Cdyn Measured Cdyn (nf) Cdyn vs Voltage (Tsoak=-5C to 95C) Estimated Cdyn (nf) Estimated Cdyn Cdyn = Cpure + Crt*(V-Vt) 3 /V Cdyn = Cpure + Crt*[V-Vt(SICC, T)] 3 /V Vt (SICC, T) = Vt dvtsicc * SICC dvtt * T Conclusion: SC model fits Si very well Cdyn becomes V, T, SICC independent Enables extracting SC power from Si measurements 15

16 Modeling Leakage Die to die and within die variations +/- 0% frequency var. >10X leakage variations Si measurements require a very large amount of dies DC simulations are insufficient to estimate leakage Normalized Frequency % 5X 130nm Normalized Leakage (Isb( Isb) (Ref: Pat Gelsinger, keynotes DAC 004) Frequency ~30% Leakage ~5-10X Getting worse in deeper sub-micron 16

17 Estimates vs. Silicon - Si correlation Comparing FC power vs. silicon, no finer granularity! We need richer power measurements and analysis methods Separate dynamic and leakage Not a trivial task! P dyn P tot V*SICC Requires thermal maps and a proper model Measure power as function of V, f, T, fast/slow dies measurements & estimates at different work loads Fine spatial resolution measurements IREM is a partial solution Possibly built-in probes for leakage and for dynamic power 17

18 Summary is one of the major challenges of the VLSI and SoC community is far more complex than C V f AF Poor abilities to correlate estimates with Si Room for further research on power modeling and on power-si correlation at product level 18