Combinatorial circuits - arithmetics

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1 Combinatorial circuits - arithmetics Lionel Morel Département Informatique - INSA Lyon Automne 2016 AC - Arith Automne / 19 Numerical Functions Blackboard AC - Arith Automne / 19

2 Numerical Functions Half-Adder The simplest one-bit operation used is called a half adder : inputs : two bits a and b that we want to add; outputs : a sum bit s and an output carry c o. a b s c o We see that: s = a b, et c o = a b. We build the corresponding circuit: Ah! But we also need to take the input carry into account. AC - Arith Automne / 19 Numerical Functions Blackboard AC - Arith Automne / 19

3 Numerical Functions Full-Adder The full adder has: inputs: 2 bits a and b, and one bit for the incoming carry c i ; outputs: one bit for the sum s and one bit for the output carry c o. For the carry: a b c i s c o We see that: s = a(b c i ) + a(b c i ). Since x y = xy + xy, we get s = a (b c i ) = a b c i. c o = abc i + abc i + abc i + abc i = (ab + ab)c i + ab(c i + c i ) = (a b)c i + ab. AC - Arith Automne / 19 Numerical Functions Full-Adder (contd) We get the circuit for a 1-bit full adder : AC - Arith Automne / 19

4 Numerical Functions n-bits Adder We can cascade k full adders to build a circuit that adds up 2 k-bits natural numbers. NB: The carry is propagated as we do in the hand-written operation. AC - Arith Automne / 19 Numerical Functions Intermission AC - Arith Automne / 19

5 Optimization criteria A boolean function f can be implemented by many ( ) circuits. What choice criteria can we use? number of logical gates dice area delay circuit frequency power consumption Optimization algorithms are exponential (in the number of input variables) an optimal circuit might not be found in a practible time. Example: Let s see how we can reduce a circuit s delay by parallelizing it. AC - Arith Automne / 19 Circuit Optimizations Propagation Delay of a logical circuit Propagation Delay Any circuit has a certain Propagation delay τ, defined as the time between a change on the circuit s inputs (at t) and the stabilization of the circuit s outputs (at t + τ). During [t, t + τ], outputs can be in unpredictable transient states. AC - Arith Automne / 19

6 Propagation Delay of a logical circuit Propagation Delay and Critical Path Each logical gate has a given (physically-fixed) delay. To determine a circuit s propagation delay, we need: compute the propagation delay associated to each path that connect one input to one output of the circuit; identify a path whose delay is maximal. This is called a critical path A circuit s propagation delay = delay of one of its critical paths. NB: There may be several critical paths. AC - Arith Automne / 19 Circuit Optimizations Propagation Delay of a logical circuit Example Blackboard AC - Arith Automne / 19

Propagation Delay of a logical circuit Example 1 1 https://en.wikipedia.

delay for all logical gates, the full adder s delay is 3 t. And the delay from r i à r o is 2 t.

7 Propagation Delay of a logical circuit Example AC - Arith Automne / 19 Circuit Optimizations Optimizing the Adder Carry Lookahead a b With a hypothetical 1 t propag. delay for all logical gates, the full adder s delay is 3 t. And the delay from r i à r o is 2 t. r s r e s b 3 a 3 b 2 a 2 b 1 a 1 b 0 a 0 For a 4-bits adder, the critical path is the one from r i to r o : delay = 8 t. r s r e For a 16-bits adder, delay is 16 t. s 3 s 2 s 1 s 0 b a b a r s r e 4 4 s s delay is proportional to the length of the carry propagation path. AC - Arith Automne / 19

8 Optimizing the Adder Speculate possible results: Carry Lookahead Compute the 4 LSbits of the result s, together with r i In parallel, compute two versions of the 4 MSbits of s One assuming that r i = 0 One assuming that r i = 1 Choose s 7..4 according to r i b a b a r e r i mux2-1 1 mux r s s s AC - Arith Automne / 19 Circuit Optimizations Optimizing the Adder Optimizing the (8-bits) adder If mux have a 2t delay. After 8t, r i is known, the two versions (one for r i = 0, one for r i = 1) The selection can now occur, based on r i. Delay from r e to r s falls to r e à r s 10t. We have just introduced parallelism. This reduces delay but it augments surface aka space-time tradeoff classic in CS, check out: AC - Arith Automne / 19

9 Optimizing the Adder La prochaine fois (je ne vous le chanterai pas...)... Hi, I m Dora, have we met??? Or, how to remember stuff that we will (surely) need later. aka, Registers and Memories. (and maybe we finish combinatorial circuits first) AC - Arith Automne / 19

Chapter 5 Arithmetic Circuits

Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed