Early Monolithic Pipelined ADCs

Transcription

1 Early Monolithic Pipelined ADCs Stephen H. Lewis Solid-State Circuits Research Laboratory Department of Electrical and Computer Engineering University of California, Davis CA USA 1

2 Pipelining Stage 1 Stage 2 Stage N Output Break a repetitive job into sequential stages When full, pipelines are fast Each stage can be optimized for the job it does All outputs come through the same path The same concept as in assembly lines 2

3 Pipelined ADC Concept Gordon, TCAS, 7/78 Jepperson, US Patent #3,119,105, 1/64 Waldhauer, US Patent #3,187,325, 6/65 Black, PhD Thesis, UC Berkeley, 11/80 McCharles, PhD Thesis, UC Berkeley, 6/81 Martin, Asilomar, 9/81 3

4 Pipelined ADCs Need SHAs φ 2 V i φ 1 C φ 1 V o CMOS provides simple SHAs MOS transistor switches have V DS = 0 when I D = 0 Little leakage 4

5 Algorithmic ADCs Analog 1 SHA 1-bit ADSC 1-bit DASC Σ 2 SHA Reusing stages saves area McCharles, Saletore, Black, and Hodges, ISSCC, 1977 Li, Chin, Gray, and Castello, JSSC 12/84 Shih and Gray, JSSC, 8/86 5

6 The First Monolithic Pipelined ADCs Analog Digital Output Digital Registers Stage 1 Stage i Stage k 1-bit ADSC 1-bit DASC Σ 2 SHA Masuda, Kitamura, Ohya, and Kikuchi, CICC b res. and linearity at 3 Msamples/s Yiu and Gray 12-b res. and 10-b linearity at 278 ksamples/s No redundancy 6

7 Masuda s SHA φ 1 φ 1 φ 1 φ 1 V i 2C C V o Single ended in 1.5-µm CMOS Uses partial offset cancellation at the input Uses dummy switch to reduce charge-injection error 7

8 V ip V in C Yiu s SHA C G 1 V o g 2 C H Fully differential in 3-µm CMOS Cancels offset at aux. input (Degrauwe, JSSC 8/85) Uses reference refreshing (Shih and Gray, JSSC 8/86) 9 clock phases per conversion Fabricated in 1984, PhD Thesis, UC Berkeley,

9 Increased Stage Resolution and Interstage Gain Analog Digital Output Digital Registers Stage 1 Stage i Stage k n-bit ADSC n-bit DASC Σ 2 n SHA Increasing n reduces significance of errors after first stage Still sensitive to first-stage comparator offsets 9

10 V R /8 0 V R /8 V R /4 V R /8 0 V R /8 V R /4 Held Residue Residue Negative Offset Residue Plots 3-bit ADSC 3-bit DASC Residue SHA Σ 8 Positive Offset Held Held Conv. Range Conv. Range If DASC is ideal, digital output and residue together are still accurate However, increasing max. Residue saturates next stage 10

11 Held Residue V R /4 V R /8 0 V R /8 V R /4 Reduced Interstage Gain Negative Offset 3-bit ADSC 1 3-bit DASC Residue SHA Σ 4 1 Positive Offset Held Conv. Range Halving the gain doubles the next-stage range Now the errors shown can be measured and corrected Correction requires ±1 Correction range is ±0.5 3-b level 11

12 Previous Work on Redundancy and Dig. Correction Verster, IEEE Trans. on Electronic Computers, 12/64 Gorbatenko, IEEE National Convention Record, 3/66 Kinniment, Aspinall, and Edwards, IEE Proc., 12/66 Horna, Comsat Technical Review, 1972 Taylor, PhD Thesis, UC Berkeley, 1978 Enabled by CMOS technologies 12

13 Interstage Offset without Redundancy Front end Stage i Σ Stage i 1 V OS Back end Output Code V OS = 0 Output Code V OS > 0 Nonlinearity Analog Analog If V OS 0, fine and coarse thresholds are not aligned Nonlinearity appears Offset cancellation is usually needed without redundancy 13

14 Interstage Offset with Redundancy n-bit ADSC n-bit DASC V OS SHA Σ Σ n V OS Σ Σ n-bit ADSC VOS n-bit DASC SHA Σ n If V OS < correction range, Nonlinearity does not appear V OS 0 causes only input-referred offset Offset cancellation is not required Reduces power dissipation 14

15 Berkeley Pipeline 3-µm double-poly CMOS Area = 5.5 mm 2 Power Diss. = 180 mw Speed = 5 Msamples/s Resolution = 9 bits 15

16 Held V R /4 Residue V R /8 Without 0 Offsets V R /8 V R /4 V R /4 Residue V R /8 With 0 Offsets V R /8 V R /4 Digital Correction with Offsets 3-bit 3-bit ADSC DASC Σ 0.5 LSB Σ 0.5 LSB Residue SHA Σ 4 Held Held Correction requires 1 when Residue > 0 Correction range is still ±0.5 3-b level Conv. Range Conv. Range 16

17 Sutardja s SHA φ 2 V i φ 1 C φ 1 V i φ 2 C φ 1 V o Uses feedforward to increase the gain Gives ideal gain = 2 with equal capacitors Increases FB factor and speed & improves accuracy PhD Thesis, UC Berkeley,

18 Residue V R /4 V R /8 0 V R /8 V R /4 Residue V R /4 V R /8 0 V R /8 V R /4 Drop the Top Comparator With top comparator Held Held Conv. Range Without top comparator Conv. Range Forces error that can be corrected (simplifies testing) Does not change the correction range Requires 2 n 2 comps (Res = log 2 (7) 2.8 b/stg) Not fast enough for video in 0.9-µm CMOS 18

19 1.5-bit Stage Resolution Residue 00 V R /2 V R /4 0 V R /4 V R / Held Conv. Range V R V R /4 V R /4 V R Requires 2 comps and 3 DAC levels (Res = log 2 (3) 1.5 b/stg) Same as in Jusuf, Memo No. UCB/ERL M90/69, UC Berkeley, 8/90 Ginetti, Jespers, and Vandemeulebroecke, JSSC 7/92 19

20 Multiplying-Digital-to-Analog Converter V ip V in V rp V rp X Z Y V rn V rn Y C C X φ 1 φ 1 φ 1 φ 1 C C φ 2 φ 2 φ 1 φ 1 φ 1 V op V on Feed forward improves accuracy and speed Generates 3 DAC levels Fast enough for video in 0.9-µm CMOS 20

21 AT&T Pipeline 0.9-µm double-poly CMOS Area = 8.7 mm 2 Power Diss. = 240 mw Speed = 20 Msamples/s Resolution = 10 bits 21

22 Other Work Karanicolas, Lee, and Bacrania, JSSC, 12/93 Cho and Gray, JSSC, 3/95 Cline and Gray, JSSC, 3/96 22

23 Acknowledgments Professor Paul R. Gray Professor T. R. Viswanathan My colleagues at Berkeley and Bell Labs 23