EE247 Lecture 19. EECS 247 Lecture 19: Data Converters 2006 H.K. Page 1. Summary Last Lecture

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1 EE247 Lecture 19 ADC Converters Sampling (continued) Clock boosters (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track & hold circuits T/H circuit incorporating gain & offset cancellation Electro-Static Discharge (ESD) protection EECS 247 Lecture 19: Data Converters 2006 H.K. Page 1 Summary Last Lecture DAC Converters (continued) DAC reconstruction filter ADC Converters Sampling Sampling network thermal noise Acquisition bandwidth limitations For example 1% accuracy T s /2>5RC Sampling switch induced distortion Sampling switch conductance dependence on input voltage Complementary switch Clock boosters EECS 247 Lecture 19: Data Converters 2006 H.K. Page 2

2 Clock Multiplier M7 & M13 for reliability Remaining issues: -V GS constant only for n <V out -Nonlinearity due to Vth dependence of M11on bodysource voltage Boosted Clock Sampling Complete Circuit Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 1999, pp Switch EECS 247 Lecture 19: Data Converters 2006 H.K. Page 3 Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IFsampling frontend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Switch EECS 247 Lecture 19: Data Converters 2006 H.K. Page 4

3 Advanced Clock Boosting Technique clk low Sampling Switch clk low Capacitors C1a & C1b charged to VDD MS off Hold mode EECS 247 Lecture 19: Data Converters 2006 H.K. Page 5 Advanced Clock Boosting Technique clk high Sampling Switch clk high Top plate of C1a & C1b connected to gate of sampling switch Bottom plate of C1a connected to V IN Bottom plate of C1b connected to V OUT VGS & VGD of MS VDD & ac signal on G of MS average of V IN & V OUT EECS 247 Lecture 19: Data Converters 2006 H.K. Page 6

4 Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IFsampling frontend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Switch Gate tracks average of input and output, reduces effect of I R drop at high frequencies Bulk also tracks signal reduced body effect (technology used allows connecting bulk to S) Reported measured SFDR = 76.5dB at f in =200MHz EECS 247 Lecture 19: Data Converters 2006 H.K. Page 7 Constant Conductance Switch Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec EECS 247 Lecture 19: Data Converters 2006 H.K. Page 8

5 Constant Conductance Switch OFF Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec EECS 247 Lecture 19: Data Converters 2006 H.K. Page 9 Constant Conductance Switch M2 Constant current constant g ds M1 replica of M2 & same VGS as M2 M1 also constant g ds ON Note: Authors report requirement of 280MHz GBW for the opamp for 12bit 50Ms/s ADC Also, opamp common-mode compliance for full input range Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec EECS 247 Lecture 19: Data Converters 2006 H.K. Page 10

6 Switch Off-Mode Feedthrough Cancellation Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Techn. Papers, pp. 314 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 11 Practical Sampling φ 1 M1 C V o R sw = f( ) distortion Switch charge injection & clock feedthrough EECS 247 Lecture 19: Data Converters 2006 H.K. Page 12

7 Sampling Switch Charge Injection & Clock Feedthrough Switching from Track to Hold V G V H V G +V th M1 V O V L V O ΔV t C s t off t First assume is a DC voltage When switch turns off offset voltage induced on C s Why? EECS 247 Lecture 19: Data Converters 2006 H.K. Page 13 Sampling Switch Charge Injection MOS xtor operating in triode region Cross section view L D Distributed channel resistance & gate & junction capacitances G C ov C ov L S C j sb B C j db D C HOLD Channel distributed RC network formed between G,S, and D Channel to substrate junction capacitance distributed & voltage dependant Drain/Source junction capacitors to substrate voltage dependant Over-lap capacitance C ov = L D xwxc ox associated with G-S & G-D overlap EECS 247 Lecture 19: Data Converters 2006 H.K. Page 14

8 Switch Charge Injection Slow Clock V H V G Device still conducting +V th V L t- t off t Slow clock clock fall time >> device speed During the period (t- to t off ) current in channel discharges channel charge into low impedance signal source Only source of error Clock feedthrough from C ov to C s EECS 247 Lecture 19: Data Converters 2006 H.K. Page 15 V G Switch Clock Feedthrough Slow Clock VG C ov D V H +V th Cov Δ V = ( Vi+ Vth VL) C + C ov s C s V L V O ΔV t Cov ( + V th V L) Cs Vo = Vi+ΔV Cov Cov Cov Vo = Vi ( Vi+ Vth VL) = Vi 1 ( Vth VL) C s C s Cs V = V ( 1+ ε ) + V o i os Cov Cov where ε = ; Vos = ( Vth VL) C C s s t- t off t EECS 247 Lecture 19: Data Converters 2006 H.K. Page 16

9 Switch Charge Injection & Clock Feedthrough Slow Clock- Example V G 10μ/0.18μ V G M1 VO V H +V th C s =1pF ' 2 ov μ ox μ th L C = 0.1fF/ C = 9fF/ V = 0.4V V = 0 V L V O ΔV t Cov 10μx0.1fF/ μ ε = = =.1% Cs 1pF Allowing ε = 1/2LSB ADC resolution < ~9bit Cov Vos = ( Vth VL) = 0.4mV C s t- t off t EECS 247 Lecture 19: Data Converters 2006 H.K. Page 17 Switch Charge Injection & Clock Feedthrough Fast Clock Q ch V G M1 VO V H V G +V th nqch n+m=1 mq ch C s =1pF V L V O ΔV t t off t Sudden gate voltage drop no gate voltage to establish current in channel channel charge has no choice but to escape out towards S & D EECS 247 Lecture 19: Data Converters 2006 H.K. Page 18

10 Switch Charge Injection & Clock Feedthrough Fast Clock Clock Fall-Time << Device Speed: V G V H Cov 1 Q Δ Vo = ( VH VL) C + C 2 C ov s s Cov 1 WCoxL( ( VH Vi Vth) ) ( VH VL) C + C 2 C Vo = Vi V = V ( 1+ ε ) + V ch ov s s o i os 1 WCoxL whereε = 2 C s V L V O +V th ΔV t Cov 1 WCoxL( VH Vth ) Vos = ( VH VL) C 2 C s s t off t For simplicity it is assumed channel charge divided equally between S & D Source of error channel charge transfer + clock feedthrough via C ov to C s EECS 247 Lecture 19: Data Converters 2006 H.K. Page 19 Switch Charge Injection & Clock Feedthrough Fast Clock- Example V G 10μ/0.18μ V G M1 VO C s =1pF V H V IN +V th V L V O ΔV t 2 ov μ ox μ th DD L C = 0.1fF / C = 9fF / V = 0.4V V = 1.8V V = 0 WLCox 10μx0.18μx9fF / μ ε = 1/2 = = 1.6% ~5 bit C 1pF s Cov 1 WCoxL( VH Vth ) Vos = ( VH VL) = 1.8mV 14.6mV = 16.4mV C 2 C s s 2 t off t EECS 247 Lecture 19: Data Converters 2006 H.K. Page 20

11 Switch Charge Injection & Clock Feedthrough Slow Clock versus Fast Clock V o V o ΔV ΔV Slow Clock Fast Clock EECS 247 Lecture 19: Data Converters 2006 H.K. Page 21 Switch Charge Injection & Clock Feedthrough Example-Summary 1.6% ε 16mV V OS.1% Clock fall time 0.4mV Clock fall time Error function of: Clock fall time Input voltage level Source impedance Sampling capacitance Switch size Clock fall/rise should be controlled not be faster (sharper) than necessary EECS 247 Lecture 19: Data Converters 2006 H.K. Page 22

12 How do we reduce the error? Reduce switch size? Switch Charge Injection Error Reduction 1Qch Δ Vo = 2Cs Cs Ts τ = RONC s = (note: = kτ ) W μcox ( VGS Vth ) 2 L Consider the figure of merit (FOM): W μcox ( VGS Vth) 1 L Cs FOM = 2 τ ΔVo Cs WCoxL( ( VH Vi Vth) ) μ FOM L 2 Reducing switch size increases τ increased distortion not a viable solution Small τ and small ΔV use minimum chanel length (mandated by technology) For a given technology τ x ΔV ~ constant EECS 247 Lecture 19: Data Converters 2006 H.K. Page 23 Sampling Switch Charge Injection & Clock Feedthrough Summary Extra charge injected onto sampling switch device turn-off Channel charge injection Clock feedthrough to C s via C ov Issues: DC offset Input dependant error voltage distortion Solutions: Complementary switch? Addition of dummy switches? Bottom-plate sampling? EECS 247 Lecture 19: Data Converters 2006 H.K. Page 24

13 Switch Charge Injection Complementary Switch φ 1 V H V G φ 1 φ 1B φ 1B V L t φ 1 φ 1B In slow clock case if area of n & p devices widths are equal (W n =W p ) effect of overlap capacitor for n & p devices to first order cancel (cancellation accuracy depends on matching of n & p width and ΔL) Since in CMOS technologies μ n ~2.5μ p choice of W n =W p not optimal from linearity perspective (W p >W n preferable) EECS 247 Lecture 19: Data Converters 2006 H.K. Page 25 Switch Charge Injection Complementary Switch Fast Clock ( ) Q = W C L V V V ch n n ox n H i th n ch p p ox p i L ( Vth p ) Q = W C L V V V G V H 1 Qch n Q ΔVo 2 Cs Cs ch p V L t Vo = Vi( 1+ ε ) + Vos 1 WC L + WC L ε 2 C n ox n p ox p s φ 1 In fast clock case To 1 st order, offset due to overlap caps cancelled for equal device width Input voltage dependant error worse! φ 1B EECS 247 Lecture 19: Data Converters 2006 H.K. Page 26

14 Switch Charge Injection Dummy Switch M1 V G V GB M2 V O C s V H V G V GB Q 1 Q 2 W M2 =1/2W M1 V L t 1 M1 M1 Q1 Qch + Qov 2 M2 M2 Q2 Qch + 2Qov 1 ForW = W Q = Q 2 M 2 M1 2 1 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 27 Switch Charge Injection Dummy Switch M1 V G V GB M2 V O C s V H V G V GB Q 1 Q 2 W M2 =1/2W M1 V L t Dummy switch same L as main switch but half W Main device clock goes low, dummy device gate goes high dummy switch acquires same amount of channel charge main switch needs to lose Effective only if exactly half of the charge transferred to M2 (depends on input/output node impedance) and requires good matching between clock fall/rise EECS 247 Lecture 19: Data Converters 2006 H.K. Page 28

15 Switch Charge Injection Dummy Switch R V G M1 V GB M2 W M2 =1/2W M1 VO C s C s To guarantee half of charge goes to each side create the same environment on both sides Add capacitor equal to sampling capacitor to the other side of the switch + add fixed resistor to emulate input resistance of following circuit Issues: Degrades sampling bandwidth EECS 247 Lecture 19: Data Converters 2006 H.K. Page 29 Dummy Switch Effectiveness Test Dummy switch W=1/2W main As Vin is increased Vc1-Vin is decreased channel charge decreased less charge injection Note large Ls good device area matching Ref: L. A. Bienstman et al, An Eight-Channel 8 13it Microprocessor Compatible NMOS D/A Converter with Programmable Scaling, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 30

16 φ + V O+ Switch Charge Injection Differential Sampling Cs V V = V V V = V o+ o od i+ i id V + V V + V Voc = = 2 2 Vo+ = Vi Vos1 V = V 1+ + V o+ o i+ i Vic ( ε ) ( ε ) ( ε + ε ) o i 2 os2 ( ε ε ) V = V + V + V + V V od id id 1 2 ic os1 os2 - Cs To 1 st order, offset terms cancel V O- Note gain error ε still about the same Has the advantage of better immunity to noise coupling and cancellation of even order harmonics EECS 247 Lecture 19: Data Converters 2006 H.K. Page 31 Switch Charge Injection Bottom Plate Sampling φ 1b φ 1a M1 V H V O Cs V L φ 1b φ 1a M2 t Switches M2 opened slightly earlier compared to M1 Injected charge by the opening of M2 is constant & eliminated when used differentially Since C s bottom plate open when M1 opened no charge injected on C s EECS 247 Lecture 19: Data Converters 2006 H.K. Page 32

17 Flip-Around Track & Hold φ 2 φ 1 S2A φ 1D φ 1D φ 2 φ 1D C φ 2 S3 v IN S1A S2 v OUT φ 1 S1 Concept based on bottomplate sampling v CM EECS 247 Lecture 19: Data Converters 2006 H.K. Page 33 Flip-Around T/H-Basic Operation φ 1 high φ 2 φ 1 S2A φ 1D φ 1D φ 2 v IN φ 1D S1A C φ 2 S2 S3 Charging C vout Q φ1 =V IN xc φ 1 S1 v CM Note: Opamp has to be stable in unity-gain configuration EECS 247 Lecture 19: Data Converters 2006 H.K. Page 34

18 Flip-Around T/H-Basic Operation φ 2 high φ 2 φ 1 S2A φ 1D φ 1D φ 2 φ 1D C φ 2 S3 Holding v IN S1A S2 v OUT φ 1 S1 Q φ2 =V OUT xc V OUT =V IN v CM EECS 247 Lecture 19: Data Converters 2006 H.K. Page 35 Flip-Around T/H - Timing φ 2 S2A φ 1D φ 1 φ 1D v IN φ 1D C φ 2 S3 φ 2 S1A S2 vout φ 1 S1 v CM S1 opens earlier than S1A No resistive path from C bottom plate to Gnd charge can not change "Bottom Plate Sampling" EECS 247 Lecture 19: Data Converters 2006 H.K. Page 36

19 Charge Injection At the instant of transitioning from track to hold mode, some of the charge stored in sampling switch S1 is dumped onto C With "Bottom Plate Sampling", only charge injection component due to opening of S1 and is to first-order independent of v IN Only a dc offset is added This dc offset can be removed with a differential architecture EECS 247 Lecture 19: Data Converters 2006 H.K. Page 37 Flip-Around T/H Constant switch V GS to minimize distortion φ 2 φ 1 S2A φ 1D φ 1D φ 2 v IN φ 1D S1A C φ 2 S2 S3 v OUT φ 1 S1 v CM Note: Among all switches only S1A & S2A experience full input voltage swing EECS 247 Lecture 19: Data Converters 2006 H.K. Page 38

20 Flip-Around T/H S1 is chosen to be an n-channel MOSFET Since it always switches the same voltage, it s onresistance, R S1, is signal-independent (to first order) Choosing R S1 >> R S1A minimizes the non-linear component of R = R S1A + R S1 S1A is a wide (much lower resistance than S1) & constant V GS switch In practice size of S1A is limited by the (nonlinear) S/D capacitance that also adds distortion If S1A s resistance is negligible delay depends only on S1 resistance S1 resistance is independent of V IN error due to finite time-constant independent of V IN EECS 247 Lecture 19: Data Converters 2006 H.K. Page 39 Differential Flip-Around T/H S11 S12 Ref: Offset voltage associated with charge injection of S11 & S12 cancelled by differential nature of the circuit During input sampling phase amp outputs shorted together W. Yang, et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER EECS 247 Lecture 19: Data Converters 2006 H.K. Page 40

21 Differential Flip-Around T/H Gain=1 Feedback factor=1 φ 1 φ 1 φ2 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 41 Differential Flip-Around T/H Issues: Input Common-Mode Range Δn-cm =V out_com -V sig_com Amplifier needs to have large input common-mode compliance EECS 247 Lecture 19: Data Converters 2006 H.K. Page 42

22 Differential Flip-Around T/H Choice of Sampling Switch Size THD simulated w/o sampling switch boosted clock -45dB THD simulated with sampling switch boosted clock (see figure) Ref: K. Vleugels et al, A 2.5-V Sigma Delta Modulator for Broadband Communications Applications IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001, pp EECS 247 Lecture 19: Data Converters 2006 H.K. Page 43 Input Common-Mode Cancellation Shorting switches M4, M5 added Ref: R. Yen, et al. A MOS Switched-Capacitor Instrumentation Amplifier, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER EECS 247 Lecture 19: Data Converters 2006 H.K. Page 44

23 Input Common-Mode Cancellation Track mode (φ high) V C1 =V I1, V C2 =V I2 V o1 =V o2 =0 Hold mode (φ low) V o1 +V o2 =0 V o1 -V o2 = -(V I1 -V I2 )(C 1 /(C 1 +C 3 )) Input common-mode level removed EECS 247 Lecture 19: Data Converters 2006 H.K. Page 45 T/H + Charge Redistribution Amplifier Track mode: (S1, S3 on S2 off) V C1 =V os V IN, V C2 =0 V o =V os EECS 247 Lecture 19: Data Converters 2006 H.K. Page 46

24 T/H + Charge Redistribution Amplifier Hold Mode 2 1 Hold/amplify mode (S1, S3 off S2 on) Offset NOT cancelled, but not amplified Input-referred offset =(C 2 /C 1 ) x V OS, & C 2 <C 1 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 47 T/H & Input Difference Amplifier Sample mode (S1, S3 on S2 off) V C1 =V os V I1, V C2 =0 V o =V os EECS 247 Lecture 19: Data Converters 2006 H.K. Page 48

25 Input Difference Amplifier Cont d Subtract/Amplify mode (S1, S3 off S2 on) During previous phase: V C1 =V os V I1, V C2 =0 V o =V os 1 Offset NOT cancelled, but not amplified Input-referred offset =(C 2 /C 1 )xv OS, & C 2 <C 1 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 49 T/H & Summing Amplifier EECS 247 Lecture 19: Data Converters 2006 H.K. Page 50

26 T/H & Summing Amplifier Cont d Sample mode (S1, S3, S5 on S2, S4 off) V C1 =V os V I1, V C2 =V os -V I3, V C3 =0 V o =V os EECS 247 Lecture 19: Data Converters 2006 H.K. Page 51 T/H & Summing Amplifier Cont d Amplify mode (S1, S3, S5 off, S2, S4 on) 3 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 52

27 Differential T/H Combined with Gain Stage Employs the previously discussed technique to eliminate the problem associated with high common-mode voltage excursion at the input of the opamp Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 53 Differential T/H Combined with Gain Stage φ1 High Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 54

28 Differential T/H Combined with Gain Stage Gain=4C/C=4 Input voltage common-mode level removed opamp can have low CMRR Amplifier offset NOT removed Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecture 19: Data Converters 2006 H.K. Page 55 Differential T/H Including Offset Cancellation Operation during offset cancellation phase shown Auxilary inputs added with A main /A aux.=10 During offset cancellation phase: Aux. amp configured in unity-gain mode: Vout=V os main offset stored on C AZ & canceled Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp , December EECS 247 Lecture 19: Data Converters 2006 H.K. Page 56

29 Differential T/H Including Offset Cancellation Operational Amplifier Operational amplifier dual input folded-cascode opamp M3,4 auxiliary input, M1,2 main input To achieve 1/10 gain ratio W M3, 4 =1/10x W M1,2 & current sources are scaled by 1/10 M5,6,7 common-mode control Output stage dual cascode high DC gain V out =g m1 r o n1 + g m2 r o n2 Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp , December EECS 247 Lecture 19: Data Converters 2006 H.K. Page 57 Differential T/H Including Offset Cancellation Phase + - (V INAZ+ -V INAZ- )= -g m1 /g m2 V offset V offset During offset cancellation phase AZ and S1 closed main amplifier offset amplified by g m1 /g m2 & stored on C AZ Auxiliary amp chosen to have lower gain so that: Aux. amp offset & charge injection associated with opening of switch AZ reduced by A aux /A main =1/10 Low increase in power dissipation resulting from addition of aux. inputs Requires an extra auto-zero clock phase EECS 247 Lecture 19: Data Converters 2006 H.K. Page 58

30 ESD Protection ADC Architectures EECS 247 Lecture 19: Data Converters 2006 H.K. Page 59 What is ESD? Electrostatic discharge Example: Charge built up on human body while walking on carpet... Charged objects near or touching IC pins can discharge through on-chip devices Without dedicated protection circuitry, ESD events could be destructive EECS 247 Lecture 19: Data Converters 2006 H.K. Page 60

31 Model and Protection Circuit [ [ EECS 247 Lecture 19: Data Converters 2006 H.K. Page 61 Equivalent Circuit Nonlinear capacitance causes distortion Distortion increases with frequency Today's converters: High frequency, low distortion! Ref: I. E. Opris, "Bootstrapped pad protection structure," IEEE J.Solid-State Circuits, pp. 300, Feb EECS 247 Lecture 19: Data Converters 2006 H.K. Page 62

32 ESD Circuit Distortion Ref: I. E. Opris, "Bootstrapped pad protection structure," IEEE J.Solid-State Circuits, pp. 300, Feb C(n )= 2...4pF for n =2...0V EECS 247 Lecture 19: Data Converters 2006 H.K. Page 63 ESD Circuit Distortion Analysis: Volterra Series Or SPICE simulations Example: v i v o R=25Ω R C j C L C jo =1pF C L =5pF peak =0.5V EECS 247 Lecture 19: Data Converters 2006 H.K. Page 64

33 ESD Circuit Distortion 2nd Order Harmonic Distortion [dbc] Input Frequency 3rd Order Harmonic Distortion [dbc] Input Frequency H D3 (@ 37.5MHz) = -92dB H D3 (@ 100MHz) = -84dB EECS 247 Lecture 19: Data Converters 2006 H.K. Page 65 ESD Circuit Distortion Distortion from ESD circuits approaches state of-the-art ADC performance! If you are working on a new, record breaking ADC, better think about ESD now... Ref.: A. Wang, "Recent developments in ESD protection for RF IC," Proc. DAC Conference, Jan Solutions still pre-mature Lots of company intellectual property! (IP) EECS 247 Lecture 19: Data Converters 2006 H.K. Page 66

34 ADC Architectures Slope Converters Successive approximation Flash Folding Time-interleaved / parallel converter Residue type ADCs Two-step Pipeline Algorithmic Oversampled ADCs EECS 247 Lecture 19: Data Converters 2006 H.K. Page 67 Single Slope ADC Ramp Generator V Ramp V IN stop start Counter "0" Clock V Ramp Low complexity Hard to generate precise ramp Better: Dual Slope, Multi-Slope Time EECS 247 Lecture 19: Data Converters 2006 H.K. Page 68

35 Dual Slope ADC Integrate n for fixed time, de-integrate with V ref applied T De-Int ~ n /V ref Insensitive to most linear error sources EECS 247 Lecture 19: Data Converters 2006 H.K. Page 69 Successive Approximation ADC Reset DAC V REF DAC Control Logic V IN 1 MSB Y Set DAC[MSB]=1 V IN >V DAC? N Set DAC[MSB-1]=1 0 MSB Clock 1 [MSB-1] Y V IN >V DAC? N 0 [MSB-1]. 1 [LSB] Y V IN >V DAC? N 0 [LSB] Binary search over DAC output DAC[Input]= ADC[Output] EECS 247 Lecture 19: Data Converters 2006 H.K. Page 70

36 Successive Approximation ADC Example: 6-bit ADC & V IN =5/8V REF V DAC /V REF V REF DAC Control Logic V IN 1 3/4 5/8 1/2 1/2 3/4 5/8 11/16 21/32 41/64 V IN Clock Time / Clock Ticks ADC High accuracy achievable (16+ Bits) Moderate speed proportional to B (MHz range) EECS 247 Lecture 19: Data Converters 2006 H.K. Page 71

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