Solid-State Electronics

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1 Solid-State Electronics 53 (29) Contents lists available at ScienceDirect Solid-State Electronics journal homepage: Drain bias dependent bias temperature stress instability in a-si:h TFT Z. Tang a, M.S. Park b, S.H. Jin b, C.R. Wie a, * a Department of Electrical Engineering, University at Buffalo, The State University of New York, Buffalo, NY 1426, USA b LCD R&D Center, Samsung Electronics Co., Ltd., Giheung-Gu, Yongin-City, Gyeonggi-Do, Republic of Korea article info abstract Article history: Received 16 September 28 Accepted 23 November 28 Available online 6 January 29 The review of this paper was arranged by Dr. Y. Kuk Keywords: a-si:h Thin film transistor Bias temperature stress Threshold voltage shift The threshold voltage (V t ) instability of hydrogenated amorphous silicon (a-si:h) thin film transistors (TFTs) is investigated under drain bias dependent bias temperature stress (V D -BTS). The drain bias reduces the overall gate overdrive stress and leads to a position-dependent V t -shift (DV t ) with maximum DV t at the source-end and minimum DV t at the drain-side of channel. Measured DV t was compared with the calculated DV t using a weighted average of local V t -shift. The calculated DV t based on weighted average agreed better with the measured data in U-type samples, but a simple linear average over the channel agreed better with the measured data in an I-type sample. This is explained in terms of the fact that the source-side channel width is larger than the drain-side width in a U-type sample which results in more contribution from the source-side to the normalized DV t. A non-uniform V t profile due to V D -BTS resulted in a higher drain current in the forward measurement (source/drain are the same as in stress) than in reverse measurement (source/drain are interchanged from stress). This also leads to a different extracted V t in forward and reverse configurations due to the non-uniform V t profile along the channel. V t extracted from the saturation transfer curve varies significantly in different current ranges due to the gate bias dependence of field-effect mobility caused by a large variation of the overdrive voltage along the channel. Ó 28 Elsevier Ltd. All rights reserved. 1. Introduction Hydrogenated amorphous silicon thin film transistors (a-si:h TFTs) have become an attractive candidate for backplane technology in active matrix organic light emitting diode (AMOLED) due to the low cost, large size and good uniformity manufacturing compared to its counterpart, low temperature poly-silicon (LTPS) TFTs [1,2]. In the conventional applications as a switch element in active matrix liquid crystal display (AMLCD), a-si:h TFTs provide a voltage driving capability and operate under a pulsed linear-mode stress. The instability in threshold voltage of a-si:h TFTs has been extensively studied [3 9]. Most studies were made under a gate bias (V GS ) stress only because the effect of drain bias stress on V t instability is deemed not important in AMLCD application. However, the drain bias stress on the a-si:h TFTs is important in analog applications and where a-si:h TFTs operate as current driving pixels such as in AMOLED and are under a saturation-mode stress where the drain bias (V DS ) equals, or is greater than, the gate bias to provide a constant current to OLED [1,2]. It is thus important to understand and accurately model the effects of drain bias stress in the V t -shift (DV t ) in such applications as AMOLED. Recently, several papers appeared concerning the V t instability under drain bias dependent bias temperature stress (V D -BTS) * Corresponding author. Tel.: ; fax: address: wie@buffalo.edu (C.R. Wie). [1 13]. It was earlier reported that DV t was approximately independent of V DS in room temperature bias stress experiments [6]. The authors assumed that the measured DV t is given approximately as the maximum value of DV t in the channel. Goh et al. reported in a room temperature bias stress experiment that DV t decreased with increasing V DS, which the authors ascribed to the reduced total gate bias stress [1]. This reduction of DV t with the increasing V DS was calculated as a total V GS stress reduced by 1/3 of V DS when both gate and drain biases are applied. More recently, Karim et al. reported a decreasing DV t with increasing V DS in a linear-mode stress (where V DS is less than the saturation drain voltage, V Dsat ) and a constant DV t in a saturation-mode stress (V DS equals or greater than V Dsat ) [11]. They interpreted this drain bias dependent DV t as being controlled by the total gate charge during stress. This interpretation was consistent with the defect pool model as, for example, the amount of deep states created is proportional to the mobile electron density in the channel [5]. The effect of geometrical factors such as channel length [12] and asymmetric source and drain structure [13] under V D -BTS at room temperature was also reported. A reduction in the normalized channel charge explained the reduced DV t in short channel (L <1lm) or asymmetric a-si:h TFTs, which had a larger channel width at drain, compared with the DV t in longer channel, or symmetric a-si:h TFTs. Defect state creation and charge trapping are the two well-known mechanisms for the V t -shift in a-si:h TFTs under BTS /$ - see front matter Ó 28 Elsevier Ltd. All rights reserved. doi:1.116/j.sse

2 226 Z. Tang et al. / Solid-State Electronics 53 (29) [3 5,7,8]. Defect state creation is dominant when the gate bias is low. If the gate bias is higher than some critical value (e.g. 5 V), the charge trapping in gate dielectric becomes the dominant mechanism for V t -shift. Since a-si:h TFTs operate in a moderate gate voltage range in AMLCD and AMOLED applications, defect state creation is usually the dominant mechanism of V t -shift in these applications. In the state creation model developed by Powell and co-workers [5], DV t is proportional to the gate overdrive bias and shows a so-called stretched exponential time dependence: " DV t ¼ðV GS V t Þ 1 exp t!# b : ð1þ t where V t is the initial threshold voltage before stress, V GS V t is the initial gate overdrive stress, and t and b are temperaturedependent parameters. More recently, for a-si:h TFTs subjected to a constant current BTS, a model based on an improved defect creation kinetics showed a power-law dependence on the gate overdrive stress [14]. For samples subjected to V D -BTS, a non-uniform gate overdrive stress in the channel will induce a position-dependent electron charge density Q ch (y) according to Q ch (y)=c G V ov (y)=c G (V GS V t V(y)), where C G is the gate capacitance and V(y) is the channel potential at position y in the channel. Q ch (y) leads to a positiondependent threshold voltage shift, DV t (y). The total gate charge, Q G, may be found by integrating the channel electron charge Q ch (y) from source (y = ) to drain (y = L). For V D -BTS, the position-dependent threshold voltage shift, DV t (y), may be found from the BTS data, i.e., DV t as a function of V GS V t at zero V DS, by replacing the gate overdrive stress with a corresponding local overdrive stress V ov (y)=v GS V t V(y). In this paper, we calculate a weighted average of stress induced DV t (y), inversely weighted by local carrier density and also a simple linear average of DV t (y) along the channel and compare the calculated results with the experimental V t -shift data in U-type and I-type a-si:h TFT after V D -BTS. We also provide a qualitative discussion on how this non-uniformity of V t may affect the experimentally extracted V t from a linear or saturation-mode transfer characteristic. We examine the channel non-uniformity under V D -BTS by measuring triode and saturation-mode transfer characteristics in different source-drain configurations. The conventional V t extraction methods from triode and saturation-mode transfer characteristic are evaluated. The non-uniform V t (y) profile does not seem to affect the extracted V t for the triode-mode transfer characteristics. However it causes a variation in V t extracted from saturation-mode transfer characteristics. 2. Experiment Fig. 1 shows the I-type (the widths of source and drain are the same) and U-type (the width of source is larger than the width of drain) a-si:h TFTs used in the experiments, with both types having inverted staggered structure. The top view of I-type and U-type samples are also shown in the figure. The gate insulator silicon nitride (SiN x ) had a thickness of 43 nm and 4 nm in the I-type and U-type samples, respectively. The gate metal consisted of Mo/Al. All metal layers were sputter deposited, and all dielectric layers are PECVD deposited. The dimensions (W/L) of I-type and U-type samples are 4 lm/2 lm and 4 lm/5.5 lm, respectively. The BTS experiments were conducted in an oven with the devices on a glass substrate wire-bonded in a DIP package. Experiments for non-wire-bonded devices were conducted on a Hotchuck mounted on a Probestation which was enclosed within an EMI-shielded dark box. The I V characteristics were measured using HP4145B semiconductor parameter analyzer while the sample was still inside Fig. 1. (a) Schematic of a-si:h TFT in cross-section view, (b) I-type and U-type samples in top view. the oven or on the Hotchuck, both maintained at the same temperature as in stress. Before each stress experiment, samples were annealed at 18 C for 2 h. This restored the original threshold voltage to within 5%. The BTS experiments were first completed for a constant V GS stress bias ranging from 2 V up to 3 V, with drain and source terminals connected to the ground. The V D -BTS experiments were subsequently conducted on the same sample, applying a constant gate bias of 2 V and a various drain bias from V to 2 V, with its source terminal connected to the ground. Both BTS and V D -BTS experiments, as well as the I V measurements, were conducted in an oven with the sample maintained at 1 C. The V D -BTS included linear-mode stress at V DS < 2 V and the saturation-mode stress at V DS = 2 V. The triode-mode transfer characteristics at a drain bias of.1 V were periodically measured during the stress with the V gs bias sweeping from 2 V to +2 V at a.5 V step. Experimental V t was obtained by linear extrapolation of the I d V gs plot for a linear-mode transfer characteristic as shown in Fig. 2a or by extrapolating the I d Vgs plot for the saturation-mode transfer characteristics, as shown in Fig. 2b. DV t was found by subtracting V t, which was measured immediately before each stress experiment, from the measured V t after the stress as DV t = V t V t. Each intermittent transfer characteristic measurement took about 4 5 s. We evaluated how these transfer characteristic measurements affect the device characteristics before and after stress. For an I-type virgin sample, after two consecutive triode-mode mea-

3 Z. Tang et al. / Solid-State Electronics 53 (29) biases of 6 V, 13 V and 2 V, respectively, with V ds sweeping from V to 3 V. The output characteristic measurement at each gate bias took about 2 3 s and may be considered as a 2 3 s BTS stress. Therefore, the output characteristics were measured only after transfer characteristics were measured before and after stress. It should be noted that the extracted V t from saturation-mode transfer characteristic examines the channel up to the pinch-off point. A comparison of the extracted V t from the linear and saturation transfer characteristics in different source and drain configurations is discussed in the latter part of this paper. 3. Results, analysis and discussion 3.1. BTS and V D -BTS results Fig. 3a shows DV t data of BTS for a U-type sample as a function of the gate overdrive stress, V GS V t, along with two different fits. The DV t was extracted from a V ds =.1 V triode-mode transfer characteristics. V t was 1.5 V as obtained before the stress. The first fit is a linear dependence, DV t ¼ BðV GS V t ÞþC ð2þ where B =.422 and C = were obtained from fitting. In the U-type sample, the dependence of DV t on the gate overdrive stress was fairly linear for V GS near 1 V or higher; while the DV t deviated significantly from this linear dependence if the V GS is lower than Fig. 2. Illustration of V t extraction from (a) triode-mode transfer characteristic measurement (V ds =.1 V) and (b) saturation-mode transfer characteristic measurement (V ds = 3 V). DV t is calculated as (V t V t ), where V t is after stress value and V t is initial value before stress. surements, the measured V t in the second measurement was about.1 V less than in the first measurement. This is negligible compared to the measured V t. After a bias stress, however, the decrease in V t in the second measurement from the value found in the first measurement was significant. For example, after 15 s of 2 V BTS stress at 1 C, the measured V t from the second measurement was about.4 V less than in the first measurement. After a 15-s stress, if transfer characteristics were measured repeatedly up to seven times, the measured V t decreased by about 1.3 V and the incremental reduction in V t after each successive measurements decreased. We repeated the same stress and measurements at 5 C and found that the measured V t decreased by only about.3 V in a second measurement from the first measurement, with a total reduction of only.8 V after seven consecutive measurements. Therefore, this V t reduction after each transfer characteristic measurement at 1 C seems to be mainly due to a thermal annealing effect of the sample held at 1 C during the 4 5 s of each transfer characteristics measurement. The annealing effect at 5 C was negligible compared with the 1 C annealing. The channel non-uniformity under V D -BTS was investigated by measuring the saturation-mode transfer characteristics and the output characteristics both in forward configuration (source and drain are same as during stress) and in reverse configuration (source and drain are reversed after stress) for an I-type sample. The saturation-mode transfer characteristic was measured at a drain bias of 3 V. The output characteristic was measured at gate Fig. 3. DV t extracted from triode-mode transfer characteristics (V ds =.1 V) as a function of gate stress bias after 15 s stress at 1 C in BTS experiments in (a) U- type TFT (W =4lm, L = 5.5 lm) and (b) I-type TFT (W = 4 lm, L =2lm). Two different fits are plotted based on linear and power-law relation.

4 228 Z. Tang et al. / Solid-State Electronics 53 (29) about 8 1 V. The DV t data of an I-type sample under similar BTS stress condition is plotted in Fig. 3b with V t = 2.3 V. The linear dependence of DV t on the gate overdrive stress is visible for V GS greater than 6 V with B =.328 and C =.48 as obtained from fitting. The BTS DV t data was fitted with a power-law formula for DV t relative to V GS V t DV t ¼ AðV GS V t Þ a where A and a are fitting parameters with values A =.17 and a = 1.26 for the U-type sample and A =.233 and a = 1.9 for the I-type sample, respectively. This formula fits the BTS data better than the linear formula Eq. (2), especially in the lower gate overdrive stress range. The power-law formula for DV t was suggested in the case of a constant current stress BTS [14,15]. In our BTS experiments, however, we used a constant voltage stress. When the gate and drain biases are applied simultaneously in the V D -BTS stress, V DS produces channel potential and leads to a non-uniform, position-dependent gate overdrive stress. The initial gate overdrive stress, V ov (y), equals (V GS V t V(y)) where V(y) is the local channel potential at position y during the bias temperature stress. In the defect creation model [5], the DV t is proportional to the concentration of defects created in the channel and the defect concentration created by BTS is proportional to [5], or has a power-law dependence on [14], the carrier concentration (i.e., the occupancy of the band tail states). The local carrier charge density, Q str (y), produced by the stress bias is given as Q str (y)=c G V o- v(y). Therefore, after V D -BTS, the device channel is expected to have a non-uniform threshold voltage V t (y). The V t -shift of device is then given by an average of the local V t - shift over the channel potential V meas of measurement: hdv t i¼ 1 V ds Z Vds DV t ðyþdv meas ðyþ where V meas (y) is the channel potential at y at a measurement drain bias V ds, and hdv t i refers to the average of V t -shift. In the Gradual- Channel Approximation, the drain current, I d, is given as I d ¼ Wl dv meas Q dy meas ðyþ where Q meas (y) is the local charge density of carriers at position y and is given by C G (V gs V t DV t (y) V(y)). Substituting Eq. (5) into Eq. (4), the average DV t becomes I d hdv t i¼ WlV ds DV t ðyþ Q meas ðyþ dy Eq. (6) indicates that the device DV t is a weighted average of the local DV t (y), inversely weighted by the local carrier density in the channel. The region with a higher DV t (y) is weighted down comparatively less than the region with a lower DV t (y) if channel potential is negligible. For a triode-mode transfer characteristic at a low V ds, e.g.,.1 V, we can make the following two approximations: Q meas ðyþ ¼C G ðv gs V t DV t ðyþ VðyÞÞ ffi C G ðv gs V t DV t ðyþþ I d ¼ W L lc G ðv gs V t hdv t iþv ds 1 2 V 2 ds ffi W L lc GV ds ðv gs V t hdv t iþ by neglecting the channel potential and thus obtaining a linear I V characteristic. From Eqs. (6) (8), we obtain the average DV t as ð3þ ð4þ ð5þ ð6þ ð7þ ð8þ I d hdv t i¼ WlV ds ffi 1 L DV t ðyþ Q meas ðyþ dy DV t ðyþdy þ 1 L DV t ðyþ DV tðyþ hdv t i V gst DV t ðyþ dy where V gst = V gs V t. The first integral on the right hand side is a simple linear average of DV t (y) over the length of channel and is independent of gate bias. The second integral provides a correction to the average DV t and is dependent on the gate bias during measurement. Note that during the transfer characteristics measurement, V gs varies and V ds is kept constant. Therefore, the second integral will yield a correction to hdv t i that depends on V gs. Note here that we use upper-case subscripts for the stress biases (V GS, V DS ), and the lower-case subscripts for the measurement biases (V gs, V ds ). If the second integral in Eq. (9) may be ignored, Eq. (9) is further approximated as hdv t iffi 1 L DV t ðyþdy ð9þ ð1þ This indicates that a triode-mode transfer characteristic may be approximately a simple linear average of the non-uniform DV t (y) along the channel. Note that the above approximation of Eq. (1) may be a rather gross approximation because the non-uniform V t implies a non-uniform carrier concentration, and thus the electric field dv meas /dy is not constant through the channel. However, even with this limitation, Eq. (1) agreed well with some experimental data. Note also that in a saturation-mode transfer characteristic, the channel potential V meas (y) is more involved, particularly in a sample with non-uniform channel, and thus this case requires a more careful analysis. After V D -BTS, DV t from triode-mode transfer characteristic can be evaluated analytically with Eq. (1) as follows: in the BTS (with zero V DS ), we assume that the local threshold voltage shift at y, DV t (y), is proportional to the initial, local carrier concentration, Q str (y)=c G V ov (y), or equivalently, to the initial gate overdrive stress, V ov (y)=v GS V t V(y), where V(y) has the boundary condition, V() = and V(L)=V DS assuming that we can neglect the voltage drops between source and channel and between drain and channel in the inverted staggered gate structure of the TFT (see Fig. 1). We also assume that the effect of drain bias V DS is simply to reduce the local, gate overdrive stress in the channel, and the local DV t (y) is assumed to follow the same functional dependence as in BTS for the same overdrive stress, Eq. (2) or Eq. (3). The DV t due to V D -BTS, Eq. (1), is then calculated using Eq. (2) or Eq. (3) after replacing V GS by V GS V(y) to yield hdv t iffi Wl Z V DS DV t ðvþq LI str ðvþdv ð11þ D where I D is the drain current during stress, and Q str (V)=C G (V GS V t V) is the local channel charge during the V D -BTS stress. Using the linear fit to the BTS data, Eq. (2), in Eq. (11), a triode-mode V D -BTS yields DV t ¼ 2 3 B ðv GS V t Þ 3 ðv GD V t Þ 3 ðv GS V t Þ 2 ðv GD V t Þ 2 þ C Similarly, a saturation-mode V D -BTS stress yields DV t ¼ 2 3 BðV GS V t ÞþC ð12tþ ð12sþ For C =, the above results, Eq. (12T) and (12S), reduce to the equations in Ref. [11] in which the authors used the drain bias dependent total gate charge formulas from Ref. [16]. Using the power-law fit to the BTS data, Eq. (3), a triode-mode V D -BTS stress yields

5 Z. Tang et al. / Solid-State Electronics 53 (29) DV t ¼ 2 2 þ a A ðv GS V t Þ 2þa ðv GD V t Þ 2þa ðv GS V t Þ 2 ðv GD V t Þ 2 Corresponding saturation-mode stress yields ð13tþ DV t ¼ 2 2 þ a AðV GS V t Þ a ð13sþ Here again, a = 1 reduces Eqs. (13T) and (13S) to the total gate charge formula of Ref. [11]. For both triode and saturation-mode stress, Eqs. (12T) and (12S) result in almost the same DV t, indicating that the higher overdrive stress (i.e., in Fig. 3, V GS V t greater than 7.5 V for U-type and 5 V for I-type) dominates the V D -BTS result and therefore, the linear fit (Eq. (2)) and the power-law fit (Eq. (3) produce no distinguishable difference. Fig. 4a shows the experimental DV t (open square) of the U-type sample as a function of the stress bias V DS at a constant V GS of 2 V after a 15-s stress at 1 C. Also plotted are the calculated DV t based on Eq. (12T) and on Eq. (9) with various values of V gs, The experimental DV t was extracted from a linear-mode transfer characteristic at V ds of.1 V. The data shows an initially decreasing DV t with the increasing stress V DS and a saturated DV t at higher stress V DS. For up to about 8 1 V of stress V DS, the triode-mode stress formula, Eq. (12T), agrees reasonably well with the experimental data, indicating that the stress V DS simply reduces the gate overdrive stress. At a higher V DS, the saturation-mode stress formula, Eq. (12S), gives a lower DV t than the measured DV t by about V. The experimental data seems to indicate that the sample entered into saturation at a drain bias of about 8 1 V. This V DS value is significantly lower than the saturation drain voltage V Dsat expected in the unstressed sample, V GS V t = 19 V, or the V Dsat value for V t extracted after the V D -BTS stress, V GS V t = = It is even lower than the V Dsat value based on the maximum V t in the channel [6], which equals the V t after BTS: V GS V t,max =2 7.8 = 12.2 V. As Fig. 4 shows, Eq. (9) gives the average DV t dependent on V gs. A smaller V gs gives a higher positive correction to the average DV t according to the second integral in Eq. (9). For a triode-mode stress of a U-type sample (see Fig. 4a), Eqs. (9) and (12T) and Ref. [11] all agree reasonably well with the experimental data while Ref. [1] slightly overestimates the average DV t. In the saturation-mode stress, only Eq. (9) for V gs = 1 V yields a reasonably good agreement with the experimental data and all other calculations significantly underestimate the experimental data. For the I-type sample (see Fig. 4b), the experimental data after V D -BTS again shows a lower apparent saturation drain bias of V than in the unstressed sample of V GS V t = 17.7 V. But this saturation drain bias value is consistent with the extracted V t after V D -BTS stress, V GS V t =2 5.8 = 14.2 V, which tends to make the correctionterm (the second integral in Eq. (9)) very small. Therefore, unlike the U-type sample, the simple linear average of DV t of Eq. (12T) agrees well with the experimental data in both the linear and saturation-mode stress. This could be explained by the fact that the U- type sample has a larger width at the source than at the drain as shown in Fig. 1b. As was pointed out earlier, a higher DV t (y) occurs near the source by the V D -BTS stress and therefore, the larger source width of U-type sample will give a higher normalized V t - shift than in the I-type sample which has the same source and drain width. In other words, Eq. (6) will yield a higher hdv t i for the U-type because of its asymmetric and wider source width over drain width compared with the symmetric I-type sample. The experimental hdv t i after a saturation-mode stress is about 5.3 V in the U-type sample and 3.5 V in the I-type sample as Fig. 4 shows. Therefore, a simple linear average of DV t (y) of Eq. (1) will underestimate the DV t in the U-type sample after a saturation-mode V D - BTS. Our explanation is also consistent with the result by Shin et al. [13] in which DV t of an asymmetric TFT (similar to our U-type structure) with a larger drain width was less than the DV t of a symmetric TFT (I-type) when subjected to the same V D -BTS stress. If the source width is smaller than the drain width in an asymmetric TFT, a smaller hdv t i will result than in a symmetric TFT. We also have analyzed the DV t extracted from forward and reverse transfer characteristics where the forward measurement has the same source and drain electrodes as in stress and the reverse measurement has the source and drain electrodes interchanged from stress. The results are discussed next. Two observations are relevant to the above discussion: the forward and reverse I V data show a clear evidence of non-uniform V t distribution in the channel and its effect on the measured V t Dependence of the experimental DV t on measurement configuration Fig. 4. Measured DV t (open square) of (a) U-type TFT and (b) I-type TFT extracted from triode-mode transfer characteristics (V ds =.1 V) as a function of stress drain bias after 15 s stress at 1 C inv D -BTS experiments with constant V G =2V along with various calculation results (solid line: simple linear average calculation (Eq. (12)); dashed line: Eq. (9) at V gs = 1 V; dot line: Eq. (9) at V gs = 1 V; dash dot line: Ref. [11]; dash dot dot line: Ref. [1]). Unlike in the triode-mode transfer characteristics, V t extracted from a saturation-mode transfer characteristic is more involved. In this section, we present and discuss the measured V t from the saturation-mode transfer characteristics. As was discussed earlier, if the V gs -dependent second integral in Eq. (9) is negligible compared with the first term, then the triode-mode transfer characteristic yields the average device DV t as a simple linear average of non-uniform DV t (y) over the length of channel, as given by Eqs. (12T) and (12S). However, Eq. (4) does not lead to a simple analytical expression for DV t from a saturation-mode transfer character-

6 23 Z. Tang et al. / Solid-State Electronics 53 (29) istic. We therefore discuss only the experimental data, qualitatively. The I-type sample was used to extract V t from triode and saturation-mode transfer characteristics in both forward and reverse configurations. Symmetry of source and drain structure of the I-type TFT allows comparison between the forward and reverse I V data while the asymmetric U-type TFT does not permit a straightforward comparison. Therefore we discuss only the I-type data. Fig. 5 shows the forward and reverse output characteristics at V gs = 2 V before and after a 15-s BTS (V GS = 2 V, 1 C) and after a saturation-mode V D -BTS (V DS =3V,V GS = 2 V, 1 C) on a wire-boned I-type sample with W/L = 4 lm /2 lm. The forward characteristic was measured first and then the reverse characteristic was measured. Fig. 5a shows that after BTS, the forward and reverse output characteristics are identical to each other whether before or after BTS, as expected because the channel has a uniform V t. Fig. 5b shows that the forward current is higher than the reverse current after a saturation-mode V D -BTS. After the V D - BTS, the local V t (y) decreases from source toward drain. This indicates a lower effective V t for the forward configuration than for the reverse configuration. This may be understood qualitatively as follows: In the forward case, the local overdrive bias is high in sourceside (where the local DV t is high) and low in the drain-side (where the local DV t is low). In the reverse case, the opposite situation is true with a high local overdrive voltage where DV t is low (i.e., the source-side of reverse measurement) and a low local overdrive voltage where the local DV t is high (i.e., the drain-side of reverse measurement). Therefore, the high DV t region is weighted down comparatively more according to Eq. (6) and thus the effective V t will be lower in forward than in reverse characteristic. Our result is in contrast with Ref. [17] which reports a higher reverse current than forward current. They argue that in the forward saturationmode, the defect region is fully inside the channel and the defect-free region (i.e., the pinch-off region of bias stress) lies in the pinch-off region and does not contribute to the current process, whereas in the reverse measurement, part of the defect region lies in the pinch-off region and the defect-free region is inside the channel and consequently the forward configuration has a lower saturation current than the reverse configuration. However, according to Eq. (6), a higher forward saturation current can result because of the fact that the high V t is weighed down by a high local overdrive bias in the forward configuration. Saturation-mode transfer characteristics were measured after BTS stress and after saturation-mode V D -BTS. Fig. 6 shows the forward and reverse transfer characteristics with the drain bias at 3 V before and after 15 s stress with the forward data measured before the reverse data. The forward transfer curves are in solid symbols and the reverse characteristics are in open symbols. For BTS (Fig. 6a), the forward and reverse transfer characteristics are identical before stress and nearly identical after 15 s stress. The slightly increased current level in the reverse characteristic after the 15 s BTS is due to a small thermal annealing during Fig. 5. Output characteristics at V gs = 2 V before stress and after 15 s stress in forward and reverse source drain configurations. The stress conditions are (a) BTS (V GS = 2 V) and (b) V D -BTS (V DS =3V,V GS = 2 V, 1 C). Solid box: before stress in forward configuration; solid circle: after 15 s stress in forward configuration; open box: before stress in reverse configuration; open circle: after 15 s stress in reverse configuration. Fig. 6. Transfer characteristics of saturation measurement (V ds = 3 V) before stress and after 15 s stress in forward and reverse source drain configurations. The stress conditions are (a) BTS (V GS = 2 V, 1 C) and (b) V D -BTS (V DS =3V, V GS = 2 V, 1 C). Solid box: before stress in forward configuration; solid circle: after 15 s stress in forward configuration; open box: before stress in reverse configuration; open circle: after 15 s stress in reverse configuration.

7 Z. Tang et al. / Solid-State Electronics 53 (29) the forward measurement (which takes about 4 s) at 1 C. We also measured reverse data before forward data in a similar way. The result showed that the forward current is a little higher than the reverse current after 15 s BTS. The averaged forward and reverse data in different sequences yielded the same currents, which confirmed the partially annealed, reduced V t from the data measured second compared with the data measured first. For V D -BTS (Fig. 6b), the forward and reverse transfer characteristics are identical before the stress, but the reverse subthreshold current is higher than the forward subthreshold current after 15 s V D -BTS stress (Fig. 6b), and the difference is more prominent than after the BTS (Fig. 6a). This is still due to the thermal annealing during the first (forward) measurement. When the reverse characteristic is measured first, the thermal annealing effect in the first (reverse) measurement is absent and thus the crossing between the forward and reverse transfer characteristics as visible in Fig. 6b does not exist. It was observed that the forward currents were nearly the same but the reverse currents were substantially different if the measurement sequence was reversed. This could be due to the fact that the annealing of V t is the highest near source and is negligible near the drain because the V t -shift is maximum at source and minimum at drain after the V D -BTS stress. The maximum V t affects the reverse current more than the forward current. Therefore, the thermal annealing effect of V t -shift apparent in the second measurement affects the reverse current, but not the forward current. It should be noted that the V t extracted in a conventional way by extrapolation of the triode or saturation-mode transfer curves, as illustrated in Fig. 2, tends to depend on the current range chosen for extrapolation. This should be due, at least partially, to the dependence of l FE on the vertical electric field (i.e., the field-effect mobility) during the measurement. Shur et al. modeled l FE as a function of gate bias [18] as l FE ¼ l c V gs V t ð14þ V AA where l is the electron mobility in the extended band, and c is a dispersion parameter and is dependent on the quality of the a- Si:H layer. V AA is dependent on the geometrical parameters such as gate dielectric thickness. The l FE dependence on V gs can lead to a different extrapolated V t if a different I d range is used. We extracted V t from the triode and saturation-mode transfer curves separately, in a repeated V D -BTS stress experiment. Fig. 7 shows the I d V gs ((a) and (c)) with the drain bias at.1 V and I d Vgs ((b) and (d)) with the drain bias at 3 V. The figure shows the forward (solid square) and reverse (open circle) transfer curves before and after a 15 s V D -BTS (V DS = V GS = 2 V, 1 C) on a non-wirebonded I-type sample (S24, W/L = 4/2). To exclude the thermal annealing effect on the transfer characteristics, we averaged the forward data from different measurement sequences, and similarly averaged reverse data, which are presented in Fig. 7. The triodemode slope (I d V gs in (a) and (c)) is fairly constant over a wide current range. For both before and after stress, the extrapolation yields a unique V t. As an example, we obtained V t by extrapolating from three different current ranges above the threshold. l FE can be calculated from the slope the triode-mode I d V gs curve as l FE =di d /dv gs / (C i V ds W/L) where di d /dv gs is the slope of I d V gs curve, and C i is insulator capacitance per unit area. Fig. 8 shows the V t extracted from the three different current ranges in forward and reverse configurations before and after stress. A maximum variance of.2 V in the extracted V t shows that the V t from triode transfer curves is relatively independent of the gate bias. This is consistent with the observation that the extracted V t from triode-mode transfer characteristic is a simple linear average of V t (y) along the channel according to Eq. (1). Fig. 7. Transfer characteristics of I d V gs in triode measurement (a) before stress and (c) after 15 s V D -BTS (V DS = V GS = 2 V, 1 C); ( I d) Vgs in saturation measurement (b) before stress; (d) after 15 s V D -BTS (V DS = V GS = 2 V, 1 C) stress in forward and reverse configurations. The data is averaged data of each configuration in different measurement sequences. Solid box: represents forward configuration data; open circle: represents reverse configuration data. Before stress, although the forward and reverse saturationmode transfer curves (i.e., the I d Vgs data) are nearly the same (see Fig. 7 b), the extracted V t from the saturation-mode data is significantly dependent on the chosen current range for extrapolation. Fig. 8 b shows that the extracted V t increases with the increasing current by about V for both forward and reverse data. On the other hand, after a saturation-mode V D -BTS, Fig. 7d showed that the averaged forward saturation-mode current is higher than the averaged reverse current at V gs > 4 5 V. This indicated that the measured forward V t is lower than the reverse V t. Fig. 8d shows that after the V D -BTS stress, the saturation-mode data shows a V t variance of about.3 V for forward direction, but a.9 V variance for the reverse V t over the current ranges used. Therefore, with the increasing V gs, the reverse saturation current increases less rapidly than the forward current. This may be represented by a smaller field-effect mobility parameter (c) in the reverse I V characteristic than in the forward I V characteristic. That is, the effects on the saturation drain current by the non-uniform V t profile after V D -BTS, namely the forward profile (V t decreasing from source to drain) and the reverse profile (V t increasing from source to drain), could be modeled by a different effective field-effect mobility parameter for the two measurement directions, but this is beyond the scope of this paper. It is interesting to note that in the triode-mode I d V gs curve has a nearly constant slope (see Fig. 7c), indicating that the V gs -dependence of l FE is very small when a small a V ds is applied. This results in a V t which is nearly independent of V gs (see Fig. 8c). This further indicates that the field-effect parameter c is V ds -dependent, taking on a small value at low V ds (triode) and a larger value at a high V ds

8 232 Z. Tang et al. / Solid-State Electronics 53 (29) Fig. 8. V t extracted from different data ranges in forward and reverse configurations from the I d V gs curve in triode measurement and ( I d) Vgs curve in saturation measurement which are presented in Fig. 7. (a) triode measurement before stress; (b) saturation measurement before stress; (c) triode measurement after stress; (d) saturation measurement after stress. (saturation). This possible V ds -dependence of c has not been considered in the original model of field-effect mobility [18]. The V t extracted from a saturation transfer curve varies significantly with the current (or equivalently, V gs ) level probably due to a larger field-effect parameter c and a large variation of the quasi-fermi potential through the channel for saturation measurement. A more careful analysis is necessary for this. However, our result suggests that an average over a wide current range is necessary when quoting V t from a saturation transfer curve. The extracted V t from saturation-mode measurement is also significantly lower than the V t from the linear transfer curves (by as much as 1.5 V, see Fig. 8c and d) [19]. This discrepancy in extracted V t between linear and saturation transfer curves requires further investigation as it could affect devices manifesting field-effect mobility such as a-si:h and organic TFTs. 4. Summary We investigated the V t instability of a-si:h TFTs under V D -BTS at 1 C in U-type and I-type a-si:h TFT samples. The measured DV t was dependent on V DS for low V DS triode-mode stress, and was independent of V DS for high V DS saturation-mode stress. Drain bias in V D -BTS in a-si TFT reduces the local gate overdrive stress V ov (y) in the channel and thus the local channel charge Q ch (y). This then leads to a reduced and non-uniform DV t (y) in the channel [19]. We suggest that the measured DV t is a weighted average of local DV t (y), inversely weighted by the local carrier density, as given by Eq. (9), during the transfer characteristic measurement. A simple linear average of DV t (y) along the channel agreed with the experimental data for the symmetric, I-type samples after V D -BTS stress. Calculation based on a weighted average better agreed with the measured DV t of V D - BTS in the asymmetric, U-type sample; while the simple linear average underestimates the DV t in U-type sample. We suggested that this is due to a larger contribution to the normalized DV t by the (wider) source-side. Output characteristics after V D -BTS shows a higher drain current in forward data (source/drain are the same as in stress) than in reverse data (source/drain interchanged from stress), yielding a smaller forward V t than the reverse V t due probably to the fact that the high local-v t region is weighed down more in the forward direction by a high local overdrive bias in that region. There is evidence that the non-uniform V t (y) profile enhances the reverse subthreshold diffusion current (Fig. 6b). Making multiple I V characteristics measurements at an elevated temperature (1 C in this paper) had significant thermal annealing effect in the data measured later. The thermal annealing seemed to affect the higher V t region near the source more strongly, thus affecting the reverse current more than the forward current. We also presented the dependence of extracted V t on the current (or voltage) range of the data. V t extracted from saturation-mode transfer characteristics show a sensitive dependence on the chosen current range even for a uniform channel device (Fig. 8b); which dependence is somewhat moderated by the non-uniform V t profile in the forward direction (Fig. 8d), but not in the reverse direction. We suggested that for V t from saturation-mode transfer curves, a wide current (or voltage) range must be used for the V t extraction in order to average out such variation.

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