N57M tap Digital Potentiometer (POT)

Transcription

1 NM tap igital Potntiomtr (POT) scription Th NM is a singl digital POT dsignd as an lctronic rplacmnt for mchanical potntiomtrs and trim pots. Idal for automatd adjustmnts on high volum production lins, thy ar also wll suitd for applications whr quipmnt rquiring priodic adjustmnt is ithr difficult to accss or locatd in a hazardous or rmot nvironmnt. Th NM contains a -tap sris rsistor array connctd btwn two trminals R H and R L. n up/down countr and dcodr that ar controlld by thr input pins, dtrmins which tap is connctd to th wipr, R W. Th wipr stting, stord in nonvolatil mmory, is not lost whn th dvic is powrd down and is automatically rinstatd whn powr is rturnd. Th wipr can b adjustd to tst nw systm valus without affcting th stord stting. Wipr-control of th NM is accomplishd with thr input control pins,,, and. Th input incrmnts th wipr in th dirction which is dtrmind by th logic stat of th input. Th input is usd to slct th dvic and also stor th wipr position prior to powr down. Th digital POT can b usd as a thr-trminal rsistiv dividr or as a two-trminal variabl rsistor. igital POTs bring variability and programmability to a wid varity of applications including control, paramtr adjustmnts, and signal procssing. Faturs -position Linar Tapr Potntiomtr Non-volatil PROM Wipr Storag Low Standby Currnt Singl Supply Opration:. V.0 V Incrmnt Up/own Srial Intrfac Rsistanc Valus: 0 k, 0 k and 00 k vailabl in SOIC, TSSOP, MSOP and Spac Saving mm TFN Packags Ths vics ar Pb-Fr, Halogn Fr/BFR Fr and ar RoHS Compliant pplications utomatd Product Calibration Rmot Control djustmnts Offst, Gain and Zro Control Tampr-proof Calibrations Contrast, Brightnss and Volum Controls Motor Controls and Fdback Systms Programmabl nalog Functions SOIC V SUFFIX B V CC TSSOP Y SUFFIX 9L PIN CONFIGURTIONS R H SOIC (V), MSOP (Z) R H TSSOP (Y) TFN (VP) (Top Viws) MSOP Z SUFFIX TFN VP SUFFIX K V CC R L R W V CC R L R W R L R W R H ORRING INFORMTION S dtaild ordring and shipping information in th packag dimnsions sction on pag 9 of this data sht. Smiconductor Componnts Industris, LLC, 0 Jun, 0 Rv. Publication Ordr Numbr: NM/

2 NM SOIC VIC MRKING INFORMTION MSOP TSSOP RLB CTVI YMXXXX BMS YMP RL YMXXX R = Rsistanc = 0 k = 0 k = 00 k L = ssmbly Location = Lad Finish NiPdu I = Industrial Tmp Rang Y = Production Yar (Last igit) M = Production Month ( 9, O, N, ) XXXX = Last Four igits of ssmbly Lot Numbr Functional iagram BMS = 0 k BMT = 0 k BTH = 00 k Y = Production Yar (Last igit) M = Production Month ( 9, O, N, ) P = Product Rvision TFN FL XXX YM = vic Cod R = Rsistanc = 0 k = 0 k = 00 k L = ssmbly Location = Lad Finish NiPdu Y = Production Yar (last digit) M = Production Month ( 9, O, N, ) XXX = Last Thr igits of ssmbly XXX = Lot Numbr F = 0 k HF = 0 k GW = 00 k XXX = Last Thr igits of ssmbly Lot Numbr Y = Production Yar (Last igit) M = Production Month ( 9, O, N, ) V CC Bit Up/own Countr 0 R H /V H R H /V H Control and Mmory Powr On Rcall R H /V H R W /V W R L /V L V CC Bit Nonvolatil Mmory Stor and Rcall Control Circuitry 9 Position codr 0 Transfr Gats Rsistor rray R L /V L R W /V W R W /V W R L /V L Figur. Gnral Figur. taild Figur. lctronic Potntiomtr Implmntation

3 NM Tabl. PIN SCRIPTIONS Nam R H R W R L V CC Incrmnt Control Up/own Control Function Potntiomtr High Trminal Ground Wipr Trminal Potntiomtr Low Trminal Chip Slct Supply Voltag Pin Function : Incrmnt Control Input Th input movs th wipr in th up or down dirction dtrmind by th condition of th input. : Up/own Control Input Th input controls th dirction of th wipr movmnt. Whn in a high stat and is low, any high-to-low transition on will caus th wipr to mov on incrmnt toward th R H trminal. Whn in a low stat and is low, any high-to-low transition on will caus th wipr to mov on incrmnt towards th R L trminal. R H : High nd Potntiomtr Trminal R H is th high nd trminal of th potntiomtr. It is not rquird that this trminal b connctd to a potntial gratr than th R L trminal. Voltag applid to th R H trminal cannot xcd th supply voltag, V CC or go blow ground,. R W : Wipr Potntiomtr Trminal R W is th wipr trminal of th potntiomtr. Its position on th rsistor array is controlld by th control inputs,, and. Voltag applid to th R W trminal cannot xcd th supply voltag, V CC or go blow ground,. R L : Low nd Potntiomtr Trminal R L is th low nd trminal of th potntiomtr. It is not rquird that this trminal b connctd to a potntial lss than th R H trminal. Voltag applid to th R L trminal cannot xcd th supply voltag, V CC or go blow ground,. R L and R H ar lctrically intrchangabl. : Chip Slct Th chip slct input is usd to activat th control input of th NM and is activ low. Whn in a high stat, activity on th and inputs will not affct or chang th position of th wipr. vic Opration Th NM oprats lik a digitally controlld potntiomtr with R H and R L quivalnt to th high and low trminals and R W quivalnt to th mchanical potntiomtr s wipr. Thr ar availabl tap positions including th rsistor nd points, R H and R L. Thr ar rsistor lmnts connctd in sris btwn th R H and R L trminals. Th wipr trminal is connctd to on of th taps and controlld by thr inputs,, and. Ths inputs control a svn-bit up/down countr whos output is dcodd to slct th wipr position. Th slctd wipr position can b stord in nonvolatil mmory using th and inputs. With st LOW th NM is slctd and will rspond to th and inputs. HIGH to LOW transitions on will incrmnt or dcrmnt th wipr (dpnding on th stat of th input and svn bit countr). Th wipr, whn at ithr fixd trminal, acts lik its mchanical quivalnt and dos not mov byond th last position. Th valu of th countr is stord in nonvolatil mmory whnvr transitions HIGH whil th input is also HIGH. Whn th NM is powrd-down, th last stord wipr countr position is maintaind in th nonvolatil mmory. Whn powr is rstord, th contnts of th mmory ar rcalld and th countr is st to th valu stord. With st low, th NM may b d-slctd and powrd down without storing th currnt wipr position in nonvolatil mmory. This allows th systm to always powr up to a prst valu stord in nonvolatil mmory.

4 NM Tabl. OPRTION MOS Opration High to Low Low High Wipr toward H High to Low Low Low Wipr toward L High Low to High X Stor Wipr Position Low Low to High X No Stor, Rturn to Standby X High X Standby R H C H R WI R W C W C L R L Figur. Potntiomtr quivalnt Circuit Tabl. BSOLUT MXIMUM RTINGS Paramtrs Ratings Units Supply Voltag V CC to 0. to V Inputs to 0. to V CC 0. V to 0. to V CC 0. V to 0. to V CC 0. V H to 0. to V CC 0. V L to 0. to V CC 0. V W to 0. to V CC 0. V Oprating mbint Tmpratur Industrial ( I suffix) 0 to C Junction Tmpratur 0 C Storag Tmpratur to 0 C Lad Soldring (0 s max) 00 C Strsss xcding thos listd in th Maximum Ratings tabl may damag th dvic. If any of ths limits ar xcdd, dvic functionality should not b assumd, damag may occur and rliability may b affctd. Tabl. RLIBILITY CHRCTRISTI Symbol Paramtr Tst Mthod Min Typ Max Units V ZP (Not ) S Suscptibility MIL ST, Tst Mthod V I LTH (Nots, ) Latch-up JC Standard 00 m T R ata Rtntion MIL ST, Tst Mthod Yars N N nduranc MIL ST, Tst Mthod 00,000,000 Stors. This paramtr is tstd initially and aftr a dsign or procss chang that affcts th paramtr.. Latch-up protction is providd for strsss up to 00 m on addrss and data pins from V to V CC V.

5 NM Tabl. C LCTRICL CHRCTRISTI (V CC =. V to V unlss othrwis spcifid) Symbol Paramtr Conditions Min Typ Max Units POWR SUPPLY V CC Oprating Voltag Rang..0 V I CC Supply Currnt (Incrmnt) V CC = V, f = MHz, I W = 0 00 V CC = V, f = 0 khz, I W = 0 0 I CC Supply Currnt (Writ) Programming, V CC = V 000 I SB (Not ) Supply Currnt (Standby) = V CC 0. V, = V CC 0. V or V CC = V 00 LOGIC INPUTS I IH Input Lakag Currnt V IN = V CC 0 I IL Input Lakag Currnt V IN = 0 V 0 V IH CMOS High Lvl Input Voltag. V V CC V V CC x 0. V CC 0. V V IL CMOS Low Lvl Input Voltag 0. V CC x 0. V POTNTIOMTR CHRCTRISTI R POT Potntiomtr Rsistanc 0 vic 0 k 0 vic 0 00 vic 00 Pot. Rsistanc Tolranc ±0 % V RH Voltag on R H pin 0 V CC V V RL Voltag on R L pin 0 V CC V Rsolution. % INL Intgral Linarity rror 0. LSB NL iffrntial Linarity rror 0. LSB R WI Wipr Rsistanc V CC = V, I W = m 0 00 V CC =. V, I W = m 0 00 I W Wipr Currnt.. m TC RPOT TC of Pot Rsistanc 00 ppm/ C TC RTIO Ratiomtric TC 0 ppm/ C V N Nois 00 khz / khz / nv/ Hz C H /C L /C W Potntiomtr Capacitancs // pf fc Frquncy Rspons Passiv ttnuator, 0 k. MHz Product paramtric prformanc is indicatd in th lctrical Charactristics for th listd tst conditions, unlss othrwis notd. Product prformanc may not b indicatd by th lctrical Charactristics if opratd undr diffrnt conditions.. This paramtr is tstd initially and aftr a dsign or procss chang that affcts th paramtr.. Latch up protction is providd for strsss up to 00 m on addrss and data pins from V to V CC V.. I W = sourc or sink.. Ths paramtrs ar priodically sampld and ar not 00% tstd.

6 NM Tabl. C TST CONITIONS V CC Rang Input Puls Lvls Input Ris and Fall Tims Input Rfrnc Lvls. V V CC V 0. x V CC to 0. x V CC 0 ns 0. x V CC Tabl. C OPRTING CHRCTRISTI (V CC =. V to.0 V, V H = V CC, V L = 0 V, unlss othrwis spcifid) Symbol Paramtr Min Typ (Not ) Max Units t CI to Stup 00 ns t I to Stup 0 ns t I to Hold 00 ns t IL LOW Priod 0 ns t IH HIGH Priod 0 ns t IC Inactiv to Inactiv s t CPH slct Tim (NO STOR) 00 ns t CPH slct Tim (STOR) 0 ms t IW to V OUT Chang s t CYC Cycl Tim s t R, t F (Not ) Input Ris and Fall Tim 00 s t PU (Not ) Powr-up to Wipr Stabl ms t WR Stor Cycl 0 ms. Typical valus ar for T = C and nominal supply voltag.. This paramtr is priodically sampld and not 00% tstd. 9. MI in th.c. Timing diagram rfrs to th minimum incrmntal chang in th W output du to a chang in th wipr position. t CI t IL t CYC t IH t IC (stor) t CPH 90% 90% 0% t I t I t F t R t IW MI () R W Figur..C. Timing

7 NM PPLICTIONS INFORMTION (a) rsistiv dividr (b) variabl rsistanc (c) two port Figur. Potntiomtr Configuration pplications V ( ) igital POT NM V () R R R R R R 9 0 R = = = / LM0 R = R = R = k R POT = 0 k V O. V igital POT R B NM R R pr POT C R ( p)r POT 0.0 F 0.00 F 0.0 F Figur. Programmabl Instrumntation mplifir Figur. Programmabl Sq. Wav Oscillator () V IN (UNRG) SHUTOWN igital POT F NM 00 k V OUT 9 S FB. V R k R 0 R 0 k 0. F. F V O (RG) I S igital POT NM pr ( p)r 0 0 M 0 k V O LT09. V Figur 9. Programmabl Voltag Rgulator Figur 0. Programmabl I to V Convrtor

8 NM V S F igital POT C 0.00 F R 0 k NM C 0.00 F R 0 k R 00 k V O. V Figur. Programmabl Bandpass Filtr OSC 0 k IC HC 0. F CLO CHI IC 9 V LL R R R V UL IC NM 0 k igital POT V S. V 0 V S. V I IC. V O V V O Figur. utomatic Gain Control

9 NM Tabl. ORRING INFORMTION Ordrabl Part Numbrs Rsistanc Valus (k ) Packag Pin Lad Finish Shipping NMW0TG 0 NMW0TG 0 NMW00TG 00 NMVP0TG (Not 0) 0 NMVP0TG 0 NMVP00TG 00 NMY0TG 0 NMY0TG 0 NMY00TG 00 NMZ0TG 0 NMZ0TG 0 NMZ00TG 00 SOIC NiPdu 00 Units / Rail TFN x mm TSSOP NiPdu NiPdu 000 / Tap & Rl 000 / Tap & Rl MSOP NiPdu 9 Units / Rail For information on tap and rl spcifications, including part orintation and tap sizs, plas rfr to our Tap and Rl Packaging Spcifications Brochur, BR0/. 0. Contact factory for availability.. ll packags ar RoHS-compliant (Pb-Fr, Halogn-Fr).. Th standard lad finish is NiPdu.. For additional packag and tmpratur options, plas contact your narst ON Smiconductor Sals offic. 9

10 NM PCKG IMNSIONS SOIC, 0 mils B ISSU O SYMBOL MIN NOM MX b c BSC h PIN # INTIFICTION L 0.0. θ 0º º TOP VIW h θ c b L SI VIW N VIW Nots: () ll dimnsions ar in millimtrs. ngls in dgrs. () Complis with JC MS-0. 0

11 NM PCKG IMNSIONS MSOP, x ISSU O SYMBOL MIN NOM MX b c BSC L L 0.9 RF L θ 0. BSC 0º º TOP VIW TIL b c SI VIW N VIW L Nots: () ll dimnsions ar in millimtrs. ngls in dgrs. () Complis with JC MO-. TIL L L

12 NM PCKG IMNSIONS TFN, x K ISSU b PIN# INTIFICTION PIN# INX R L TOP VIW SI VIW BOTTOM VIW SYMBOL MIN NOM MX RF b FRONT VIW TYP L Nots: () ll dimnsions ar in millimtrs. () Complis with JC MO-9.

13 NM PCKG IMNSIONS b TSSOP,.x 9L ISSU O SYMBOL MIN NOM MX b c BSC L.00 RF L θ º º TOP VIW c SI VIW L N VIW L Nots: () ll dimnsions ar in millimtrs. ngls in dgrs. () Complis with JC MO-. ON Smiconductor and ar tradmarks of Smiconductor Componnts Industris, LLC dba ON Smiconductor or its subsidiaris in th Unitd Stats and/or othr countris. ON Smiconductor owns th rights to a numbr of patnts, tradmarks, copyrights, trad scrts, and othr intllctual proprty. listing of ON Smiconductor s product/patnt covrag may b accssd at /sit/pdf/patnt Marking.pdf. ON Smiconductor rsrvs th right to mak changs without furthr notic to any products hrin. ON Smiconductor maks no warranty, rprsntation or guarant rgarding th suitability of its products for any particular purpos, nor dos ON Smiconductor assum any liability arising out of th application or us of any product or circuit, and spcifically disclaims any and all liability, including without limitation spcial, consquntial or incidntal damags. Buyr is rsponsibl for its products and applications using ON Smiconductor products, including complianc with all laws, rgulations and safty rquirmnts or standards, rgardlss of any support or applications information providd by ON Smiconductor. Typical paramtrs which may b providd in ON Smiconductor data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including Typicals must b validatd for ach customr application by customr s tchnical xprts. ON Smiconductor dos not convy any licns undr its patnt rights nor th rights of othrs. ON Smiconductor products ar not dsignd, intndd, or authorizd for us as a critical componnt in lif support systms or any F Class mdical dvics or mdical dvics with a sam or similar classification in a forign jurisdiction or any dvics intndd for implantation in th human body. Should Buyr purchas or us ON Smiconductor products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold ON Smiconductor and its officrs, mploys, subsidiaris, affiliats, and distributors harmlss against all claims, costs, damags, and xpnss, and rasonabl attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that ON Smiconductor was nglignt rgarding th dsign or manufactur of th part. ON Smiconductor is an qual Opportunity/ffirmativ ction mployr. This litratur is subjct to all applicabl copyright laws and is not for rsal in any mannr. PUBLICTION ORRING INFORMTION LITRTUR FULFILLMNT: Litratur istribution Cntr for ON Smiconductor 9. nd Pkwy, urora, Colorado 00 US Phon: 0 or 00 0 Toll Fr US/Canada Fax: 0 or 00 Toll Fr US/Canada mail: ordrlit@onsmi.com N. mrican Tchnical Support: 00 9 Toll Fr US/Canada urop, Middl ast and frica Tchnical Support: Phon: Japan Customr Focus Cntr Phon: 00 ON Smiconductor Wbsit: Ordr Litratur: For additional information, plas contact your local Sals Rprsntativ NM/