CAT25010, CAT25020, CAT Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM

Transcription

1 CT25010, CT25020, CT K, 2-K and 4-K SPI Srial CMOS PROM sription Th CT25010/20/40 ar 1 K/2 K/4 K Srial CMOS PROM dvis intrnally organizd as 128x8/256x8/512x8 its. Thy fatur a 16 yt pag writ uffr and support th Srial Priphral Intrfa (SPI) protool. Th dvi is nald through a Chip Slt () input. In addition, th rquird us signals ar a lok input (), data input () and data output () lins. Th HOL input may usd to paus any srial ommuniation with th CT25010/20/40 dvi. Ths dvis fatur softwar and hardwar writ prottion, inluding partial as wll as full array prottion. Faturs 10 MHz SPI Compatil 1.8 V to 5.5 V Supply Voltag Rang SPI Mods (0,0) & (1,1) 16 yt Pag Writ Buffr Slf timd Writ Cyl Hardwar and Softwar Prottion Blok Writ Prottion Prott 1/4, 1/2 or ntir PROM rray Low Powr CMOS Thnology 1,000,000 Program/ras Cyls 100 Yar ata Rtntion Industrial and xtndd Tmpratur Rang 8 lad PIP, IC, TSP and 8 pad TFN Pakags Ths vis ar P Fr, Halogn Fr/BFR Fr, and RoHS Compliant WP HOL V CC CT25010 CT25020 CT25040 IC 8 V SUFFIX CS 751B WP V SS Pin Nam WP V SS HOL V CC PIP 8 L SUFFIX CS 646 PIN CONFIGURTION 1 MP 8 Z SUFFIX CS 846 TSP 8 Y SUFFIX CS 948L TFN 8 VP2 SUFFIX CS 511K V CC HOL PIP (L), IC (V), MP (Z) TSP (Y), TFN (VP2) PIN FUNCTION Chip Slt Srial ata Output Writ Prott Ground Srial ata Input Srial Clok Funtion Hold Transmission Input Powr Supply V SS Figur 1. Funtional Symol ORRING INFORMTION S dtaild ordring and shipping information in th pakag dimnsions stion on pag 15 of this data sht. Smiondutor Componnts Industris, LLC, 2010 Fruary, 2010 Rv Puliation Ordr Numr: CT25010/

2 Tal 1. BLUT MXIMUM RTINGS Paramtrs Ratings Units Oprating Tmpratur 45 to +130 C Storag Tmpratur 65 to +150 C Voltag on any Pin with Rspt to Ground (Not 1) 0.5 to V CC V Strsss xding Maximum Ratings may damag th dvi. Maximum Ratings ar strss ratings only. Funtional opration aov th Rommndd Oprating Conditions is not implid. xtndd xposur to strsss aov th Rommndd Oprating Conditions may afft dvi rliaility. Tal 2. RLIBILITY CHRCTRISTI (Not 2) Symol Paramtr Min Units N N (Not 3) nduran 1,000,000 Program / ras Cyls T R ata Rtntion 100 Yars Tal 3..C. OPRTING CHRCTRISTI (V CC = +1.8 V to +5.5 V, T = 40 C to +125 C unlss othrwis spifid.) Symol Paramtr Tst Conditions Min Max Units I CC Supply Currnt Rad, Writ, V CC = 5.0 V, 10 MHz / 40 C to 85 C 2 m opn 5 MHz / 40 C to 125 C 2 m I SB1 Standy Currnt V IN = GN or V CC, = V CC, WP = V CC, V CC = 5.0 V I SB2 Standy Currnt V IN = GN or V CC, = V CC, WP = GN, V CC = 5.0 V 2 T = 40 C to +85 C 4 T = 40 C to +125 C 5 I L Input Lakag Currnt V IN = GN or V CC 2 2 I LO Output Lakag Currnt = V CC, T = 40 C to +85 C 1 1 V OUT = GN or V CC T = 40 C to +125 C 1 2 V IL Input Low Voltag V CC V V IH Input High Voltag 0.7 V CC V CC V V OL1 Output Low Voltag V CC > 2.5 V, I OL = 3.0 m 0.4 V V OH1 Output High Voltag V CC > 2.5 V, I OH = 1.6 m V CC 0.8 V V V OL2 Output Low Voltag V CC > 1.8 V, I OL = V V OH2 Output High Voltag V CC > 1.8 V, I OH = 100 V CC 0.2 V V Tal 4. PIN CPCITNC (Not 2) (T = 25 C, f = 1.0 MHz, V CC = +5.0 V) Symol Tst Conditions Min Typ Max Units C OUT Output Capaitan () V OUT = 0 V 8 pf C IN Input Capaitan (,,, WP, HOL) V IN = 0 V 8 pf 1. Th C input voltag on any pin should not lowr than 0.5 V or highr than V CC V. uring transitions, th voltag on any pin may undrshoot to no lss than 1.5 V or ovrshoot to no mor than V CC V, for priods of lss than 20 ns. 2. Ths paramtrs ar tstd initially and aftr a dsign or pross hang that affts th paramtr aording to appropriat C Q100 and JC tst mthods. 3. Pag Mod, V CC = 5 V, 25 C. 2

3 Tal 5..C. CHRCTRISTI (T = 40 C to +125 C, unlss othrwis spifid.) (Nots 4, 8) V CC = 2.5 V 5.5 V V CC = 1.8 V 5.5 V T = 40 C to +85 C Symol Paramtr Min Max Min Max Units f Clok Frquny C 5 C 10 MHz t SU ata Stup Tim ns t H ata Hold Tim ns t WH High Tim ns t WL Low Tim ns t LZ HOL to Output Low Z ns t RI (Not 5) Input Ris Tim 2 2 s t FI (Not 5) Input Fall Tim 2 2 s t H HOL Stup Tim 0 0 ns t C HOL Hold Tim ns t V Output Valid from Clok Low ns t HO Output Hold Tim 0 0 ns t IS Output isal Tim ns t HZ HOL to Output High Z ns t High Tim ns t S Stup Tim ns t H Hold Tim ns t CNS Inativ Stup Tim ns t CNH Inativ Hold Tim ns t WPS WP Stup Tim ns t WPH WP Hold Tim ns t WC (Not 7) Writ Cyl Tim 5 5 ms Tal 6. POWR UP TIMING (Nots 5, 6) Symol Paramtr Max Units t PUR Powr up to Rad Opration 1 ms t PUW Powr up to Writ Opration 1 ms 4. C Tst Conditions: Input Puls Voltags: 0.3 V CC to 0.7 V CC Input ris and fall tims: 10 ns Input and output rfrn voltags: 0.5 V CC Output load: urrnt sour I OL max /I OH max ; C L = 50 pf 5. This paramtr is tstd initially and aftr a dsign or pross hang that affts th paramtr. 6. t PUR and t PUW ar th dlays rquird from th tim V CC is stal until th spifid opration an initiatd. 7. t WC is th tim from th rising dg of aftr a valid writ squn to th nd of th intrnal writ yl. 8. ll Chip Slt () timing paramtrs ar dfind rlativ to th positiv lok dg (Figur 2). t H timing spifiation is valid for di rvision and highr. Th di rvision is idntifid y lttr or a ddiatd marking od on top of th pakag. For prvious produt rvision (Rv. C) th t H is dfind rlativ to th ngativ lok dg (plas rfr to data sht o. No. M-1006 Rv. U) 3

4 Pin sription : Th srial data input pin apts op ods, addrsss and data. In SPI mods (0,0) and (1,1) input data is lathd on th rising dg of th lok input. : Th srial data output pin is usd to transfr data out of th dvi. In SPI mods (0,0) and (1,1) data is shiftd out on th falling dg of th lok. : Th srial lok input pin apts th lok providd y th host and usd for synhronizing ommuniation twn host and CT25010/20/40. : Th hip slt input pin is usd to nal/disal th CT25010/20/40. Whn is high, th output is tri statd (high impdan) and th dvi is in Standy Mod (unlss an intrnal writ opration is in progrss). vry ommuniation sssion twn host and CT25010/20/40 must prdd y a high to low transition and onludd with a low to high transition of th input. WP: Th writ prott input pin will allow all writ oprations to th dvi whn hld high. Whn WP pin is tid low all writ oprations ar inhiitd. HOL: Th HOL input pin is usd to paus transmission twn host and CT25010/20/40, without having to rtransmit th ntir squn at a latr tim. To paus, HOL must takn low and to rsum it must takn ak high, with th input low during oth transitions. Whn not usd for pausing, th HOL input should tid to V CC, ithr dirtly or through a rsistor. Funtional sription Th CT25010/20/40 dvis support th Srial Priphral Intrfa (SPI) us protool, mods (0,0) and (1,1). Th dvi ontains an 8 it instrution rgistr. Th instrution st and assoiatd op ods ar listd in Tal 7. Rading data stord in th CT25010/20/40 is aomplishd y simply providing th R ommand and an addrss. Writing to th CT25010/20/40, in addition to a WRIT ommand, addrss and data, also rquirs naling th dvi for writing y first stting rtain its in a Status Rgistr, as will xplaind latr. ftr a high to low transition on th input pin, th CT25010/20/40 will apt any on of th six instrution op ods listd in Tal 7 and will ignor all othr possil 8 it ominations. Th ommuniation protool follows th timing from Figur 2. Tal 7. INSTRUCTION ST (Not 9) Instrution Opod Opration WRN nal Writ Oprations WRI isal Writ Oprations RSR Rad Status Rgistr WRSR Writ Status Rgistr R 0000 X011 Rad ata from Mmory WRIT 0000 X010 Writ ata to Mmory 9. X = 0 for CT25010, CT X = 8 for CT25040 t t CNH t S t WH t WL t H t CNS t SU t H t RI t FI VLI IN t V t V t IS t HO HI Z VLI OUT HI Z Figur 2. Synhronous ata Timing Status Rgistr Th Status Rgistr, as shown in Tal 8, ontains a numr of status and ontrol its. Th RY (Rady) it indiats whthr th dvi is usy with a writ opration. This it is automatially st to 1 during an intrnal writ yl, and rst to 0 whn th dvi is rady to apt ommands. For th host, this it is rad only. Th WL (Writ nal Lath) it is st/rst y th WRN/WRI ommands. Whn st to 1, th dvi is in a Writ nal stat and whn st to 0, th dvi is in a Writ isal stat. Th BP0 and BP1 (Blok Prott) its dtrmin whih loks ar urrntly writ prottd. Thy ar st y th usr with th WRSR ommand and ar non volatil. Th usr is allowd to prott a quartr, on half or th ntir mmory, y stting ths its aording to Tal 9. Th prottd loks thn om rad only. 4

5 Tal 8. STTUS RGISTR BP1 BP0 WL RY Tal 9. BLOCK PROTCTION BITS Status Rgistr Bits BP1 BP0 rray ddrss Prottd Prottion 0 0 Non No Prottion 0 1 CT25010: F, CT25020: 0C0 0FF, CT25040: 180 1FF Quartr rray Prottion 1 0 CT25010: F, CT25020: 080 0FF, CT25040: 100 1FF Half rray Prottion 1 1 CT25010: F, CT25020: 000 0FF, CT25040: 000 1FF Full rray Prottion Th CT25010/20/40 dvi powrs up into a writ disal stat. Th dvi ontains a Writ nal Lath (WL) whih must st for attmpting to writ to th mmory array or to th status rgistr. In addition, th addrss of th mmory loation(s) to writtn must outsid th prottd ara, as dfind y BP0 and BP1 its from th status rgistr. Writ nal and Writ isal Th intrnal Writ nal Lath and th orrsponding Status Rgistr WL it ar st y snding th WRN WRIT OPRTIONS instrution to th CT25010/20/40. Car must takn to tak th input high aftr th WRN instrution, as othrwis th Writ nal Lath will not proprly st. WRN timing is illustratd in Figur 3. Th WRN instrution must snt prior to any WRIT or WRSR instrution. Th intrnal writ nal lath is rst y snding th WRI instrution as shown in Figur 4. isaling writ oprations y rstting th WL it, will prott th dvi against inadvrtnt writs ashd Lin = mod (1, 1) HIGH IMPNC Figur 3. WRN Timing ashd Lin = mod (1, 1) HIGH IMPNC Figur 4. WRI Timing 5

6 Byt Writ On th WL it is st, th usr may xut a writ squn, y snding a WRIT instrution, a 8 it addrss and data as shown in Figur 5. For th CT25040, it 3 of th writ instrution opod ontains 8 addrss it. Intrnal programming will start aftr th low to high transition. uring an intrnal writ yl, all ommands, xpt for RSR (Rad Status Rgistr) will ignord. Th RY it will indiat if th intrnal writ yl is in progrss (RY high), or th dvi is rady to apt ommands (RY low). Pag Writ ftr snding th first data yt to th CT25010/20/40, th host may ontinu snding data, up to a total of 16 yts, aording to timing shown in Figur 6. ftr ah data yt, th lowr ordr addrss its ar automatially inrmntd, whil th highr ordr addrss its (pag addrss) rmain unhangd. If during this pross th nd of pag is xdd, thn loading will roll ovr to th first yt in th pag, thus possily ovrwriting prviously loadd data. Following ompltion of th writ yl, th CT25010/20/40 is automatially rturnd to th writ disal stat OPCO BYT RSS T IN X* HIGH IMPNC ashd Lin = mod (1, 1) * X = 0 for CT25010, CT x = 8 for CT25040 Figur 5. Byt WRIT Timing (N 1)x (N 1)x8 16+Nx8 1 OPCO X* BYTRSS 7 0 ata ata ata Byt 1 Byt 2 Byt 3 HIGH IMPNC ashd Lin = mod (1, 1) * X = 0 for CT25010, CT x = 8 for CT25040 Figur 6. Pag WRIT Timing T IN ata Byt N

7 Writ Status Rgistr Th Status Rgistr is writtn y snding a WRSR instrution aording to timing shown in Figur 7. Only its 2 and 3 an writtn using th WRSR ommand. Writ Prottion Whn WP input is low all writ oprations to th mmory array and Status Rgistr ar inhiitd. WP going low whil is still low will intrrupt a writ to th status rgistr. If th intrnal writ yl has alrady n initiatd, WP going low will hav no fft on any writ opration to th Status Rgistr. Th WP input timing is shown in Figur OPCO T IN ashd Lin = mod (1, 1) HIGH IMPNC MSB Figur 7. WRSR Timing t WPS t WPH WP WP ashd Lin = mod (1, 1) Figur 8. WP Timing 7

8 R OPRTIONS Rad from Mmory rray To rad from mmory, th host snds a R instrution followd y a 8 it addrss (for th CT25040, it 3 of th rad instrution opod ontains 8 addrss it). ftr riving th last addrss it, th CT25010/20/40 will rspond y shifting out data on th pin (as shown in Figur 9). Squntially stord data an rad out y simply ontinuing to run th lok. Th intrnal addrss pointr is automatially inrmntd to th nxt highr addrss as data is shiftd out. ftr rahing th highst mmory addrss, th addrss ountr rolls ovr to th lowst mmory addrss, and th rad yl an ontinud indfinitly. Th rad opration is trminatd y taking high. Rad Status Rgistr To rad th status rgistr, th host simply snds a RSR ommand. ftr riving th last it of th ommand, th CT25010/20/40 will shift out th ontnts of th status rgistr on th pin (Figur 10). Th status rgistr may rad at any tim, inluding during an intrnal writ yl. Whil th intrnal writ yl is in progrss, th RSR ommand will output th RY (Rady) it status only (i.., data out = FFh) OPCO BYT RSS X* HIGH IMPNC ashd Lin = mod (1, 1) * X = 0 for CT25010, CT X = 8 for CT25040 Figur 9. R Timing T OUT MSB OPCO T OUT HIGH IMPNC ashd Lin = mod (1, 1) MSB Figur 10. RSR Timing 8

9 Hold Opration Th HOL input an usd to paus ommuniation twn host and CT25010/20/40. To paus, HOL must takn low whil is low (Figur 11). uring th hold ondition th dvi must rmain sltd ( low). uring th paus, th data output pin () is tri statd (high impdan) and transitions ar ignord. To rsum ommuniation, HOL must takn high whil is low. sign Considrations Th CT25010/20/40 dvis inorporat Powr On Rst (POR) iruitry whih protts th intrnal logi against powring up in th wrong stat. Th dvi will powr up into Standy mod aftr V CC xds th POR triggr lvl and will powr down into Rst mod whn V CC drops low th POR triggr lvl. This i dirtional POR havior protts th dvi against rown out failur following a tmporary loss of powr. Th CT25010/20/40 dvi powrs up in a writ disal stat and in a low powr standy mod. WRN instrution must issud prior to any writs to th dvi. ftr powr up, th pin must rought low to ntr a rady stat and riv an instrution. ftr a sussful yt/pag writ or status rgistr writ, th dvi gos into a writ disal mod. Th input must st high aftr th propr numr of lok yls to start th intrnal writ yl. ss to th mmory array during an intrnal writ yl is ignord and programming is ontinud. ny invalid op od will ignord and th srial output pin () will rmain in th high impdan stat. t C t C t H HOL t H t HZ HIGH IMPNC ashd Lin = mod (1, 1) t LZ Figur 11. HOL Timing 9

10 PCKG IMNONS PIP 8, 300 mils CS ISSU SYMBOL MIN NOM MX PIN # 1 INTIFICTION B BSC L TOP VIW 2 1 L 2 B VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. (2) Complis with JC MS

11 PCKG IMNONS IC 8, 150 mils CS 751B 01 ISSU O SYMBOL MIN NOM MX BSC h PIN # 1 INTIFICTION L θ 0º 8º TOP VIW h 1 θ L VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) Complis with JC MS

12 PCKG IMNONS TSP8, 4.4x3 CS 948L 01 ISSU O SYMBOL MIN NOM MX BSC L 1.00 RF L1 θ º 8º TOP VIW 2 1 VIW 1 L1 N VIW L Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) Complis with JC MO

13 PCKG IMNONS TFN8, 2x3 CS 511K 01 ISSU 2 PIN#1 INTIFICTION PIN#1 INX R 1 2 L TOP VIW VIW BOTTOM VIW SYMBOL MIN NOM MX RF FRONT VIW TYP L Nots: (1) ll dimnsions ar in millimtrs. (2) Complis with JC MO

14 PCKG IMNONS MP 8, 3x3 CS ISSU O SYMBOL MIN NOM MX BSC L L RF L2 θ 0.25 BSC 0º 6º TOP VIW 2 TIL 1 VIW N VIW L2 Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) Complis with JC MO-187. TIL L1 L 14

15 xampl of Ordring Information (Not 12) Prfix vi # Suffix CT V I G T3 Company I Produt Numr 25010: 1 K 25020: 2 K 25040: 4 K Tmpratur Rang I = Industrial ( 40 C to +85 C) = xtndd ( 40 C to +125 C) Lad Finish G: NiPdu Blank: Matt Tin Tap & Rl (Not 15) T: Tap & Rl 3: 3,000 Units / Rl Pakag L: PIP V: IC, JC Y: TSP VP2: TFN (2 x 3 mm) Z: MP (Not 13) 10. ll pakags ar RoHS ompliant (Lad fr, Halogn fr). 11. Th standard lad finish is NiPdu. 12. Th dvi usd in th aov xampl is a CT25040VI GT3 (IC, Industrial Tmpratur, NiPdu, Tap & Rl, 3,000/Rl). 13. For MP pakag availaility, plas ontat your narst ON Smiondutor Sals offi. 14. For additional pakag and tmpratur options, plas ontat your narst ON Smiondutor Sals offi. 15. For information on tap and rl spifiations, inluding part orintation and tap sizs, plas rfr to our Tap and Rl Pakaging Spifiations Brohur, BR8011/. ON Smiondutor and ar rgistrd tradmarks of Smiondutor Componnts Industris, LLC (SCILLC). SCILLC rsrvs th right to mak hangs without furthr noti to any produts hrin. SCILLC maks no warranty, rprsntation or guarant rgarding th suitaility of its produts for any partiular purpos, nor dos SCILLC assum any liaility arising out of th appliation or us of any produt or iruit, and spifially dislaims any and all liaility, inluding without limitation spial, onsquntial or inidntal damags. Typial paramtrs whih may providd in SCILLC data shts and/or spifiations an and do vary in diffrnt appliations and atual prforman may vary ovr tim. ll oprating paramtrs, inluding Typials must validatd for ah ustomr appliation y ustomr s thnial xprts. SCILLC dos not onvy any lins undr its patnt rights nor th rights of othrs. SCILLC produts ar not dsignd, intndd, or authorizd for us as omponnts in systms intndd for surgial implant into th ody, or othr appliations intndd to support or sustain lif, or for any othr appliation in whih th failur of th SCILLC produt ould rat a situation whr prsonal injury or dath may our. Should Buyr purhas or us SCILLC produts for any suh unintndd or unauthorizd appliation, Buyr shall indmnify and hold SCILLC and its offirs, mploys, susidiaris, affiliats, and distriutors harmlss against all laims, osts, damags, and xpnss, and rasonal attorny fs arising out of, dirtly or indirtly, any laim of prsonal injury or dath assoiatd with suh unintndd or unauthorizd us, vn if suh laim allgs that SCILLC was nglignt rgarding th dsign or manufatur of th part. SCILLC is an qual Opportunity/ffirmativ tion mployr. This litratur is sujt to all applial opyright laws and is not for rsal in any mannr. PUBLICTION ORRING INFORMTION LITRTUR FULFILLMNT: Litratur istriution Cntr for ON Smiondutor P.O. Box 5163, nvr, Colorado US Phon: or Toll Fr US/Canada Fax: or Toll Fr US/Canada mail: ordrlit@onsmi.om N. mrian Thnial Support: Toll Fr US/Canada urop, Middl ast and fria Thnial Support: Phon: Japan Customr Fous Cntr Phon: ON Smiondutor Wsit: Ordr Litratur: For additional information, plas ontat your loal Sals Rprsntativ CT25010/