128-Kb I 2 C CMOS Serial EEPROM

Transcription

1 b I 2 MO rial EEPROM FEURE upports tandard and Fast I 2 Protocol 1.8V to 5.5V upply Voltag Rang 64-Byt Pag Writ Buffr Hardwar Writ Protction for ntir mmory chmitt riggrs and Nois upprssion Filtrs on I 2 Bus Inputs (L and D). Low powr MO tchnology DEVIE DERIPION h is a 128-b rial MO EEPROM, intrnally organizd as 16,384 words of 8 bits ach. It faturs a 64-byt pag writ buffr and supports both th tandard (100 khz) as wll as Fast (400 khz) I 2 protocol. Writ oprations can b inhibitd by taking th WP pin High (this protcts th ntir mmory). 1,000,000 program/ras cycls 100 yar data rtntion Industrial and Extndd tmpratur rang RoH-compliant 8-lad PDIP, OI, OP and UDFN packags For additional packags and Ordring Information dtails, s pag 15. PIN ONFIGURION FUNIONL YMBOL PDIP (L) OI (W) OP (Y) UDFN (HU3) V V WP L L V 4 5 D 2, 1, D For th location of Pin 1, plas consult th corrsponding packag drawing. WP PIN FUNION 0, 1, 2 Dvic ddrss Inputs D rial Data Input/Output L rial lock Input WP Writ Protct Input V V Powr upply Ground V * atalyst carris th I 2 protocol undr a licns from th Philips orporation ILL. ll rights rsrvd. haractristics subjct to chang without notic. 1 Doc. No. MD-1103, Rv. L

2 24128 BOLUE MXIMUM RING (1) torag mpratur Voltag on ny Pin with Rspct to Ground (2) -65 to V to +6.5 V RELIBILIY HRERII (3) ymbol Paramtr Min Units N (4) END Enduranc 1,000,000 Program/ Eras ycls DR Data Rtntion 100 Yars D.. OPERING HRERII V = 1.8 V to 5.5 V, = -40 to +125, unlss othrwis spcifid. ymbol Paramtr st onditions Min Max Units I R Rad urrnt Rad, f L = 400kHz 1 m I W Writ urrnt Writ, f L = 400kHz 3 m = -40 to I B tandby urrnt ll I/O Pins at GND or V = -40 to μ = -40 to I L I/O Pin Lakag Pin at GND or V = -40 to μ V IL Input Low Voltag -0.5 V x 0.3 V V IH Input High Voltag V x 0.7 V V V OL1 Output Low Voltag V < 2.5 V, I OL = 3.0m 0.4 V V OL2 Output Low Voltag V < 2.5 V, I OL = 1.0m 0.2 V PIN IMPEDNE HRERII V = 1.8 V to 5.5 V, = -40 to +125, unlss othrwis spcifid. ymbol Paramtr onditions Max Units IN (3) D I/O Pin apacitanc V IN = 0 V 8 pf IN (3) Input apacitanc (othr pins) V IN = 0 V 6 pf I WP (5) WP Input urrnt V IN < V IH 200 μ V IN > V IH 1 μ Not: (1) trsss abov thos listd undr bsolut Maximum Ratings may caus prmannt damag to th dvic. hs ar strss ratings only, and functional opration of th dvic at ths or any othr conditions outsid of thos listd in th oprational sctions of this spcification is not implid. Exposur to any absolut maximum rating for xtndd priods may affct dvic prformanc and rliability. (2) h D input voltag on any pin should not b lowr than -0.5 V or highr than V V. During transitions, th voltag on any pin may undrshoot to no lss than -1.5 V or ovrshoot to no mor than V V, for priods of lss than 20 ns. (3) hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat E-Q100 and JEDE tst mthods. (4) Pag Mod, V = 5 V, 25 (5) Whn not drivn, th WP pin is pulld down to GND intrnally. For improvd nois immunity, th intrnal pull-down is rlativly strong; thrfor th xtrnal drivr must b abl to supply th pull-down currnt whn attmpting to driv th input HIGH. o consrv powr, as th input lvl xcds th trip point of th MO input buffr (~ 0.5 x V), th strong pull-down rvrts to a wak currnt sourc. Doc. No. MD-1103, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic.

3 HRERII (1) V = 1.8 V to 5.5 V, = -40 to tandard Fast ymbol Paramtr Min Max Min Max Units F L lock Frquncy khz t HD: R ondition Hold im μs t LOW Low Priod of L lock μs t HIGH High Priod of L lock μs t U: R ondition tup im μs t HD:D Data Hold im 0 0 μs t U:D Data tup im ns t R D and L Ris im ns t (2) F D and L Fall im ns t U:O OP ondition tup im μs t BUF Bus Fr im Btwn OP and R μs t L Low to D Data Out μs t DH Data Out Hold im ns (2) i Nois Puls Filtrd at L and D Inputs ns t U:WP WP tup im 0 0 μs t HD:WP WP Hold im μs t WR Writ ycl im 5 5 ms t (2, 3) PU Powr-up to Rady Mod 1 1 ms Not: (1) st conditions according to.. st onditions tabl. (2) std initially and aftr a dsign or procss chang that affcts this paramt. (3) t PU is th dlay btwn th tim V is stabl and th dvic is rady to accpt commands... E ONDIION Input Lvls Input Ris and Fall ims Input Rfrnc Lvls Output Rfrnc Lvls Output Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrnt ourc: I OL = 3 m (V 2.5 V); I OL = 1 m (V < 2.5 V); L = 100 pf 2009 ILL. ll rights rsrvd. haractristics subjct to chang without notic. 3 Doc No. MD-1103, Rv. L

4 24128 POWER-ON REE (POR) h incorporats Powr-On Rst (POR) circuitry which protcts th dvic against powring up in th wrong stat. h will powr up into tandby mod aftr V xcds th POR triggr lvl and will powr down into Rst mod whn V drops blow th POR triggr lvl. his bi-dirctional POR fatur protcts th dvic against brown-out failur following a tmporary loss of powr. PIN DERIPION L: h rial lock input pin accpts th rial lock gnratd by th Mastr. D: h rial Data I/O pin rcivs input data and transmits data stord in EEPROM. In transmit mod, this pin is opn drain. Data is acquird on th positiv dg, and is dlivrd on th ngativ dg of L. 0, 1 and 2 : h ddrss pins accpt th dvic addrss. Whn not drivn, ths pins ar pulld LOW intrnally. WP: h Writ Protct input pin inhibits all writ oprations, whn pulld HIGH. Whn not drivn, this pin is pulld LOW intrnally. FUNIONL DERIPION h supports th Intr-Intgratd ircuit (I 2 ) Bus data transmission protocol, which dfins a dvic that snds data to th bus as a transmittr and a dvic rciving data as a rcivr. Data flow is controlld by a Mastr dvic, which gnrats th srial clock and all R and OP conditions. h acts as a lav dvic. Mastr and lav altrnat as ithr transmittr or rcivr. Up to 8 dvics may b connctd to th bus as dtrmind by th dvic addrss inputs 0, 1, and 2. I 2 BU PROOOL h I 2 bus consists of two wirs, L and D. h two wirs ar connctd to th V supply via pull-up rsistors. Mastr and lav dvics connct to th 2- wir bus via thir rspctiv L and D pins. h transmitting dvic pulls down th D lin to transmit a 0 and rlass it to transmit a 1. Data transfr may b initiatd only whn th bus is not busy (s.. haractristics). During data transfr, th D lin must rmain stabl whil th L lin is HIGH. n D transition whil L is HIGH will b intrprtd as a R or OP condition (Figur 1). h R condition prcds all commands. It consists of a HIGH to LOW transition on D whil L is HIGH. h R acts as a wak-up call to all rcivrs. bsnt a R, a lav will not rspond to commands. h OP condition complts all commands. It consists of a LOW to HIGH transition on D whil L is HIGH. Dvic ddrssing h Mastr initiats data transfr by crating a R condition on th bus. h Mastr thn broadcasts an 8-bit srial lav addrss. h first 4 bits of th lav addrss ar st to 1010, for normal Rad/Writ oprations (Figur 2). h nxt 3 bits, 2, 1 and 0, slct on of 8 possibl lav dvics and must match th stat of th xtrnal addrss pins. h last bit, R/W, spcifis whthr a Rad (1) or Writ (0) opration is to b prformd. cknowldg ftr procssing th lav addrss, th lav rsponds with an acknowldg () by pulling down th D lin during th 9 th clock cycl (Figur 3). h lav will also acknowldg all addrss byts and vry data byt prsntd in Writ mod. In Rad mod th lav shifts out a data byt, and thn rlass th D lin during th 9 th clock cycl. s long as th Mastr acknowldgs th data, th lav will continu transmitting. h Mastr trminats th sssion by not acknowldging th last data byt (No) and by issuing a OP condition. Bus timing is illustratd in Figur 4. Doc. No. MD-1103, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic.

5 24128 Figur 1. R/OP onditions L D R ONDIION OP ONDIION Figur 2. lav ddrss Bits DEVIE DDRE R/W Figur 3. cknowldg iming BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUPU FROM RNMIER D OUPU FROM REEIVER R DELY ( t ) EUP ( t U:D ) Figur 4. Bus iming t F t HIGH t R t LOW t LOW L t U: t HD:D t HD: t U:D t U:O D IN t t DH t BUF D OU 2009 ILL. ll rights rsrvd. haractristics subjct to chang without notic. 5 Doc No. MD-1103, Rv. L

6 24128 WRIE OPERION Byt Writ Upon rciving a lav addrss with th R/W bit st to 0, th will intrprt th nxt two byts as addrss byts hs byts ar usd to initializ th intrnal addrss countr; th 2 most significant bits ar don t car, th nxt 8 point to on of 256 availabl pags and th last 6 point to a location within a 64 byt pag. byt following th addrss byts will b intrprtd as data. h data will b loadd into th Pag Writ Buffr and will vntually b writtn to mmory at th addrss spcifid by th 14 activ addrss bits providd arlir. h will acknowldg th lav addrss, addrss byts and data byt. h Mastr thn starts th intrnal Writ cycl by issuing a OP condition (Figur 5). During th intrnal Writ cycl (t WR ), th D output will b tri-statd and additional Rad or Writ rqusts will b ignord (Figur 6). Hardwar Writ Protction With th WP pin hld HIGH, th ntir mmory is protctd against Writ oprations. If th WP pin is lft floating or is groundd, it has no impact on th opration of th h stat of th WP pin is strobd on th last falling dg of L immdiatly prcding th first data byt (Figur 8). If th WP pin is HIGH during th strob intrval, th will not acknowldg th data byt and th Writ rqust will b rjctd. Dlivry tat h is shippd rasd, i.., all byts ar FFh. Pag Writ By continuing to load data into th Pag Writ Buffr aftr th 1 st data byt and bfor issuing th OP condition, up to 64 byts can b writtn simultanously during on intrnal Writ cycl (Figur 7). If mor data byts ar loadd than locations availabl to th nd of pag, thn loading will continu from th bginning of pag, i.. th pag addrss is latchd and th addrss count automatically incrmnts to and thn wrapsaround at th pag boundary. Prviously loadd data can thus b ovrwrittn by nw data. What is vntually writtn to mmory rflcts th latst Pag Writ Buffr contnts. Only data loadd within th most rcnt Pag Writ squnc will b writtn to mmory. cknowldg Polling h rady/busy status of th can b ascrtaind by snding Rad or Writ rqusts immdiatly following th OP condition that initiatd th intrnal Writ cycl. s long as intrnal Writ is in progrss, th will not acknowldg th lav addrss. Doc. No. MD-1103, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic.

7 24128 Figur 5. Byt Writ qunc BU IVIY: MER LVE R LVE DDRE * = Don't ar Bit ** DDRE a13 a8 DDRE a7 a0 D O P P Figur 6. Writ ycl iming L D 8 th Bit Byt n t WR OP ONDIION R ONDIION DDRE Figur 7. Pag Writ qunc BU IVIY: MER LVE R * = Don't ar Bit P 63 LVE DDRE ** DDRE a 13 a 8 DDRE a 7 a 0 D n D n+1 D n+p O P P Figur 8. WP iming DDRE D L D a 7 a 0 d 7 d 0 tu:wp WP thd:wp 2009 ILL. ll rights rsrvd. haractristics subjct to chang without notic. 7 Doc No. MD-1103, Rv. L

8 24128 RED OPERION Immdiat Rad Upon rciving a lav addrss with th R/W bit st to 1, th will intrprt this as a rqust for data rsiding at th currnt byt addrss in mmory. h will acknowldg th lav addrss, will immdiatly shift out th data rsiding at th currnt addrss, and will thn wait for th Mastr to rspond. If th Mastr dos not acknowldg th data (No) and thn follows up with a OP condition (Figur 9), th rturns to tandby mod. lctiv Rad o rad data rsiding at a spcific location, th intrnal addrss countr must first b initializd as dscribd undr Byt Writ. If rathr than following up th two addrss byts with data, th Mastr instad follows up with an Immdiat Rad squnc, thn th will us th 14 activ addrs bits to initializ th intrnal addrss countr and will shift out data rsiding at th corrsponding location. If th Mastr dos not acknowldg th data (No) and thn follows up with a OP condition (Figur 10), th rturns to tandby mod. quntial Rad If during a Rad sssion th Mastr acknowldgs th 1 st data byt, thn th will continu transmitting data rsiding at subsqunt locations until th Mastr rsponds with a No, followd by a OP (Figur 11). In contrast to Pag Writ, during quntial Rad th addrss count will automatically incrmnt to and thn wrap-around at nd of mmory (rathr than nd of pag). Doc. No. MD-1103, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic.

9 24128 Figur 9. Immdiat Rad qunc and iming BU IVIY: MER R LVE DDRE N O O P P LVE D L 8 9 D 8 th Bit D OU NO OP Figur 10. lctiv Rad qunc BU IVIY: MER LVE R * = Don't ar Bit LVE DDRE ** DDRE a 13 a 8 DDRE a 7 a 0 R LVE DDRE D N O O P P Figur 11. quntial Rad qunc BU IVIY: MER LVE DDRE N O O P P LVE D D n n+1 D n+2 D n+x 2009 ILL. ll rights rsrvd. haractristics subjct to chang without notic. 9 Doc No. MD-1103, Rv. L

10 24128 PGE OULINE DRWING PDIP 8-Lad 300mils (L) PIN # 1 IDENIFIION D E1 YMBOL MIN NOM MX b b c D E B E B L OP VIEW E 2 1 L b2 c b B IDE VIEW END VIEW For currnt ap and Rl information, download th PDF fil from: Nots: 1. ll dimnsions ar in millimtrs. 2. omplis with JEDE M-001. Doc. No. MD-1103, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic.

11 24128 OI 8-Lad 150mils (W) PIN # 1 IDENIFIION E1 E YMBOL MIN NOM MX b c D E E B h L θ 0º 8º OP VIEW D h 1 θ b L c IDE VIEW END VIEW For currnt ap and Rl information, download th PDF fil from: Nots: 1. ll dimnsions ar in millimtrs. 2. omplis with JEDE M ILL. ll rights rsrvd. haractristics subjct to chang without notic. 11 Doc No. MD-1103, Rv. L

12 24128 OP 8-Lad 4.4mm (Y) b E1 E YMBOL MIN NOM MX b c D E E B L 1.00 REF L θ1 0 8 OP VIEW D 2 θ1 c 1 L1 L IDE VIEW END VIEW For currnt ap and Rl information, download th PDF fil from: Nots: 1. ll dimnsions ar in millimtrs. ngls in dgrs. 2. omplis with JEDE MO-153. Doc. No. MD-1103, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic.

13 24128 UDFN 8-Pad 2 x 3mm (HU3) D DEIL DP IZE 1.3 x 1.8 E E2 PIN #1 IDENIFIION PIN #1 INDEX RE 1 D2 OP VIEW IDE VIEW BOOM VIEW b YMBOL MIN NOM MX L REF DEIL b D D E E YP 0.10 REF L FRON VIEW For currnt ap and Rl information, download th PDF fil from: Nots: 1. ll dimnsions ar in millimtrs. 2. omplis with JEDE MO ILL. ll rights rsrvd. haractristics subjct to chang without notic. 13 Doc No. MD-1103, Rv. L

14 24128 MOP 8-Lad 3.0 x 3.0mm (Z) E E1 YMBOL MIN NOM MX b c D E E B L L REF L B θ 0º 6º OP VIEW D 2 DEIL 1 b c IDE VIEW END VIEW θ L2 L L1 DEIL For currnt ap and Rl information, download th PDF fil from: Nots: 1. ll dimnsions ar in millimtrs. ngls in dgrs. 2. omplis with JEDE MO-187. Doc. No. MD-1103, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic.

15 24128 EXMPLE OF ORDERING INFORMION Prfix Dvic # uffix Y I G 3 ompany ID Product Numbr mpratur Rang I = Industrial (-40 to +85 ) E = Extndd (-40 to +125 ) : ap & Rl 3: 3000/Rl Packag L: PDIP W: OI, JEDE Y: OP HU3: UDFN (2 x 3mm) Z: MOP Lad Finish G: NiPdu Blank: Matt-in ORDERING INFORMION Ordrabl Part Numbrs 24128LI-G 24128LE-G 24128WI-G WE-G YI-G YE-G HU3IG3* 24128HU3EG3* 24128ZI-G ZE-G3 * Part numbr is not xactly th sam as th Exampl of Ordring Information shown abov. For part numbrs markd with * thr ar NO hyphns in th ordrabl part numbrs. Nots: (1) ll packags ar RoH-compliant (Lad-fr, Halogn-fr). (2) h standard lad finish is NiPdu. (3) h dvic usd in th abov xampl is a 24128YI-G3 (OP, Industrial mpratur, NiPdu, ap & Rl, 3,000/Rl). (4) For additional packag and tmpratur options, plas contact your narst ON miconductor als offic ILL. ll rights rsrvd. haractristics subjct to chang without notic. 15 Doc No. MD-1103, Rv. L

16 24128 REVIION HIORY Dat Rvision Dscription 07-Oct-05 Initial Issu 16-Nov-05 B Updat Ordring Information dd ap and Rl pcifications 02-Fb-06 Updat.. haractristics Updat Ordring Information 13-Mar-06 D Updat.. haractristics 26-pr-06 E Updat Faturs Updat Dvic Dscription Updat Pin onfiguration Updat.. haractristics Updat Hardwar Writ Protcttion dd Figur 6a dd 8-Lad OP Packag Drawing Updat Ordring Information dd 8-Lad OP Packag Marking 19-May-06 F Updat Faturs Updat Dvic Dscription Updat Pin onfiguration Updat Ordring Information Updat D.. Oprating haractristics Updat Pin Impdanc haractristics Updat.. haractristics dd Powr-On Rst (POR) Updat 8-Lad PDIP Packag Drawing Updat 8-Lad OI Packag Drawing Updat 8-Lad OP Packag Drawing Updat ap and Rl 11-ug-06 G Updat Faturs Updat D.. Oprating haractristics Updat Pin Impdanc haractristics Updat.. st onditions Updat Powr-On Rst (POR) Updat Pin Dscription Updat I 2 Bus Protocol Updat Dvic ddrssing Updat cknowldg Updat Writ Oprations Updat Byt Writ Updat Pag Writ Updat cknowldg Polling dd Dlivry tat Updat Rad Oprations Updat lctiv Rad Updat quntial Rad Updat Figur 1, 2, 3, 5, 6, 6a, 7, 8, 9 and 10 Updat Part Marking Updat Ordring Information 21-ug-07 H dd Extndd tmpratur rang Updat D.. Oprating haractristics tabl Updat Packag Outlin Drawings and add UDFN Packag Outlin Drawing dd MD- to documnt numbr 29-ug-07 I Updat UDFN Packag Outlin Drawing to includ dimnsion. 18-p-07 J dd MOP Packag Outlin Drawing 05-Nov-08 hang logo and fin print to ON miconductor 14-Jul-09 L Updat Ordring Information tabl Doc. No. MD-1103, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic.

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