100-Tap Digitally Programmable Potentiometer (DPP )

Transcription

1 00-Tap Digitally Programmabl Potntiomtr ( ) CAT FEATURES 00-position linar tapr potntiomtr Non-volatil EEPROM wipr storag 0 na ultra-low standby currnt Singl supply opration:. V.0 V Incrmnt up/down srial intrfac Rsistanc valus: kω, 0 kω, 0 kω and 00 kω Availabl in PDIP, SOIC, TSSOP and MSOP packags APPLICATIONS Automatd product calibration Rmot control adjustmnts Offst, gain and zro control Tampr-proof calibrations Contrast, brightnss and volum controls Motor controls and fdback systms Programmabl analog functions For Ordring Information dtails, s pag. DESCRIPTION Th CAT is a singl digitally programmabl potntiomtr ( ) dsignd as a lctronic rplacmnt for mchanical potntiomtrs. Idal for automatd adjustmnts on high volum production lins, thy ar also wll suitd for applications whr quipmnt rquiring priodic adjustmnt is ithr difficult to accss or locatd in a hazardous or rmot nvironmnt. Th CAT contains a 00-tap sris rsistor array connctd btwn two trminals R H and R L. An up/ down countr and dcodr that ar controlld by thr input pins, dtrmins which tap is connctd to th wipr, R W. Th wipr stting, stord in nonvolatil mmory, is not lost whn th dvic is powrd down and is automatically rinstatd whn powr is rturnd. Th wipr can b adjustd to tst nw systm valus without affcting th stord stting. Wipr-control of th CAT is accomplishd with thr input control pins, CS, U/D, and INC. Th INC input incrmnts th wipr in th dirction which is dtrmind by th logic stat of th U/D input. Th CS input is usd to slct th dvic and also stor th wipr position prior to powr down. Th digitally programmabl potntiomtr can b usd as a thr-trminal rsistiv dividr or as a twotrminal variabl rsistor. FUNCTIONAL DIAGRAM V CC U/D INC CS -BIT UP/DOWN COUNTER 0 R H R H R H 9 U/D INC CS Control and Mmory Powr On Rcall GND R W R L V CC GND -BIT NONVOLATILE MEMORY STORE AND RECALL CONTROL CIRCUITRY ONE OF THIRTY TWO DECODER 0 TRANSFER GATES RESISTOR ARRAY R L RW R W R L Gnral Dtaild Elctronic Potntiomtr Implmntation 009 SCILLC. All rights rsrvd. Doc. No. MD-009 Rv. Y

2 CAT PIN CONFIGURATION PDIP -Lad (L) SOIC Lad (V) MSOP Lad (Z) INC U/D R H GND CAT V CC CS R L R WB TSSOP Lad (Y) CS V CC INC U/D CAT R L R WB GND R H PIN DESCRIPTIONS Nam Function INC Incrmnt Control U/D Up/Down Control R H Potntiomtr High Trminal GND Ground R W Wipr Trminal R L Potntiomtr Low Trminal CS Chip Slct Supply Voltag V CC PIN DESCRIPTION INC : Incrmnt Control Input Th INC input movs th wipr in th up or down dirction dtrmind by th condition of th U/D input. U/D : Up/Down Control Input Th U/D input controls th dirction of th wipr movmnt. Whn in a high stat and CS is low, any high-to-low transition on INC will caus th wipr to mov on incrmnt toward th R H trminal. Whn in a low stat and CS is low, any high-to-low transition on INC will caus th wipr to mov on incrmnt towards th R L trminal. R H : High End Potntiomtr Trminal R H is th high nd trminal of th potntiomtr. It is not rquird that this trminal b connctd to a potntial gratr than th R L trminal. Voltag applid to th R H trminal cannot xcd th supply voltag, V CC or go blow ground, GND. R W : Wipr Potntiomtr Trminal R W is th wipr trminal of th potntiomtr. Its position on th rsistor array is controlld by th control inputs, INC, U/D and CS. Voltag applid to th R W trminal cannot xcd th supply voltag, V CC or go blow ground, GND. R L : Low End Potntiomtr Trminal R L is th low nd trminal of th potntiomtr. It is not rquird that this trminal b connctd to a potntial lss than th R H trminal. Voltag applid to th R L trminal cannot xcd th supply voltag, V CC or go blow ground, GND. R L and R H ar lctrically intrchangabl. CS : Chip Slct Th chip slct input is usd to activat th control input of th CAT and is activ low. Whn in a high stat, activity on th INC and U/D inputs will not affct or chang th position of th wipr. DEVICE OPERATION Th CAT oprats lik a digitally controlld potntiomtr with R H and R L quivalnt to th high and low trminals and R W quivalnt to th mcha nical potntiomtr's wipr. Thr ar 00 availabl tap positions including th rsistor nd points, R H and R L. Thr ar 99 rsistor lmnts connctd in sris btwn th R H and RL trminals. Th wipr trminal is connctd to on of th 00 taps and controlld by thr inputs, INC, U/D and CS. Ths inputs control a svn-bit up/down countr whos output is dcodd to slct th wipr position. Th slctd wipr position can b stord in non-volatil mmory using th INC and CS inputs. With CS st LOW th CAT is slctd and will rspond to th U/D and INC inputs. HIGH to LOW transitions on INC wil incrmnt or dcrmnt th wipr (dpnding on th stat of th U/D input and svn-bit countr). Th wipr, whn at ithr fixd trminal, acts lik its mchanical quivalnt and dos not mov byond th last position. Th valu of th countr is stord in nonvolatil mmory whnvr CS transitions HIGH whil th INC input is also HIGH. Whn th CAT is powrd-down, th last stord wipr countr position is maintaind in th nonvolatil mmory. Whn powr is rstord, th contnts of th mmory ar rcalld and th countr is st to th valu stord. With INC st low, th CAT may b d-slctd and powrd down without storing th currnt wipr position in nonvolatil mmory. This allows th systm to always powr up to a prst valu stord in non - volatil mmory. Doc. No. MD-009 Rv. Y 009 SCILLC. All rights rsrvd.

3 CAT OPERATION MODES INC CS U/D Opration High to Low Low High Wipr toward H High to Low Low Low Wipr toward L High Low to High X Stor Wipr Position Low Low to High X No Stor, Rturn to Standby X High X Standby ABSOLUTE MAXIMUM RATINGS () Paramtrs Ratings Units Supply Voltag V CC to GND -0. to V Inputs CS to GND -0. to V CC 0. V INC to GND -0. to V CC 0. V U/D to GND -0. to V CC 0. V H to GND -0. to V CC 0. V L to GND -0. to V CC 0. V W to GND -0. to V CC 0. V RELIABILITY CHARACTERISTICS Paramtrs Ratings Units Oprating Ambint Tmpratur Commrcial ( C or Blank suffix) 0 to 0 ºC Industrial ( I suffix) -0 to ºC Junction Tmpratur 0 ºC Storag Tmpratur - to 0 ºC Lad Soldring (0s max) 00 ºC Symbol Paramtr Tst Mthod Min Typ Max Units () V ZAP ESD Suscptibility MIL-STD-, Tst Mthod V () () I LTH Latch-Up JEDEC Standard 00 ma T DR Data Rtntion MIL-STD-, Tst Mthod Yars N END Enduranc MIL-STD-, Tst Mthod 00,000,000 Stors DC ELECTRICAL CHARACTERISTICS VCC =. V to V unlss othrwis spcifid Powr Supply Symbol Paramtr Conditions Min Typ Max Units V CC Oprating Voltag Rang..0 V I CC Supply Currnt (Incrmnt) V CC = V, f = MHz, I W = 0 00 µa V CC = V, f = 0 khz, I W = 0 0 µa I CC Supply Currnt (Writ) Programming, V CC = V 000 µa V CC = V 00 µa () CS = V I SB Supply Currnt (Standby) CC - 0. V U/D, INC = V CC - 0. V or GND 0.0 µa () Strsss abov thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. Ths ar strss ratings only, and functional opration of th dvic at ths or any othr conditions outsid of thos listd in th oprational sctions of this spcification is not implid. Exposur to any absolut maximum rating for xtndd priods may affct dvic prformanc and rliability. () This paramtr is tstd initially and aftr a dsign or procss chang that affcts th paramtr. () Latch-up protction is providd for strsss up to 00 ma on addrss and data pins from - V to V CC V () I W = sourc or sink () Ths paramtrs ar priodically sampld and ar not 00% tstd. 009 SCILLC. All rights rsrvd. Doc. No. MD-009 Rv. Y

4 CAT Logic Inputs Symbol Paramtr Conditions Min Typ Max Units I IH Input Lakag Currnt V IN = V CC 0 µa I IL Input Lakag Currnt V IN = 0 V -0 µa V IH CMOS High Lvl Input Voltag V CC x 0. V CC 0. V. V V CC V CMOS Low Lvl Input Voltag -0. V CC x 0. V V IL Potntiomtr Charactristics Symbol Paramtr Conditions Min Typ Max Units -0 Dvic R POT -0 Dvic 0 Potntiomtr Rsistanc kω -0 Dvic 0-00 Dvic 00 Pot. Rsistanc Tolranc ±0 % V RH Voltag on R H pin 0 V CC V V RL Voltag on R L pin 0 V CC V Rsolution % INL Intgral Linarity Error I W µa 0. LSB DNL Diffrntial Linarity Error I W µa LSB R WI I W V CC = V, I W = ma 00 Ω Wipr Rsistanc V CC =. V, I W = ma 000 Ω Wipr Currnt () -.. ma TC RPOT TC of Pot Rsistanc 00 ppm/ºc TC RATIO Ratiomtric TC 0 ppm/ºc V N Nois 00 khz / khz / nv/ Hz C H /C L /C W Potntiomtr Capacitancs // pf fc Frquncy Rspons Passiv Attnuator, 0 kω. MHz () This paramtr is not 00% tstd. Doc. No. MD-009 Rv. Y 009 SCILLC. All rights rsrvd.

5 CAT AC CONDITIONS OF TEST V CC Rang Input Puls Lvls Input Ris and Fall Tims Input Rfrnc Lvls. V V CC V 0.V CC to 0.V CC 0 ns 0.V CC AC OPERATING CHARACTERISTICS V CC =. V to.0 V, V H = V CC, V L = 0 V, unlss othrwis spcifid Symbol Paramtr Min Typ () Max Units t CI CS to INC Stup 00 ns t DI U/D to INC Stup 0 ns t ID U/D to INC Hold 00 ns t IL INC LOW Priod 0 ns t IH INC HIGH Priod 0 ns t IC INC Inactiv to CS Inactiv µs t CPH CS Dslct Tim (NO STORE) 00 ns t CPH CS Dslct Tim (STORE) 0 ms t IW INC to V OUT Chang µs t CYC INC Cycl Tim µs () t R, t F INC Input Ris and Fall Tim 00 µs () t PU Powr-up to Wipr Stabl ms t WR Stor Cycl 0 ms A.C. TIMING CS t (stor) CYC t IH t IC t CPH INC t CI til 90% 90% 0% U/D t DI t ID t F t R t IW MI () R W () Typical valus ar for T A = ºC and nominal supply voltag. () This paramtr is priodically sampld and not 00% tstd. () MI in th A.C. Timing diagram rfrs to th minimum incrmntal chang in th W output du to a chang in th wipr position. 009 SCILLC. All rights rsrvd. Doc. No. MD-009 Rv. Y

6 CAT APPLICATIONS INFORMATION Potntiomtr Configuration (a) rsistiv dividr (b) variabl rsistanc (c) two-port Applications V (-) CAT/ V () R R R R 9 R 0 R R A A = A = A = ¼ LM0 R = R = R = kω R POT = 0kΩ V O.V R A R B C R R pr POT 0.0µF 0.00µF (-p)r POT 0.0µF Programmabl Instrumntation Amplifir Programmabl Sq. Wav Oscillator () ICA ¼ HC V REF = V OSC 0kΩ ICB CS 0kΩ 0.0µF V CORR 99kΩ 99kΩ ICA V OUT = V ± mv -V 99kΩ 99kΩ V SENSOR = V ± 0mV 00mV CAT/ IC Snsor Snsor Auto Rfrncing Circuit Doc. No. MD-009 Rv. Y 009 SCILLC. All rights rsrvd.

7 CAT 00kΩ V OUT V O (REG) CAT/ V IN (UNREG) SHUTDOWN SD µf CAT/ 9 GND.V FB R kω R 0Ω R 0kΩ 0.µF.µF I S 0Ω pr (-p)r 0Ω MΩ 0k A A LT09 V O.V Programmabl Voltag Rgulator Programmabl I to V Convrtor IC HC IC 9 V LL R OSC CLO R 0kΩ 0.µF IC CAT/ 0kΩ CHI V S.V 0 V S.V AI IC Automatic Gain Control V UL R V O 0 V O.V V S µf C 0.00µF R 0kΩ CAT/ C 0.00µF R 0kΩ R 00kΩ Programmabl Bandpass Filtr A V O.V R 00kΩ Srial Bus CAT/ V S.V R 00kΩ R 00kΩ R.kΩ I S R 00kΩ.V A A =A = LMC0A Programmabl Currnt Sourc/Sink 009 SCILLC. All rights rsrvd. Doc. No. MD-009 Rv. Y

8 CAT PACKAGE OUTLINE DRAWINGS PDIP -Lad 00 mils (L) ()() PIN # IDENTIFICATION D E SYMBOL MIN NOM MAX A. A 0. A b b... c D E.... BSC E.0.. B. 0.9 L TOP VIEW E A A A L b c b B SIDE VIEW END VIEW () All dimnsions ar in millimtrs. () Complis with JEDEC Standard MS-00. Doc. No. MD-009 Rv. Y 009 SCILLC. All rights rsrvd.

9 CAT SOIC -Lad 0 mils (V) ()() SYMBOL MIN NOM MAX A.. A b PIN # IDENTIFICATION E E c D.0.00 E.0.0 E BSC h L 0.0. θ 0º º TOP VIEW D h A A θ c b L SIDE VIEW END VIEW () All dimnsions ar in millimtrs. Angls in dgrs. () Complis with JEDEC Spcification MS SCILLC. All rights rsrvd. 9 Doc. No. MD-009 Rv. Y

10 CAT TSSOP -Lad. mm (Y) ()() b E E SYMBOL MIN NOM MAX A.0 A A b c D E E BSC L.00 REF L θ 0 TOP VIEW D A A θ c A L L SIDE VIEW END VIEW () All dimnsions ar in millimtrs. () Complis with JEDEC Standard MO- Doc. No. MD-009 Rv. Y SCILLC. All rights rsrvd.

11 CAT MSOP -Lad.0 x.0 mm (Z) ()() E E SYMBOL MIN NOM MAX A.0 A A b c D E E BSC L L 0.9 REF L 0. BSC θ 0º º TOP VIEW D A A DETAIL A A b c SIDE VIEW END VIEW θ L L L DETAIL A () All dimnsions ar in millimtrs. Angls in dgrs. () Complis with JEDEC Spcification MS SCILLC. All rights rsrvd. Doc. No. MD-009 Rv. Y

12 CAT EXAMPLE OF ORDERING INFORMATION Prfix Dvic # Suffix CAT V I -0 G ()() T Optional Company ID Product Numbr Packag L: PDIP V: SOIC Y: TSSOP Z: MSOP Tmpratur Rang I = Industrial (-0ºC to ºC) Rsistanc -0: kω -0: 0 kω -0: 0 kω -00: 00 kω Tap & Rl T: Tap & Rl :,000/Rl Lad Finish Blank: Matt-Tin G: NiPdAu () All packags ar RoHS-compliant (Lad-fr, Halogn-fr). () Th standard lad finish is NiPdAu, xcpt MSOP packag is Matt-Tin. () Contact factory for Matt-Tin finish availability for PDIP, SOIC and TSSOP packags. () This dvic usd in th abov xampl is a CATVI-0-GT (SOIC, Industrial Tmpratur, 0 kω, NiPdAu, Tap & Rl,,000/Rl). ORDERING INFORMATION Ordrabl Part Numbr Rsistanc (kω) Packag-Pins Lad Finish CATLI-0-G CATLI-0-G 0 CATLI-0-G 0 PDIP- NiPdAu CATLI-00-G 00 CATVI-0-GT CATVI-0-GT 0 CATVI-0-GT 0 SOIC- NiPdAu CATVI-00-GT 00 CATYI-0-GT CATYI-0-GT 0 CATYI-0-GT 0 TSSOP- NiPdAu CATYI-00-GT 00 CATZI-0-T CATZI-0-T 0 CATZI-0-T 0 MSOP- Matt-Tin CATZI-00-T 00 Doc. No. MD-009 Rv. Y 009 SCILLC. All rights rsrvd.

13 CAT REVISION HISTORY Dat Rv. Dscription 09-Oct-0 M Rvisd Faturs Rvisd DC Elctrical Charactristics 0-Mar-0 N Updatd Potntiomtr Paramtrs 9-Mar-0 O Changd Grn Packag marking for SOIC from W to V 0-Apr-0 P Add kω vrsion to data sht 0-Apr-0 Q Eliminatd data sht dsignation Updatd Tap and Rl spcs in Ordring Information -Jan-0 R Updatd Potntiomtr Paramtrs -Apr-0 S Updatd Exampl of Ordring Information 0-Jun-0 T Addd Packag Outlin Addd MD- in front of Documnt No. -Fb-0 U Updat Logic Inputs tabl Updat Application Information (Snsor Auto Rfrncing Circuit and Programmabl Currnt Sourc/Sink) Updat Packag Outlin Drawings -Mar-0 V Updat Exampl of Ordring Information Dlt MSOP in NiPdAu platd finish Add Top Mark Cods link 0-Nov-0 X Chang logo and fin print to ON Smiconductor 0-Jul-09 Y Updat Ordring Information tabl ON Smiconductor and ar rgistrd tradmarks of Smiconductor Componnts Industris, LLC (SCILLC). SCILLC rsrvs th right to mak changs without furthr notic to any products hrin. SCILLC maks no warranty, rprsntation or guarant rgarding th suitability of its products for any particular purpos, nor dos SCILLC assum any liability arising out of th application or us of any product or circuit, and spcifically disclaims any and all liability, including without limitation spcial, consquntial or incidntal damags. Typical paramtrs which may b providd in SCILLC data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. All oprating paramtrs, including Typicals must b validatd for ach customr application by customr's tchnical xprts. SCILLC dos not convy any licns undr its patnt rights nor th rights of othrs. SCILLC products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th body, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th SCILLC product could crat a situation whr prsonal injury or dath may occur. Should Buyr purchas or us SCILLC products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold SCILLC and its officrs, mploys, subsidiaris, affiliats, and distributors harmlss against all claims, costs, damags, and xpnss, and rasonabl attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that SCILLC was nglignt rgarding th dsign or manufactur of th part. SCILLC is an Equal Opportunity/Affirmativ Action Employr. This litratur is subjct to all applicabl copyright laws and is not for rsal in any mannr. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Litratur Distribution Cntr for ON Smiconductor P.O. Box, Dnvr, Colorado 0 USA Phon: 0-- or Toll Fr USA/Canada Fax: 0-- or 00-- Toll Fr USA/Canada ordrlit@onsmi.com N. Amrican Tchnical Support: Toll Fr USA/Canada Europ, Middl East and Africa Tchnical Support: Phon: Japan Customr Focus Cntr: Phon: ---0 ON Smiconductor Wbsit: Ordr Litratur: For additional information, plas contact your local Sals Rprsntativ 009 SCILLC. All rights rsrvd. Doc. No. MD-009 Rv. Y