3-wire Serial EEPROMs AT93C56A AT93C66A. Advance Information. Features. Description. Pin Configurations. 2K (256 x 8 or 128 x 16)

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1 Faturs Low-voltag and Standard-voltag Opration 2.7 (V CC = 2.7V to 5.5V).8 (V CC =.8V to 5.5V) Usr-slctabl Intrnal Organization 2K: 256 x 8 or 28 x 6 4K: 52 x 8 or 256 x 6 3-wir Srial Intrfac Squntial Rad Opration 2 MHz Clock Rat (5V) Slf-timd Writ Cycl (0 ms Max) High Rliability Enduranc: Million Writ Cycls Data Rtntion: 00 Yars Automotiv Grad, Extndd Tmpratur, and Lad-fr/Halogn-fr Dvics Availabl 8-lad PP, 8-lad JEDEC SOIC, 8-lad EIAJ SOIC, 8-lad MAP, 8-lad TSSOP, and 8-ball dbga2 Packags 3-wir Srial EEPROMs 2K (256 x 8 or 28 x 6) 4K (52 x 8 or 256 x 6) Dscription Th AT93C56A/66A provids 2048/4096 bits of srial lctrically rasabl programmabl rad-only mmory (EEPROM) organizd as 28/256 words of 6 bits ach whn th ORG pin is connctd to VCC and 256/52 words of 8 bits ach whn it is tid to ground. Th dvic is optimizd for us in many industrial and commrcial applicatio whr low-powr and low-voltag opratio ar ssntial. Th AT93C56A/66A is availabl in spac-saving 8-lad PP, 8-lad JEDEC SOIC, 8-lad EIAJ SOIC, 8-lad MAP, 8-lad TSSOP, and 8-ball dbga2 packags. AT93C56A AT93C66A Advanc Information Pin Configuratio Pin Nam Function DO GND VCC Chip Slct Srial Data Clock Srial Data Input Srial Data Output Ground Powr Supply VCC DC ORG GND 8-ball dbga Bottom Viw DO DO 8-lad SOIC VCC DC ORG GND ORG Intrnal Organization DC DO Don t Connct 8-lad TSSOP VCC DC ORG GND VCC DC ORG GND 8-lad MAP Bottom Viw DO DO 8-lad PP VCC DC ORG GND Rv.

2 Absolut Maximum Ratings* Th AT93C56A/66A is nabld through th Chip Slct pin () and accssd via a 3-wir srial intrfac coisting of Data Input (), Data Output (DO), and Shift Clock (). Upon rciving a READ itruction at, th addrss is dcodd and th data is clockd out srially on th data output pin DO. Th WRITE cycl is compltly slftimd and no sparat ERASE cycl is rquird bfor WRITE. Th WRITE cycl is only nabld whn th part is in th ERASE/WRITE ENABLE stat. Whn is brought high following th initiation of a WRITE cycl, th DO pin outputs th READY/BUSY status of th part. Th AT93C56A/66A is availabl in 2.7V to 5.5V and.8v to 5.5V vrsio. Oprating Tmpratur C to +25 C Storag Tmpratur C to +50 C Voltag on Any Pin with Rspct to Ground....0V to +7.0V Maximum Oprating Voltag V *NOTICE: Strsss byond thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. This is a strss rating only, and functional opration of th dvic at ths or any othr conditio byond thos indicatd in th oprational sctio of this spcification is not implid. Exposur to absolut maximum rating conditio for xtndd priods may affct dvic rliability DC Output Currnt ma Block Diagram Not: Whn th ORG pin is connctd to VCC, th x 6 organization is slctd. Whn it is connctd to ground, th x 8 organization is slctd. If th ORG pin is lft unconnctd and th application dos not load th input byond th capability of th intrnal Mg ohm pullup, thn th x 6 organization is slctd. Th fatur is not availabl on th.8v dvics. 2

3 Pin Capacitanc () Applicabl ovr rcommndd oprating rang from T A = 25 C, f =.0 MHz, V CC = +5.0V (unlss othrwis notd). Symbol Tst Conditio Max Units Conditio C OUT Output Capacitanc (DO) 5 pf V OUT = 0V C IN Input Capacitanc (,, ) 5 pf V IN = 0V Not:. This paramtr is charactrizd and is not 00% tstd. DC Charactristics Applicabl ovr rcommndd oprating rang from: T AI = 40 C to +85 C, V CC = +.8V to +5.5V, T AE = 40 C to +25 C, V CC = +.8V to +5.5V (unlss othrwis notd). Symbol Paramtr Tst Condition Min Typ Max Unit V CC Supply Voltag V V CC2 Supply Voltag V V CC3 Supply Voltag V I CC Supply Currnt V CC = 5.0V Not:. V IL min and V IH max ar rfrnc only and ar not tstd. READ at.0 MHz ma WRITE at.0 MHz ma I SB Standby Currnt V CC =.8V = 0V 0 0. µa I SB2 Standby Currnt V CC = 2.7V = 0V µa I SB3 Standby Currnt V CC = 5.0V = 0V 7 30 µa I IL Input Lakag V IN = 0V to V CC µa I OL Output Lakag V IN = 0V to V CC µa () V IL () V IH () V IL2 () V IH2 V OL V OH V OL2 V OH2 Input Low Voltag Input High Voltag Input Low Voltag Input High Voltag Output Low Voltag Output High Voltag Output Low Voltag Output High Voltag.8V V CC 2.7V.8V V CC 2.7V V CC x V CC + V CC x 0.3 V CC + I OL = 2. ma 0.4 V I OH = 0.4 ma 2.4 V I OL = 0.5 ma 0.2 V I OH = 00 µa V CC 0.2 V V V 3

4 AC Charactristics Applicabl ovr rcommndd oprating rang from T AI = 40 C to + 85 C, T AE = 40 C to +25 C, V CC = As Spcifid, CL = TTL Gat and 00 pf (unlss othrwis notd). Symbol Paramtr Tst Condition Min Typ Max Units f Clock Frquncy 4.5V V CC 5.5V.8V V CC 5.5V MHz t H High Tim.8V V CC 5.5V t L Low Tim.8V V CC 5.5V t Minimum Low Tim.8V V CC 5.5V t S Stup Tim Rlativ to.8v V CC 5.5V t S Stup Tim Rlativ to.8v V CC 5.5V t H Hold Tim Rlativ to 0 t H Hold Tim Rlativ to.8v V CC 5.5V t PD Output Dlay to AC Tst.8V V CC 5.5V t PD0 Output Dlay to 0 AC Tst.8V V CC 5.5V t SV to Status Valid AC Tst.8V V CC 5.5V t DF to DO in High Impdanc AC Tst = V IL.8V V CC 5.5V t WP Writ Cycl Tim 0 ms 4.5V V CC 5.5V 0. 3 ms Enduranc () 5.0V, 25 C, Pag Mod M Writ Cycls Not:. This paramtr is charactrizd and is not 00% tstd. 4

5 Itruction St for th AT93C56A and AT93C66A Itruction Not: SB Op Cod Addrss Data x 8 x 6 x 8 x 6 Th X s in th addrss fild rprsnt don t car valus and must b clockd. Commnts READ 0 A 8 A 0 A 7 A 0 Rads data stord in mmory, at spcifid addrss. EWEN 00 XXXXXXX XXXXXX Writ nabl must prcd all programming mods. ERASE A 8 A 0 A 7 A 0 Erass mmory location A n A 0. WRITE 0 A 8 A 0 A 7 A 0 D 7 D 0 D 5 D 0 Writs mmory location A n A 0. ERAL 00 0XXXXXXX 0XXXXXX Erass all mmory locatio. Valid only at V CC = 4.5V to 5.5V. WRAL 00 0XXXXXXX 0XXXXXX D 7 D 0 D 5 D 0 only at V CC = 5.0V ±0% and Disabl Writs all mmory locatio. Valid Rgistr clard. EWDS 00 00XXXXXXX 00XXXXXX Disabls all programming itructio. Functional Dscription Th AT93C56A/66A is accssd via a simpl and vrsatil 3-wir srial communication intrfac. Dvic opration is controlld by svn itructio issud by th host procssor. A valid itruction starts with a rising dg of and coists of a Start Bit (logic ) followd by th appropriat Op Cod and th dsird mmory addrss location. READ (READ): Th Rad (READ) itruction contai th addrss cod for th mmory location to b rad. Aftr th itruction and addrss ar dcodd, data from th slctd mmory location is availabl at th srial output pin DO. Output data changs ar synchronizd with th rising dgs of srial clock. It should b notd that a dummy bit (logic 0 ) prcds th 8- or 6-bit data output string. Th AT93C56A/66A supports squntial rad opratio. Th dvic will automatically incrmnt th intrnal addrss pointr and clock out th nxt mmory location as long as Chip Slct () is hld high. In this cas, th dummy bit (logic 0 ) will not b clockd out btwn mmory locatio, thus allowing for a continuous stram of data to b rad. ERASE/WRITE (EWEN): To assur data intgrity, th part automatically gos into th Eras/Writ Disabl (EWDS) stat whn powr is first applid. An Eras/Writ Enabl (EWEN) itruction must b xcutd first bfor any programming itructio can b carrid out. Plas not that onc in th EWEN stat, programming rmai nabld until an EWDS itruction is xcutd or V CC powr is rmovd from th part. ERASE (ERASE): Th Eras (ERASE) itruction programs all bits in th spcifid mmory location to th logical stat. Th slf-timd ras cycl starts onc th ERASE itruction and addrss ar dcodd. Th DO pin outputs th READY/BUSY status of th part if is brought high aftr bing kpt low for a minimum of 250 (t ). A logic at pin DO indicats that th slctd mmory location has bn rasd, and th part is rady for anothr itruction. 5

6 WRITE (WRITE): Th Writ (WRITE) itruction contai th 8 or 6 bits of data to b writtn into th spcifid mmory location. Th slf-timd programming cycl t WP starts aftr th last bit of data is rcivd at srial data input pin. Th DO pin outputs th READY/BUSY status of th part if is brought high aftr bing kpt low for a minimum of 250 (t ). A logic 0 at DO indicats that programming is still in progrss. A logic indicats that th mmory location at th spcifid addrss has bn writtn with th data pattrn containd in th itruction and th part is rady for furthr itructio. A READY/BUSY status cannot b obtaind if th is brought high aftr th nd of th slf-timd programming cycl t WP. ERASE ALL (ERAL): Th Eras All (ERAL) itruction programs vry bit in th mmory array to th logic stat and is primarily usd for tsting purposs. Th DO pin outputs th READY/BUSY status of th part if is brought high aftr bing kpt low for a minimum of 250 (t ). Th ERAL itruction is valid only at V CC = 5.0V ± 0%. WRITE ALL (WRAL): Th Writ All (WRAL) itruction programs all mmory locatio with th data pattr spcifid in th itruction. Th DO pin outputs th READY/BUSY status of th part if is brought high aftr bing kpt low for a minimum of 250 (t ). Th WRAL itruction is valid only at V CC = 5.0V ± 0%. ERASE/WRITE SABLE (EWDS): To protct agait accidntal data disturb, th Eras/Writ Disabl (EWDS) itruction disabls all programming mods and should b xcutd aftr all programming opratio. Th opration of th READ itruction is indpndnt of both th EWEN and EWDS itructio and can b xcutd at any tim. Timing Diagrams Synchronous Data Timing Not:. This is th minimum priod. 6

7 Organization Ky for Timing Diagrams AT93C56A (2K) Nots:. A 8 is a DON T CARE valu, but th xtra clock is rquird. 2. A 7 is a DON T CARE valu, but th xtra clock is rquird. AT93C66A (4K) I/O x 8 x 6 x 8 x 6 A N () A 8 (2) A 7 A 8 A 7 D N D 7 D 5 D 7 D 5 READ Timing t High Impdanc EWEN Timing t

8 EWDS Timing t WRITE Timing t 0 A N... A0 D N... D0 DO HIGH IMPEDANCE BUSY READY t WP WRAL Timing () t D N... D0 O HIGH IMPEDANCE BUSY READY t WP Not:. Valid only at V CC = 4.5V to 5.5V. 8

9 ERASE Timing t CHECK STATUS STANDBY A N- A N-2... A0 A N t SV t DF DO HIGH IMPEDANCE BUSY READY HIGH IMPEDANCE t WP ERAL Timing () t CHECK STATUS STANDBY t SV t DF DO HIGH IMPEDANCE BUSY HIGH IMPEDANCE READY t WP Not:. Valid only at V CC = 4.5V to 5.5V. 9

10 AT93C56A Ordring Information Ordring Cod Packag Opration Rang AT93C56A-0PI-2.7 AT93C56A-0SI-2.7 AT93C56AW-0SI-2.7 AT93C56A-0TI-2.7 AT93C56AU3-0UI-2.7 AT93C56AY-0YI-2.7 8P3 8S2 8U3-8Y Industrial Tmpratur ( 40 C to 85 C) AT93C56A-0PI-.8 AT93C56A-0SI-.8 AT93C56AW-0SI-.8 AT93C56A-0TI-.8 AT93C56AU3-0UI-.8 AT93C56AY-0YI-.8 AT93C56A-0SU-2.7 AT93C56A-0SU-.8 AT93C56A-0TU-2.7 AT93C56A-0TU-.8 AT93C56A-0SQ-2.7 AT93C56A-0SE-2.7 Not: 8P3 8S2 8U3-8Y Industrial Tmpratur ( 40 C to 85 C) For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabl. Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) Lad-fr/Halogn-fr/ High Grad/Extndd Tmpratur ( 40 C to 25 C) High Grad/Extndd Tmpratur ( 40 C to 25 C) Packag Typ 8P3 8S2 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PP) 8-lad, 0.50" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 0.200" Wid, Plastic Gull Wing Small Outlin (EIAJ SOIC) 8-lad, 0.70 Wid, Thin Shrink Small Outlin Packag (TSSOP) 8U3-8-ball, di Ball Grid Array Packag (dbga2) 8Y 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) Optio 2.7 Low-voltag (2.7V to 5.5V).8 Low-voltag (.8V to 5.5V) 0

11 AT93C66A Ordring Information Ordring Cod Packag Opration Rang AT93C66A-0PI-2.7 AT93C66A-0SI-2.7 AT93C66AW-0SI-2.7 AT93C66A-0TI-2.7 AT93C66AU3-0UI-2.7 AT93C66AY-0YI-2.7 8P3 8S2 8U3-8Y Industrial ( 40 C to 85 C) AT93C66A-0PI-.8 AT93C66A-0SI-.8 AT93C66AW-0SI-.8 AT93C66A-0TI-.8 AT93C66AU3-0UI-.8 AT93C66AY-0YI-.8 AT93C66A-0SU-2.7 AT93C66A-0SU-.8 AT93C66A-0TU-2.7 AT93C66A-0TU-.8 AT93C66A-0SQ-2.7 AT93C66A-0SE-2.7 Not: 8P3 8S2 8U3-8Y Industrial ( 40 C to 85 C) For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabl. Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) Lad-fr/Halogn-fr/ High Grad/Extndd Tmpratur ( 40 C to 25 C) High Grad/Extndd Tmpratur ( 40 C to 25 C) Packag Typ 8P3 8S2 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PP) 8-lad, 0.50" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 0.200" Wid, Plastic Gull Wing Small Outlin (EIAJ SOIC) 8-lad, 0.70" Wid, Thin Shrink Small Outlin Packag (TSSOP) 8U3-8-ball, di Ball Grid Array Packag (dbga2) 8Y 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) Optio 2.7 Low-voltag (2.7V to 5.5V).8 Low-voltag (.8V to 5.5V)

12 Packaging Information 8P3 PP E E N Top Viw c A End Viw D D A2 A COMMON MENSIONS (Unit of Masur = inchs) SYMBOL MIN NOM MAX NOTE A A b b b c b3 4 PL b2 b L D D E E Sid Viw 0.00 BSC A BSC 4 L Nots: R. This drawing is for gnral information only; rfr to JEDEC Drawing MS-00, Variation BA for additional information. 2. Dimio A and L ar masurd with th packag satd in JEDEC sating plan Gaug GS D, D and E dimio do not includ mold Flash or protrusio. Mold Flash or protrusio shall not xcd 0.00 inch. 4. E and A masurd with th lads cotraind to b prpndicular to datum. 5. Pointd or roundd lad tips ar prfrrd to as irtion. 6. b2 and b3 maximum dimio do not includ Dambar protrusio. Dambar protrusio shall not xcd 0.00 (0.25 mm) Orchard Parkway San Jos, CA 953 TITLE 8P3, 8-lad, 0.300" Wid Body, Plastic Dual In-lin Packag (PP) DRAWING NO. 8P3 0/09/02 REV. B 2

13 JEDEC SOIC C E E N L Top Viw End Viw B A COMMON MENSIONS (Unit of Masur = mm) D Sid Viw A SYMBOL MIN NOM MAX NOTE A A b C D E E BSC L Not: Ths drawings ar for gnral information only. Rfr to JEDEC Drawing MS-02, Variation AA for propr dimio, tolrancs, datums, tc. 0/7/03 R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE, 8-lad (0.50" Wid Body), Plastic Gull Wing Small Outlin (JEDEC SOIC) DRAWING NO. REV. B 3

14 8S2 EIAJ SOIC C E E N L Top Viw D Sid Viw b A A End Viw COMMON MENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A A b C D E , 3 E L BSC 4 Nots:. This drawing is for gnral information only; rfr to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of th uppr and lowr dis and rsin burrs ar not includd. 3. It is rcommndd that uppr and lowr cavitis b qual. If thy ar diffrnt, th largr dimion shall b rgardd. 4. Dtrmi th tru gomtric position. 5. Valus b and C apply to pb/sn soldr platd trminal. Th standard thicks of th soldr layr shall b / mm. R 2325 Orchard Parkway San Jos, CA 953 TITLE 8S2, 8-lad, 0.209" Body, Plastic Small Outlin Packag (EIAJ) DRAWING NO. 8S2 0/7/03 REV. C 4

15 TSSOP 3 2 Pin indicator this cornr E E L N Top Viw L End Viw b D Sid Viw A2 A COMMON MENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE D , 5 E 6.40 BSC E , 5 A.20 A b BSC L L.00 REF Nots:. This drawing is for gnral information only. Rfr to JEDEC Drawing MO-53, Variation AA, for propr dimio, tolrancs, datums, tc. 2. Dimion D dos not includ mold Flash, protrusio or gat burrs. Mold Flash, protrusio and gat burrs shall not xcd 0.5 mm (0.006 in) pr sid. 3. Dimion E dos not includ intr-lad Flash or protrusio. Intr-lad Flash and protrusio shall not xcd 0.25 mm (0.00 in) pr sid. 4. Dimion b dos not includ Dambar protrusion. Allowabl Dambar protrusion shall b 0.08 mm total in xcss of th b dimion at maximum matrial condition. Dambar cannot b locatd on th lowr radius of th foot. Minimum spac btwn protrusion and adjacnt lad is 0.07 mm. 5. Dimion D and E to b dtrmind at Datum Plan H. 5/30/02 R 2325 Orchard Parkway San Jos, CA 953 TITLE, 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) DRAWING NO. REV. B 5

16 8U3- dbga2 E D. b PIN BALL PAD CORNER Top Viw A 2 A A (d) PIN BALL PAD CORNER Sid Viw d () 8 Bottom Viw 8 SOLDER BALLS. Dimion 'b' is masurd at th maximum soldr ball diamtr. This drawing is for gnral information only COMMON MENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A A A b D.50 BSC E 2.00 BSC 0.50 BSC 0.25 REF d.00 BSC d 0.25 REF R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE 8U3-, 8-ball,.50 x 2.00 mm Body, 0.50 mm pitch, Small Di Ball Grid Array Packag (dbga2) 6/24/03 DRAWING NO. REV. PO8U3- A 6

17 8Y MAP PIN INDEX AREA A PIN INDEX AREA E D D L E A b Top Viw End Viw Bottom Viw Sid Viw A COMMON MENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A 0.90 A D E D E b TYP L /28/03 R 2325 Orchard Parkway San Jos, CA 953 TITLE 8Y, 8-lad (4.90 x 3.00 mm Body) MSOP Array Packag (MAP) Y DRAWING NO. 8Y REV. C 7

18 Atml Corporation 2325 Orchard Parkway San Jos, CA 953, USA Tl: (408) Fax: (408) Rgional Hadquartrs Europ Atml Sarl Rout ds Arsnaux 4 Cas Postal 80 CH-705 Fribourg Switzrland Tl: (4) Fax: (4) Asia Room 29 Chinachm Goldn Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tl: (852) Fax: (852) Japan 9F, Tontsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo Japan Tl: (8) Fax: (8) Atml Opratio Mmory 2325 Orchard Parkway San Jos, CA 953, USA Tl: (408) Fax: (408) Microcontrollrs 2325 Orchard Parkway San Jos, CA 953, USA Tl: (408) Fax: (408) La Chantrri BP Nants Cdx 3, Franc Tl: (33) Fax: (33) ASIC/ASSP/Smart Cards Zon Industrill 306 Rousst Cdx, Franc Tl: (33) Fax: (33) East Chynn Mtn. Blvd. Colorado Springs, CO 80906, USA Tl: (79) Fax: (79) Scottish Entrpris Tchnology Park Maxwll Building East Kilbrid G75 0QR, Scotland Tl: (44) Fax: (44) RF/Automotiv Thrsitrass 2 Postfach Hilbronn, Grmany Tl: (49) Fax: (49) East Chynn Mtn. Blvd. Colorado Springs, CO 80906, USA Tl: (79) Fax: (79) Biomtrics/Imaging/Hi-Rl MPU/ High Spd Convrtrs/RF Datacom Avnu d Rochplin BP Saint-Egrv Cdx, Franc Tl: (33) Fax: (33) Litratur Rqusts Disclaimr: Atml Corporation maks no warranty for th us of its products, othr than thos xprssly containd in th Company s standard warranty which is dtaild in Atml s Trms and Conditio locatd on th Company s wb sit. Th Company assums no rspoibil ity for any rrors which may appar in this documnt, rsrvs th right to chang dvics or spcificatio dtaild hrin at any tim without notic, and dos not mak any commitmnt to updat th information containd hrin. No lics to patnts or othr intllctual proprty of Atml ar grantd by th Company in connction with th sal of Atml products, xprssly or by implication. Atml s products ar not authorizd for us as critical componnts in lif support dvics or systms. Atml Corporation All rights rsrvd. Atml and combinatio throf, ar th rgistrd tradmarks, and dbga is th tradmark of Atml Corporation or its subsidiaris. Othr trms and product nams may b th tradmarks of othrs. Printd on rcycld papr. xm