Three-wire Serial EEPROMs AT93C46 AT93C56 (1) AT93C66 (2)

Transcription

1 Faturs Low-voltag and Standard-voltag Opration 2.7 (V CC = 2.7V to 5.5V).8 (V CC =.8V to 5.5V) Usr-slctabl Intrnal Organization K: 28 x 8 or 64 x 6 2K: 256 x 8 or 28 x 6 4K: 52 x 8 or 256 x 6 Thr-wir Srial Intrfac 2 MHz Clock Rat (5V) Slf-timd Writ Cycl (0 ms max) High Rliability Enduranc: Million Writ Cycls Data Rtntion: 00 Yars Automotiv Grad, Extndd Tmpratur and Lad-Fr/Halogn-Fr Dvics Availabl 8-lad PDIP, 8-lad JEDEC SOIC, 8-lad EIAJ SOIC, 8-lad MAP, 8-lad TSSOP, and 8-ball dbga2 Packags Dscription Th AT93C46/56/66 provids 024/2048/4096 bits of srial lctrically rasabl programmabl rad-only mmory (EEPROM), organizd as 64/28/256 words of 6 bits ach (whn th ORG pin is connctd to VCC), and 28/256/52 words of 8 bits ach (whn th ORG pin is tid to ground). Th dvic is optimizd for us in many industrial and commrcial applications whr low-powr and low-voltag oprations ar ssntial. Th AT93C46/56/66 is availabl in spac-saving 8-lad PDIP, 8-lad JEDEC SOIC, 8-lad EIAJ SOIC, 8-lad MAP, 8-lad TSSOP, and 8-lad dbga2 packags. Th AT93C46/56/66 is nabld through th Chip Slct pin () and accssd via a thr-wir srial intrfac consisting of Data Input (DI), Data Output (DO), and Shift Clock (). Upon rciving a Rad instruction at DI, th addrss is dcodd and th data is clockd out srially on th DO pin. Th Writ cycl is compltly slf-timd, and no sparat Eras cycl is rquird bfor Writ. Th Writ cycl is only nabld whn th part is in th Eras/Writ Enabl stat. Whn is brought high following th initiation of a Writ cycl, th DO pin outputs th Rady/Busy status of th part. Th AT93C46/56/66 is availabl in 2.7V to 5.5V and.8v to 5.5V vrsions. Tabl. Pin Configurations Pin Nam Function Chip Slct Srial Data Clock DI DO 8-lad SOIC VCC DC ORG GND VCC DC ORG GND 8-lad dbga D D0 Thr-wir Srial EEPROMs K (28 x 8 or 64 x 6) 2K (256 x 8 or 28 x 6) 4K (52 x 8 or 256 x 6) AT93C46 AT93C56 () AT93C66 (2) Not:. This dvic is not rcommndd for nw dsigns. Plas rfr to AT93C56A. 2. This dvic is not rcommndd for nw dsigns. Plas rfr to AT93C66A. DI DO GND VCC Srial Data Input Srial Data Output Ground Powr Supply DI DO 8-lad PDIP VCC DC ORG GND DC VCC 8-lad SOIC Rotatd (R) (K JEDEC Only) ORG GND DO DI ORG DC Intrnal Organization Don t Connct VCC 8 DC 7 ORG 6 GND 5 8-lad MAP 2 3 DI 4 DO DI DO 8-lad TSSOP VCC DC ORG GND

2 Absolut Maximum Ratings* Oprating Tmpratur C to +25 C Storag Tmpratur C to +50 C Voltag on Any Pin with Rspct to Ground....0V to +7.0V Maximum Oprating Voltag V *NOTICE: Strsss byond thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. This is a strss rating only, and functional opration of th dvic at ths or any othr conditions byond thos indicatd in th oprational sctions of this spcification is not implid. Exposur to absolut maximum rating conditions for xtndd priods may affct dvic rliability DC Output Currnt ma Figur. Block Diagram Not: Whn th ORG pin is connctd to VCC, th x 6 organization is slctd. Whn it is connctd to ground, th x 8 organization is slctd. If th ORG pin is lft unconnctd and th application dos not load th input byond th capability of th intrnal Mg ohm pullup, thn th x 6 organization is slctd. Th fatur is not availabl on th.8v dvics. For th AT93C46, if x 6 organization is th mod of choic and Pin 6 (ORG) is lft unconnctd, Atml rcommnds using th AT93C46A dvic. For mor dtails, s th AT93C46A datasht. 2 AT93C46/56/66

3 AT93C46/56/66 Tabl 2. Pin Capacitanc () Applicabl ovr rcommndd oprating rang from T A = 25 C, f =.0 MHz, V CC = +5.0V (unlss othrwis notd) Symbol Tst Conditions Max Units Conditions C OUT Output Capacitanc (DO) 5 pf V OUT = 0V C IN Input Capacitanc (,, DI) 5 pf V IN = 0V Not:. This paramtr is charactrizd and is not 00% tstd. Tabl 3. DC Charactristics Applicabl ovr rcommndd oprating rang from: T AI = 40 C to +85 C, V CC = +.8V to +5.5V, T AE = -40 C to +25 C, V CC = +.8V to +5.5V (unlss othrwis notd) Symbol Paramtr Tst Condition Min Typ Max Unit V CC Supply Voltag V V CC2 Supply Voltag V V CC3 Supply Voltag V I CC Supply Currnt V CC = 5.0V Not:. V IL min and V IH max ar rfrnc only and ar not tstd. READ at.0 MHz ma WRITE at.0 MHz ma I SB Standby Currnt V CC =.8V = 0V 0 0. µa I SB2 Standby Currnt V CC = 2.7V = 0V µa I SB3 Standby Currnt V CC = 5.0V = 0V 7 30 µa I IL Input Lakag V IN = 0V to V CC 0..0 µa I OL Output Lakag V IN = 0V to V CC 0..0 µa V IL () Input Low Voltag () V IH Input High Voltag 2.0 V CC + Input Low Voltag 0.6 V CC x 0.3.8V V CC 2.7V () V IH2 Input High Voltag V CC x 0.7 V CC + V IL2 () V OL Output Low Voltag I OL = 2. ma 0.4 V V OH Output High Voltag I OH = 0.4 ma 2.4 V V OL2 Output Low Voltag I OL = 0.5 ma 0.2 V.8V V CC 2.7V V OH2 Output High Voltag I OH = 00 µa V CC 0.2 V V V 3

4 Tabl 4. AC Charactristics Applicabl ovr rcommndd oprating rang from T AI = 40 C to + 85 C, V CC = As Spcifid, CL = TTL Gat and 00 pf (unlss othrwis notd) Symbol Paramtr Tst Condition Min Typ Max Units f t H t L t Clock Frquncy High Tim Low Tim Minimum Low Tim 4.5V V CC 5.5V.8V V CC 5.5V 4.5V V CC 5.5V.8V V CC 5.5V 4.5V V CC 5.5V.8V V CC 5.5V 4.5V V CC 5.5V.8V V CC 5.5V t S Stup Tim Rlativ to t DIS DI Stup Tim Rlativ to Not:. This paramtr is charactrizd and is not 00% tstd. 4.5V V CC 5.5V.8V V CC 5.5V 4.5V V CC 5.5V.8V V CC 5.5V t H Hold Tim Rlativ to 0 ns t DIH DI Hold Tim Rlativ to t PD t PD0 t SV t DF t WP Output Dlay to Output Dlay to 0 to Status Valid to DO in High Impdanc Writ Cycl Tim AC Tst AC Tst AC Tst 4.5V V CC 5.5V.8V V CC 5.5V 4.5V V CC 5.5V.8V V CC 5.5V 4.5V V CC 5.5V.8V V CC 5.5V 4.5V V CC 5.5V.8V V CC 5.5V 4.5V V AC Tst CC 5.5V 2.7V V = V CC 5.5V IL.8V V CC 5.5V MHz ns ns ns ns ns ns ns ns ns ns 0 ms 4.5V V CC 5.5V 0. 3 ms Enduranc () 5.0V, 25 C M Writ Cycls 4 AT93C46/56/66

5 AT93C46/56/66 Tabl 5. Instruction St for th AT93C46 Instruction Not: SB Op Cod Addrss Data x 8 x 6 x 8 x 6 Th Xs in th addrss fild rprsnt DON T CARE valus and must b clockd. Commnts READ 0 A 6 A 0 A 5 A 0 Rads data stord in mmory, at spcifid addrss EWEN 00 XXXXX XXXX Writ nabl must prcd all programming mods ERASE A 6 A 0 A 5 A 0 Erass mmory location A n A 0 WRITE 0 A 6 A 0 A 5 A 0 D 7 D 0 D 5 D 0 Writs mmory location A n A 0 Erass all mmory locations. Valid ERAL 00 0XXXXX 0XXXX only at V CC = 4.5V to 5.5V Writs all mmory locations. Valid WRAL 00 0XXXXX 0XXXX D 7 D 0 D 5 D 0 only at V CC = 4.5V to 5.5V EWDS 00 00XXXXX 00XXXX Disabls all programming instructions Tabl 6. Instruction St for th AT93C56 () and AT93C66 (2) Instruction SB Op Cod Addrss Data x 8 x 6 x 8 x 6 Nots:. This dvic is not rcommndd for nw dsigns. Plas rfr to AT93C56A. 2. This dvic is not rcommndd for nw dsigns. Plas rfr to AT93C66A. Commnts READ 0 A 8 A 0 A 7 A 0 Rads data stord in mmory, at spcifid addrss EWEN 00 XXXXXXX XXXXXX Writ nabl must prcd all programming mods ERASE A 8 A 0 A 7 A 0 Erass mmory location A n A 0 WRITE 0 A 8 A 0 A 7 A 0 D 7 D 0 D 5 D 0 Writs mmory location A n A 0 ERAL 00 0XXXXXXX 0XXXXXX Erass all mmory locations. Valid only at V CC = 4.5V to 5.5V WRAL 00 0XXXXXXX 0XXXXXX D 7 D 0 D 5 D 0 only at V CC = 5.0V ±0% and Disabl Writs all mmory locations. Valid Rgistr clard EWDS 00 00XXXXXXX 00XXXXXX Disabls all programming instructions 5

6 Functional Dscription Th AT93C46/56/66 is accssd via a simpl and vrsatil thr-wir srial communication intrfac. Dvic opration is controlld by svn instructions issud by th host procssor. A valid instruction starts with a rising dg of and consists of a start bit (logic ) followd by th appropriat op cod and th dsird mmory addrss location. READ (READ): Th Rad (READ) instruction contains th addrss cod for th mmory location to b rad. Aftr th instruction and addrss ar dcodd, data from th slctd mmory location is availabl at th srial output pin DO. Output data changs ar synchronizd with th rising dgs of srial clock. It should b notd that a dummy bit (logic 0 ) prcds th 8- or 6-bit data output string. ERASE/WRITE ENABLE (EWEN): To assur data intgrity, th part automatically gos into th Eras/Writ Disabl (EWDS) stat whn powr is first applid. An Eras/Writ Enabl (EWEN) instruction must b xcutd first bfor any programming instructions can b carrid out. Plas not that onc in th EWEN stat, programming rmains nabld until an EWDS instruction is xcutd or V CC powr is rmovd from th part. ERASE (ERASE): Th Eras (ERASE) instruction programs all bits in th spcifid mmory location to th logical stat. Th slf-timd ras cycl starts onc th Eras instruction and addrss ar dcodd. Th DO pin outputs th Rady/Busy status of th part if is brought high aftr bing kpt low for a minimum of ns (t ). A logic at pin DO indicats that th slctd mmory location has bn rasd and th part is rady for anothr instruction. WRITE (WRITE): Th Writ (WRITE) instruction contains th 8 or 6 bits of data to b writtn into th spcifid mmory location. Th slf-timd programming cycl t WP starts aftr th last bit of data is rcivd at srial data input pin DI. Th DO pin outputs th Rad/Busy status of th part if is brought high aftr bing kpt low for a minimum of ns (t ). A logic 0 at DO indicats that programming is still in progrss. A logic indicats that th mmory location at th spcifid addrss has bn writtn with th data pattrn containd in th instruction and th part is rady for furthr instructions. A Rady/Busy status cannot b obtaind if th is brought high aftr th nd of th slftimd programming cycl twp. ERASE ALL (ERAL): Th Eras All (ERAL) instruction programs vry bit in th mmory array to th logic stat and is primarily usd for tsting purposs. Th DO pin outputs th Rady/Busy status of th part if is brought high aftr bing kpt low for a minimum of ns (t ). Th ERAL instruction is valid only at V CC = 5.0V ± 0%. WRITE ALL (WRAL): Th Writ All (WRAL) instruction programs all mmory locations with th data pattrns spcifid in th instruction. Th DO pin outputs th Rady/Busy status of th part if is brought high aftr bing kpt low for a minimum of ns (t ). Th WRAL instruction is valid only at V CC = 5.0V ± 0%. ERASE/WRITE DISABLE (EWDS): To protct against accidntal data disturb, th Eras/Writ Disabl (EWDS) instruction disabls all programming mods and should b xcutd aftr all programming oprations. Th opration of th Rad instruction is indpndnt of both th EWEN and EWDS instructions and can b xcutd at any tim. 6 AT93C46/56/66

7 AT93C46/56/66 Timing Diagrams Figur 2. Synchronous Data Timing µs Not:. This is th minimum priod. Tabl 7. Organization Ky for Timing Diagrams AT93C46 (K) AT93C56 (2K) () AT93C66 (4K) (2) I/O x 8 x 6 x 8 x 6 x 8 x 6 A N A 6 A 5 A 8 (3) A 7 (4) A 8 A 7 D N D 7 D 5 D 7 D 5 D 7 D 5 Nots:. This dvic is not rcommndd for nw dsigns. Plas rfr to AT93C56A. 2. This dvic is not rcommndd for nw dsigns. Plas rfr to AT93C66A. 3. A 8 is a don t car valu, but th xtra clock is rquird. 4. A 7 is a don t car valu, but th xtra clock is rquird. 7

8 Figur 3. READ Timing t High Impdanc Figur 4. EWEN Timing t DI Figur 5. EWDS Timing t DI AT93C46/56/66

9 AT93C46/56/66 Figur 6. WRITE Timing t DI 0 A N... A0 D N... D0 DO HIGH IMPEDANCE BUSY READY t WP Figur 7. WRAL Timing () t DI D N... D0 DO HIGH IMPEDANCE BUSY READY t WP Not:. Valid only at V CC = 4.5V to 5.5V. Figur 8. ERASE Timing t CHECK STATUS STANDBY DI A N- A N-2... A0 A N t SV t DF DO HIGH IMPEDANCE BUSY READY HIGH IMPEDANCE t WP 9

10 Figur 9. ERAL Timing () t CHECK STATUS STANDBY DI t SV t DF DO HIGH IMPEDANCE BUSY HIGH IMPEDANCE READY t WP Not:. Valid only at V CC = 4.5V to 5.5V. 0 AT93C46/56/66

11 AT93C46/56/66 AT93C46 Ordring Information () Ordring Cod Packag Opration Rang AT93C46-0PI-2.7 AT93C46-0SI-2.7 AT93C46R-0SI-2.7 AT93C46W-0SI-2.7 AT93C46-0TI-2.7 AT93C46-0PI-.8 AT93C46-0SI-.8 AT93C46R-0SI-.8 AT93C46W-0SI-.8 AT93C46-0TI-.8 AT93C46-0PU-2.7 AT93C46-0PU-.8 AT93C46-0SU-2.7 AT93C46-0SU-.8 AT93C46W-0SU-2.7 AT93C46W-0SU-.8 AT93C46-0TU-2.7 AT93C46-0TU-.8 AT93C46Y-0YU-2.7 AT93C46Y-0YU-.8 AT93C46Y5-0YU-2.7 AT93C46Y5-0YU-.8 AT93C46U3-0UU-2.7 AT93C46U3-0UU-.8 AT93C46-W2.7- (2) AT93C46-W.8- (2) Nots:. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th Tabl 3 on pag 3 and Tabl 4 on pag Availabl in waffl pack and wafr form, ordr as SL79 for wafr form. Bumpd di availabl upon rqust. 8Y 8Y 8Y5 8Y5 8U3-8U3- Di Sal Di Sal Industrial ( 40 C to 85 C) Industrial ( 40 C to 85 C) Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) Industrial ( 40 C to 85 C) Packag Typ 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8-lad, 0.50" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 0.200" Wid, Plastic Gull Wing Small Outlin (EIAJ SOIC) 8-lad, 0.70" Wid, Thin Shrink Small Outlin Packag (TSSOP) 8U3-8-ball, Di Ball Grid Array Packag (dbga2) 8Y 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) 8Y5 8-lad, 2.00 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) Options 2.7 Low Voltag (2.7V to 5.5V).8 Low Voltag (.8V to 5.5V) R Rotatd Pinout

12 AT93C56 () Ordring Information Ordring Cod (2) Packag Opration Rang AT93C56-0PI-2.7 AT93C56-0SI-2.7 AT93C56W-0SI-2.7 AT93C56-0TI-2.7 AT93C56Y-0YI-2.7 AT93C56-0PI-.8 AT93C56-0SI-.8 AT93C56W-0SI-.8 AT93C56-0TI-.8 AT93C56Y-0YI-.8 Nots:. This dvic is not rcommndd for nw dsigns. Plas rfr to AT93C56A. 2. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in Tabl 3 on pag 3 and Tabl 4 on pag 4. 8Y 8Y Industrial ( 40 C to 85 C) Industrial ( 40 C to 85 C) Packag Typ 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8-lad, 0.50" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 0.200" Wid, Plastic Gull Wing Small Outlin (EIAJ SOIC) 8-lad, 0.70" Wid, Thin Shrink Small Outlin Packag (TSSOP) 8Y 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) Options 2.7 Low Voltag (2.7V to 5.5V).8 Low Voltag (.8V to 5.5V) 2 AT93C46/56/66

13 AT93C46/56/66 AT93C66 () Ordring Information Ordring Cod (2) Packag Opration Rang AT93C66-0PI-2.7 AT93C66-0SI-2.7 AT93C66W-0SI-2.7 AT93C66-0TI-2.7 AT93C66Y-0YI-2.7 AT93C66-0PI-.8 AT93C66-0SI-.8 AT93C66W-0SI-.8 AT93C66-0TI-.8 AT93C66Y-0YI-.8 Nots:. This dvic is not rcommndd for nw dsigns. Plas rfr to AT93C66A. 2. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in Tabl 3 on pag 3 and Tabl 4 on pag 4. 8Y 8Y Industrial ( 40 C to 85 C) Industrial ( 40 C to 85 C) Packag Typ 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8-lad, 0.50" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 0.200" Wid, Plastic Gull Wing Small Outlin (EIAJ SOIC) 8-lad, 0.70" Wid, Thin Shrink Small Outlin Packag (TSSOP) 8Y 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) Options 2.7 Low Voltag (2.7V to 5.5V).8 Low Voltag (.8V to 5.5V) 3

14 Packaging Information PDIP E E N Top Viw c A End Viw D D A2 A COMMON DIMENSIONS (Unit of Masur = inchs) SYMBOL MIN NOM MAX NOTE A A b b b c b3 4 PL b2 b L D D E E Sid Viw 0.00 BSC A BSC 4 L Nots: R. This drawing is for gnral information only; rfr to JEDEC Drawing MS-00, Variation BA for additional information. 2. Dimnsions A and L ar masurd with th packag satd in JEDEC sating plan Gaug GS D, D and E dimnsions do not includ mold Flash or protrusions. Mold Flash or protrusions shall not xcd 0.00 inch. 4. E and A masurd with th lads constraind to b prpndicular to datum. 5. Pointd or roundd lad tips ar prfrrd to as insrtion. 6. b2 and b3 maximum dimnsions do not includ Dambar protrusions. Dambar protrusions shall not xcd 0.00 (0.25 mm) Orchard Parkway San Jos, CA 953 TITLE, 8-lad, 0.300" Wid Body, Plastic Dual In-lin Packag (PDIP) DRAWING NO. 0/09/02 REV. B 4 AT93C46/56/66

15 AT93C46/56/66 JEDEC SOIC C E E N L Top Viw End Viw B A COMMON DIMENSIONS (Unit of Masur = mm) D Sid Viw A SYMBOL MIN NOM MAX NOTE A A b C D E E BSC L Not: Ths drawings ar for gnral information only. Rfr to JEDEC Drawing MS-02, Variation AA for propr dimnsions, tolrancs, datums, tc. 0/7/03 R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE, 8-lad (0.50" Wid Body), Plastic Gull Wing Small Outlin (JEDEC SOIC) DRAWING NO. REV. B 5

16 EIAJ SOIC C E E N L Top Viw D Sid Viw b A A End Viw COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A A b C D E , 3 E L BSC 4 Nots:. This drawing is for gnral information only; rfr to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of th uppr and lowr dis and rsin burrs ar not includd. 3. It is rcommndd that uppr and lowr cavitis b qual. If thy ar diffrnt, th largr dimnsion shall b rgardd. 4. Dtrmins th tru gomtric position. 5. Valus b and C apply to pb/sn soldr platd trminal. Th standard thicknss of th soldr layr shall b / mm. R 2325 Orchard Parkway San Jos, CA 953 TITLE, 8-lad, 0.209" Body, Plastic Small Outlin Packag (EIAJ) DRAWING NO. 0/7/03 REV. C 6 AT93C46/56/66

17 AT93C46/56/66 TSSOP 3 2 Pin indicator this cornr E E L N Top Viw L End Viw b D Sid Viw A2 A COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE D , 5 E 6.40 BSC E , 5 A.20 A b BSC L L.00 REF Nots:. This drawing is for gnral information only. Rfr to JEDEC Drawing MO-53, Variation AA, for propr dimnsions, tolrancs, datums, tc. 2. Dimnsion D dos not includ mold Flash, protrusions or gat burrs. Mold Flash, protrusions and gat burrs shall not xcd 0.5 mm (0.006 in) pr sid. 3. Dimnsion E dos not includ intr-lad Flash or protrusions. Intr-lad Flash and protrusions shall not xcd 0.25 mm (0.00 in) pr sid. 4. Dimnsion b dos not includ Dambar protrusion. Allowabl Dambar protrusion shall b 0.08 mm total in xcss of th b dimnsion at maximum matrial condition. Dambar cannot b locatd on th lowr radius of th foot. Minimum spac btwn protrusion and adjacnt lad is 0.07 mm. 5. Dimnsion D and E to b dtrmind at Datum Plan H. 5/30/02 R 2325 Orchard Parkway San Jos, CA 953 TITLE, 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) DRAWING NO. REV. B 7

18 8U3- dbga2 E D. b PIN BALL PAD CORNER Top Viw A 2 A A (d) PIN BALL PAD CORNER Sid Viw d () 8 Bottom Viw 8 SOLDER BALLS. Dimnsion b is masurd at th maximum soldr ball diamtr. This drawing is for gnral information only COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A A A b D.50 BSC E 2.00 BSC 0.50 BSC 0.25 REF d.00 BSC d 0.25 REF R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE 8U3-, 8-ball,.50 x 2.00 mm Body, 0.50 mm pitch, Small Di Ball Grid Array Packag (dbga2) 6/24/03 DRAWING NO. REV. PO8U3- A 8 AT93C46/56/66

19 AT93C46/56/66 8Y MAP PIN INDEX AREA A PIN INDEX AREA E D D L E A b Top Viw End Viw Bottom Viw Sid Viw A COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A 0.90 A D E D E b TYP L /28/03 R 2325 Orchard Parkway San Jos, CA 953 TITLE 8Y, 8-lad (4.90 x 3.00 mm Body) MSOP Array Packag (MAP) Y DRAWING NO. 8Y REV. C 9

20 8Y5 MAP D2 b (8x) E Pin Indx Ara E2 Pin ID L (8x) D A3 (6x).50 REF. Top Viw A Bottom Viw COMMON DIMENSIONS (Unit of Masur = mm) A2 Sid Viw A SYMBOL MIN NOM MAX NOTE D 2.00 BSC E 3.00 BSC D E A 0.90 A A A REF L BSC b Nots: R. This drawing is for gnral information only. Rfr to JEDEC Drawing MO-229, for propr dimnsions, tolrancs, datums, tc. 2. Dimnsion b applis to mtallizd trminal and is masurd btwn 0.5 mm and 0.30 mm from th trminal tip. If th trminal has th optional radius on th othr nd of th trminal, th dimnsion should not b masurd in that radius ara Orchard Parkway San Jos, CA 953 TITLE 8Y5, 8-lad 2.0 x 3.0 mm Body, 0.50 mm Pitch, Mini-Map, Dual No Lad Packag (DFN) /2/03 DRAWING NO. REV. 8Y5 A 20 AT93C46/56/66

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