32-Tap Digitally Programmable Potentiometer (DPP )

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1 -Tap Digitally Programmabl Potntiomtr (DPP ) CAT FEATURES -position linar tapr potntiomtr Low powr CMOS tchnology Singl supply opration:.v V Incrmnt up/down srial intrfac Rsistanc valus: 0kΩ, 0kΩ and 00kΩ Availabl in PDIP, SOIC, TSSOP, MSOP and spac saving x.mm TDFN packags APPLICATIONS Automatd product calibration Rmot control adjustmnts Offst, gain and zro control Tampr-proof calibrations Contrast, brightnss and volum controls Motor controls and fdback systms Programmabl analog functions For Ordring Information dtails, s pag. DESCRIPTION Th CAT is a singl digitally programmabl potntiomtr (DPP ) dsignd as a lctronic rplacmnt for mchanical potntiomtrs and trim pots. Idal for automatd adjustmnts on high volum production lins, thy ar also wll suitd for applications whr quipmnt rquiring priodic adjustmnt is ithr difficult to accss or locatd in a hazardous or rmot nvironmnt. Th CAT contains a -tap sris rsistor array connctd btwn two trminals R H and R L. An up/down countr and dcodr that ar controlld by thr input pins, dtrmins which tap is connctd to th wipr, R W. Th wipr is always st to th mid point, tap at powr up. Th tap position is not stord in mmory. Wipr-control of th CAT is accomplishd with thr input control pins, CS, U/D, and INC. Th INC input incrmnts th wipr in th dirction which is dtrmind by th logic stat of th U/D input. Th CS input is usd to slct th dvic. Th digitally programmabl potntiomtr can b usd as a thr-trminal rsistiv dividr or as a two-trminal variabl rsistor. DPPs bring variability and programmability to a wid varity of applications including control, paramtr adjustmnts, and signal procssing. For a pin-compatibl dvic that rcalls a stord tap position on powr-up rfr to th CAT data sht. FUNCTIONAL DIAGRAM V CC R H /V H R H V DD R H GND U/D INC CS Control and Powr-On Rcall R W CS INC U/D UP-DOWN COUNTER -POSITION DECODER R W /V W RW R L GND R L /V L R L Gnral Dtaild Elctronic Potntiomtr Implmntation Catalyst Smiconductor, Inc. Doc. No. MD- Rv. H

2 PIN CONFIGURATION PDIP -Lad (L), SOIC -Lad (V), MSOP -Lad (Z) TSSOP -Lad (Y) CS R L V CC R WB CAT INC GND U/D R H PIN FUNCTION INC V CC U/D CS CAT R H R L GND R WB TDFN -Pad (ZD) Top Viw INC V CC U/D CS R H R L GND R WB INC : Incrmnt Control Input Th INC input movs th wipr in th up or down dirction dtrmind by th condition of th U/D input. U/D : Up/Down Control Input Th U/D input controls th dirction of th wipr movmnt. Whn in a high stat and CS is low, any high-to-low transition on INC will caus th wipr to mov on incrmnt toward th R H trminal. Whn in a low stat and CS is low, any high-to-low transition on INC will caus th wipr to mov on incrmnt towards th R L trminal. R H : High End Potntiomtr Trminal R H is th high nd trminal of th potntiomtr. It is not rquird that this trminal b connctd to a potntial gratr than th R L trminal. Voltag applid to th R H trminal cannot xcd th supply voltag, V CC or go blow ground, GND. R W : Wipr Potntiomtr Trminal R W is th wipr trminal of th potntiomtr. Its position on th rsistor array is controlld by th control inputs, INC, U/D and CS. Voltag applid to th R W trminal cannot xcd th supply voltag, V CC or go blow ground, GND. R L : Low End Potntiomtr Trminal R L is th low nd trminal of th potntiomtr. It is not rquird that this trminal b connctd to a potntial lss than th R H trminal. Voltag applid to th R L trminal cannot xcd th supply voltag, V CC or go blow ground, GND. R L and R H ar lctrically intrchangabl. PIN DESCRIPTIONS Nam Function INC U/D R H GND R W R L CS V CC Incrmnt Control Up/Down Control Potntiomtr High Trminal Ground Buffrd Wipr Trminal Potntiomtr Low Trminal Chip Slct Supply Voltag CS : Chip Slct Th chip slct input is usd to activat th control input of th CAT and is activ low. Whn in a high stat, activity on th INC and U/D inputs will not affct or chang th position of th wipr. DEVICE OPERATION Th CAT oprats lik a digitally controlld potntiomtr with R H and R L quivalnt to th high and low trminals and R W quivalnt to th mchanical potntiomtr's wipr. Thr ar availabl tap positions including th rsistor nd points, R H and R L. Thr ar rsistor lmnts connctd in sris btwn th R H and R L trminals. Th wipr trminal is connctd to on of th taps and controlld by thr inputs, INC, U/D and CS. Ths inputs control a fiv-bit up/down countr whos output is dcodd to slct th wipr position. With CS st LOW th CAT is slctd and will rspond to th U/D and INC inputs. HIGH to LOW transitions on INC will incrmnt or dcrmnt th wipr (dpnding on th stat of th U/D input and fiv-bit countr). Th wipr, whn at ithr fixd trminal, acts lik its mchanical quivalnt and dos not mov byond th last position. Whn th CAT is powrd-down, th wipr position is rst. Whn powr is rstord, th countr is st to th mid point, tap. Doc. No. MD- Rv. H Catalyst Smiconductor, Inc.

3 OPERATION MODES R H INC CS U/D Opration High to Low Low High Wipr toward H High to Low Low Low Wipr toward L High Low to High X Stor Wipr Position Low Low to High X No Stor, Rturn to Standby X High X Standby C H C L R L R WI C W R W Potntiomtr Equivalnt Circuit ABSOLUTE MAXIMUM RATINGS () Paramtrs Ratings Units Paramtrs Ratings Units Supply Voltag Oprating Ambint Tmpratur V CC to GND -0. to V V Industrial ( I suffix) -0 to ºC Inputs Junction Tmpratur 0 ºC CS to GND -0. to V CC 0. V Storag Tmpratur - to 0 ºC INC to GND -0. to V CC 0. V Lad Soldring (0s max) 00 ºC U/D to GND -0. to V CC 0. V H to GND -0. to V CC 0. V L to GND -0. to V CC 0. V W to GND -0. to V CC 0. V RELIABILITY CHARACTERISTICS Symbol Paramtr Tst Mthod Min Typ Max Units () V ZAP ESD Suscptibility MIL-STD-, Tst Mthod V () () I LTH Latch-Up JEDEC Standard 00 ma T DR Data Rtntion MIL-STD-, Tst Mthod Yars N END Enduranc MIL-STD-, Tst Mthod 00,000,000 Stors DC ELECTRICAL CHARACTERISTICS VCC =.V to V unlss othrwis spcifid Powr Supply Symbol Paramtr Conditions Min Typ Max Units V CC Oprating Voltag Rang. V I CC Supply Currnt (Incrmnt) V CC = V, f = MHz, I W = 0 00 µa V CC = V, f = 0kHz, I W = 0 0 µa () CS = V I SB Supply Currnt (Standby) CC - 0.V U/D, INC = V CC - 0.V or GND 0.0 µa Nots: () Strsss abov thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. Ths ar strss ratings only, and functional opration of th dvic at ths or any othr conditions outsid of thos listd in th oprational sctions of this spcification is not implid. Exposur to any absolut maximum rating for xtndd priods may affct dvic prformanc and rliability. () This paramtr is tstd initially and aftr a dsign or procss chang that affcts th paramtr. () Latch-up protction is providd for strsss up to 00mA on addrss and data pins from -V to V CC V. () I W = sourc or sink. () Ths paramtrs ar priodically sampld and ar not 00% tstd. Catalyst Smiconductor, Inc. Doc. No. MD- Rv. H

4 Logic Inputs Symbol Paramtr Conditions Min Typ Max Units I IH Input Lakag Currnt V IN = V CC 0 µa I IL Input Lakag Currnt V IN = 0V -0 µa V IH TTL High Lvl Input Voltag V CC V.V V CC.V TTL Low Lvl Input Voltag 0 0. V V IL V IH CMOS High Lvl Input Voltag V CC x 0. V CC 0. V.V V CC V CMOS Low Lvl Input Voltag -0. V CC x 0. V V IL Potntiomtr Charactristics Symbol Paramtr Conditions Min Typ Max Units -0 Dvic 0 R POT Potntiomtr Rsistanc -0 Dvic 0 kω -00 Dvic 00 Pot. Rsistanc Tolranc ±0 % V RH Voltag on R H pin 0 V CC V V RL Voltag on R L pin 0 V CC V Rsolution. % INL Intgral Linarity Error I W µa 0. LSB DNL Diffrntial Linarity Error I W µa LSB R WI V CC = V, I W = ma 0 00 Ω Wipr Rsistanc V CC =.V, I W = ma 0 00 Ω I W Wipr Currnt () ma TC RPOT TC of Pot Rsistanc ±0 ±00 ppm/ºc TC RATIO Ratiomtric TC 0 ppm/ºc V N Nois 00kHz / khz / nv/ Hz C H /C L /C W Potntiomtr Capacitancs // pf fc Frquncy Rspons Passiv Attnuator, 0kΩ. MHz Doc. No. MD- Rv. H Catalyst Smiconductor, Inc.

5 AC CONDITIONS OF TEST V CC Rang.V V CC.0V Input Puls Lvls Input Ris and Fall Tims Input Rfrnc Lvls 0.V CC to 0.V CC 0ns 0.V CC AC OPERATING CHARACTERISTICS V CC =.V to.0v, V H = V CC, V L = 0V, unlss othrwis spcifid Symbol Paramtr Min Typ () Max Units t CI t DI t ID t IL t IH t IC t CPH t IW t CYC t R, t F () t PU () CS to INC Stup 00 ns U/D to INC Stup 0 ns U/D to INC Hold 00 ns INC LOW Priod 0 ns INC HIGH Priod 0 ns INC Inactiv to CS Inactiv µs CS Dslct Tim 00 ns INC to V OUT Chang µs INC Cycl Tim µs INC Input Ris and Fall Tim 00 µs Powr-up to Wipr Stabl ms A.C. TIMING CS t (stor) CYC t IH t IC t CPH INC t CI til 90% 90% 0% U/D t DI t ID t F t R t IW MI () R W Nots: () Typical valus ar for T A = ºC and nominal supply voltag. () This paramtr is priodically sampld and not 00% tstd. () MI in th A.C. Timing diagram rfrs to th minimum incrmntal chang in th W output du to a chang in th wipr position. Catalyst Smiconductor, Inc. Doc. No. MD- Rv. H

6 APPLICATIONS INFORMATION POTENTIOMETER CONFIGURATION (a) rsistiv dividr (b) variabl rsistanc (c) two-port APPLICATIONS V (-) DPP CAT// V () R R R R 9 R R R A 0 A = A = A = ¼ LM0 R = R = R = kω R POT = 0kΩ V O.V DPP R A R B C R R pr POT 0.0µF 0.00µF (-p)r POT 0.0µF Programmabl Instrumntation Amplifir Programmabl Sq. Wav Oscillator () ICA ¼ HC V REF = V OSC 00mV 0kΩ ICIB CS 0kΩ 0.0µF DPP CAT/ IC V CORR 99kΩ 99kΩ ICIA V OUT = V ± mv -V Snsor 99kΩ 99kΩ V SHIFT = 00mV V SENSOR = V ± 0mV Snsor Auto Rfrncing Circuit Doc. No. MD- Rv. H Catalyst Smiconductor, Inc.

7 CAT/ DPP I S 0Ω pr (-p)r 0Ω MΩ 0k A A LT09 V O.V Programmabl Voltag Rgulator Programmabl I to V Convrtr 00kΩ V OUT V O (REG) V IN (UNREG) SHUTDOWN µf Control and Mmory POR 9 SD GND CAT//.V FB R kω R 0Ω R 0kΩ 0.µF.µF IC HC IC 9 V LL R OSC CLO R 0kΩ 0.µF IC CAT/ U/D 0kΩ INC CS V S CHI.V AI IC V UL R V O. V O V V S µf DPP C 0.00µF R 0kΩ CAT/ C 0.00µF R 0kΩ R 00kΩ A V O.V 0 V S.V Automatic Gain Control Programmabl Bandpass Filtr CAT/ R 00kΩ Srial Bus.V V S R 00kΩ R 00kΩ R.kΩ I S R 00kΩ.V A A =A = LMC0A Programmabl Currnt Sourc/Sink Catalyst Smiconductor, Inc. Doc. No. MD- Rv. H

8 PACKAGE OUTLINE DRAWINGS PDIP -Lad 00mils (L) ()() PIN # IDENTIFICATION D E SYMBOL MIN NOM MAX A. A 0. A b b... c D E.... BSC E.0.. B. 0.9 L TOP VIEW E A A A L b c b B SIDE VIEW END VIEW For currnt Tap and Rl information, download th PDF fil from: Nots: () All dimnsions ar in millimtrs. () Complis with JEDEC standard MS-00. Doc. No. MD- Rv. H Catalyst Smiconductor, Inc.

9 SOIC -Lad 0mils (V) ()() SYMBOL MIN NOM MAX A.. A b PIN # IDENTIFICATION E E c D.0.00 E.0.0 E BSC h L 0.0. θ 0º º TOP VIEW D h A A θ c b L SIDE VIEW END VIEW For currnt Tap and Rl information, download th PDF fil from: Nots: () All dimnsions ar in millimtrs. Angls in dgrs. () Complis with JEDEC standard MS-0. Catalyst Smiconductor, Inc. 9 Doc. No. MD- Rv. H

10 TSSOP -Lad.mm (Y) ()() b E E SYMBOL MIN NOM MAX A.0 A A b c D E E BSC L.00 REF L θ 0 TOP VIEW D A A θ c A L L SIDE VIEW END VIEW For currnt Tap and Rl information, download th PDF fil from: Nots: () All dimnsions ar in millimtrs. Angls in dgrs. () Complis with JEDEC standard MO-. Doc. No. MD- Rv. H 0 Catalyst Smiconductor, Inc.

11 MSOP -Lad.0 x.0mm (Z) ()() E E SYMBOL MIN NOM MAX A.0 A A b c D E E BSC L L 0.9 REF L 0. BSC θ 0º º TOP VIEW D A A DETAIL A A b c SIDE VIEW END VIEW θ L L L DETAIL A For currnt Tap and Rl information, download th PDF fil from: Nots: () All dimnsions ar in millimtrs. Angls in dgrs. () Complis with JEDEC standard MO-. Catalyst Smiconductor, Inc. Doc. No. MD- Rv. H

12 TDFN -Pad x.mm (ZD) ()() PIN# IDENTIFICATION SYMBOL MIN NOM MAX A A A 0.0 REF b D D E E TYP L A A For currnt Tap and Rl information, download th PDF fil from: Nots: () All dimnsions ar in millimtrs. () Complis with JEDEC standard MO-9. Catalyst Smiconductor, Inc. Doc. No. MD- Rv. H

13 EXAMPLE OF ORDERING INFORMATION () Prfix Dvic # Suffix CAT V I -0 G T Optional Company ID Product Numbr Packag L: PDIP V: SOIC Y: TSSOP Z: MSOP ZD: TDFN () Tmpratur Rang I = Industrial (-0ºC to ºC) Rsistanc -0: 0 kω -0: 0 kω -00: 00 kω Tap & Rl T: Tap & Rl : 000/Rl Lad Finish Blank: Matt-Tin G: NiPdAu ORDERING PART NUMBER CATLI-0-G CATLI-0-G CATLI-00-G CATVI-0-G CATVI-0-G CATVI-00-G CATYI-0-G CATYI-0-G CATYI-00-G CATZI-0-G CATZI-0-G CATZI-00-G CATZDI-0 () CATZDI-0 () CATZDI-00 () Nots: () All packags ar RoHS-compliant (Lad-fr, Halogn-fr). () Th standard lad finish is NiPdAu. () This dvic usd in th abov xampl is a CATVI-0-GT (SOIC, Industrial Tmpratur, 0kΩ, NiPdAu, Tap & Rl). () For additional packag and tmpratur options, plas contact your narst Catalyst Smiconductor Sals offic. () TDFN is not availabl in NiPdAu (-G) vrsion. () Contact factory for packag availability. Catalyst Smiconductor, Inc. Doc. No. MD- Rv. H

14 REVISION HISTORY Dat Rv. Rason 09//00 Changd dsignation to Prliminary. B Updatd Dscription. Updatd Potntiomtr Paramtrs tabl. 0/0/00 C Updatd Potntiomtr Paramtrs tabl. 0/9/00 D Changd Grn Packag marking for SOIC from W to V 0//00 E Updatd Tap and Rl spcs in Ordring Information 0//00 F Dltd ICC from DC Charactristics tabl Updatd AC Oprating Charactristics tabl Updatd A.C. Timing diagram. 0/0/00 G Updat Absolut Maximum Ratings tabl Updat DC Elctrical Charactristics tabls Updat AC Conditions of Tst tabl Updat all Packag Outlin Drawings Updat Exampl of Ordring Information Updat Ordring Part Numbr 0/0/00 H Updat Functional Diagram Updat Packag Outlin Drawings Copyrights, Tradmarks and Patnts Catalyst Smiconductor, Inc. Tradmarks and rgistrd tradmarks of Catalyst Smiconductor includ ach of th following: Adaptiv Analog, Byond Mmory, DPP, EZDim, LDD, MiniPot, Quad-Mod and Quantum Charg Programmabl Catalyst Smiconductor has bn issud U.S. and forign patnts and has patnt applications pnding that protct its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Smiconductor products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th body, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th Catalyst Smiconductor product could crat a situation whr prsonal injury or dath may occur. Catalyst Smiconductor rsrvs th right to mak changs to or discontinu any product or srvic dscribd hrin without notic. Products with data shts labld "Advanc Information" or "Prliminary" and othr products dscribd hrin may not b in production or offrd for sal. Catalyst Smiconductor adviss customrs to obtain th currnt vrsion of th rlvant product information bfor placing ordrs. Circuit diagrams illustrat typical smiconductor applications and may not b complt. Catalyst Smiconductor, Inc. Corporat Hadquartrs 9 Stndr Way Santa Clara, CA 90 Phon: Documnt No: MD- Fax: Rvision: H Issu dat: 0/0/0

100-Tap Digitally Programmable Potentiometer (DPP )

100-Tap Digitally Programmable Potentiometer (DPP ) 00-Tap Digitally Programmabl Potntiomtr ( ) CAT FEATURES 00-position linar tapr potntiomtr Non-volatil EEPROM wipr storag 0nA ultra-low standby currnt Singl supply opration:.v.0v Incrmnt up/down srial