NLU2G16. Dual Non-Inverting Buffer

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NLU2G ual Non-Invrting Buffr Th NLU2G MiniGat is an advancd high spd CMOS dual non invrting buffr in ultra small footprint. Th NLU2G input and output structurs provid protction whn voltags up to 7.

1 NLU2G ual Non-Invrting Buffr Th NLU2G MiniGat is an advancd high spd CMOS dual non invrting buffr in ultra small footprint. Th NLU2G input and output structurs provid protction whn voltags up to 7.0 V ar applid, rgardlss of th supply voltag. Faturs High Spd: t P = 3.5 ns = 5.0 V Low Powr issipation: I CC = (Max) at T = 25 C Powr own Protction Providd on inputs Balancd Propagation lays Ovrvoltag Tolrant (OVT) Input and Output Pins Ultra Small Packags Ths ar Pb Fr vics IN OUT Y UFN.2 x.0 CS 57 ULLG.0 x.0 CS 3 MRKING IGRMS C M CM GN 2 5 ULLG.2 x.0 CS 3 CM IN 2 3 OUT Y2 ULLG.5 x.0 CS 3F M Figur. Pinout (Top Viw) IN OUT Y UFN.0 x.0 CS 57BX X M IN 2 OUT Y2 Figur 2. Logic Symbol UFN.5 x.0 CS 57Q X M PIN SSIGNMNT IN 2 GN 3 IN 2 OUT Y2 5 OUT Y C or M = vic Marking = at Cod ORRING INFORMTION S dtaild ordring and shipping information in th packag dimnsions sction on pag of this data sht. L H FUNCTION TBL Y L H Smiconductor Componnts Industris, LLC, 202 July, 202 Rv. 3 Publication Ordr Numbr: NLU2G/

2 NLU2G MXIMUM RTINGS Symbol Paramtr Valu Unit C Supply Voltag 0.5 to +7.0 V V IN C Input Voltag 0.5 to +7.0 V V OUT C Output Voltag 0.5 to +7.0 V I IK C Input iod Currnt V IN < GN 20 m I OK C Output iod Currnt V OUT < GN ±20 m I O C Output Sourc/Sink Currnt ±2.5 m I CC C Supply Currnt Pr Supply Pin ±25 m I GN C Ground Currnt pr Ground Pin ±25 m T STG Storag Tmpratur Rang 5 to +50 C T L Lad Tmpratur, mm from Cas for 0 Sconds 20 C T J Junction Tmpratur Undr Bias 50 C MSL Moistur Snsitivity Lvl F R Flammability Rating Oxygn Indx: 28 to 3 UL 9 V 0.25 in I LTCHUP Latchup Prformanc bov and Blow GN at 25 C (Not 2) ±500 m Strsss xcding Maximum Ratings may damag th dvic. Maximum Ratings ar strss ratings only. Functional opration abov th Rcommndd Oprating Conditions is not implid. xtndd xposur to strsss abov th Rcommndd Oprating Conditions may affct dvic rliability.. Masurd with minimum pad spacing on an FR board, using 0 mm by inch, 2 ounc coppr trac no air flow. 2. Tstd to I / JS78. RCOMMN OPRTING CONITIONS Symbol Paramtr Min Max Unit Positiv C Supply Voltag V V IN igital Input Voltag V V OUT Output Voltag V T Oprating Fr ir Tmpratur C t/ V Input Transition Ris or Fall Rat = 3.3 V ± 0.3 V = 5.0 V ± 0.5 V ns/v 2

3 NLU2G C LCTRICL CHRCTRISTICS Symbol Paramtr Conditions V IH Low Lvl Input Voltag (V) x T = 25 C T = +85 C T = 55 C to +25 C Min Typ Max Min Max Min Max 0.75 x Unit V 2.3 to x 0.70 x V IL Low Lvl Input Voltag x 0.25 x 0.25 x V 2.3 to x 0.30 x 0.30 x V OH High Lvl Output Voltag V IN = V IH or V IL I OH = V V IN = V IH or V IL I OH = m I OH = 8 m V V OL Low Lvl Output Voltag V IN = V IH or V IL I OL = V V IN = V IH or V IL I OL = m I OL = 8 m I IN Input Lakag Currnt 0 V IN 5.5 V 0 to 5.5 ±0. ±.0 ±.0 I CC Quiscnt Supply Currnt 0 V IN C LCTRICL CHRCTRISTICS (Input t r = t f = 3.0 ns) Symbol t PLH, t PHL Paramtr Propagation lay, Input to Output Y (V) 3.0 to 3..5 to 5.5 Tst Condition T = 25 C T = +85 C T = 55 C to +25 C Min Typ Max Min Max Min Max C L = 5 pf ns C L = 50 pf C L = 5 pf C L = 50 pf C IN Input Capacitanc pf C P Powr issipation Capacitanc (Not 3) pf 3. C P is dfind as th valu of th intrnal quivalnt capacitanc which is calculatd from th dynamic oprating currnt consumption without load. vrag oprating currnt can b obtaind by th quation I CC(OPR) = C P f in + I CC. C P is usd to dtrmin th no load dynamic powr consumption: P = C P 2 f in + I CC. Unit 3

4 NLU2G SWITCHING WVFORMS TST POINT t PLH 50% 50% t PHL GN VIC UNR TST OUTPUT C L * Y Figur 3. Switching Wavforms *Includs all prob and jig capacitanc Figur. Tst Circuit ORRING INFORMTION vic Packag Shipping NLU2GMUTCG UFN,.2 x.0, 0.P (Pb Fr) 3000 / Tap & Rl NLU2GMXTCG ULLG,.5 x.0, 0.5P (Pb Fr) NLU2GBMXTCG ULLG,.2 x.0, 0.P (Pb Fr) NLU2GCMXTCG ULLG,.0 x.0, 0.35P (Pb Fr) NLU2GMUTCG UFN,.5 x.0, 0.5P (Pb Fr) NLU2GCMUTCG UFN,.0 x.0, 0.35P (Pb Fr) 3000 / Tap & Rl 3000 / Tap & Rl 3000 / Tap & Rl 3000 / Tap & Rl 3000 / Tap & Rl For information on tap and rl spcifications, including part orintation and tap sizs, plas rfr to our Tap and Rl Packaging Spcifications Brochur, BR80/.

5 NLU2G PCKG IMNSIONS UFN.5x.0, 0.5P CS 57Q ISSU O PIN ON 0.0 C 0.0 C É TOP VIW TIL B SI VIW B 2 L C STING PLN XPOS Cu L TIL OPTIONL CONSTRUCTIONS MOL CMP TIL B OPTIONL CONSTRUCTIONS L NOTS:. IMNSIONING N TOLRNCING PR SM Y.5M, CONTROLLING IMNSION:. 3. IMNSION b PPLIS TO PLT TRMINL N IS MSUR BTWN 0.5 N 0.30 mm FROM TH TRMINL TIP. IM MIN MX RF b BSC.00 BSC 0.50 BSC L L 0.5 MOUNTING FOOTPRINT PCKG OUTLIN L.2 TIL b 0.0 C B NOT *For additional information on our Pb Fr stratgy and soldring dtails, plas download th ON Smiconductor Soldring and Mounting Tchniqus Rfrnc Manual, SOLRRM/. 5

6 NLU2G PCKG IMNSIONS UFN.0x.0, 0.35P CS 57BX ISSU O PIN ON 2X 2X 0.0 C É É 0.0 C L TOP VIW SI VIW 3 B 3 5X L C STING PLN NOTS:. IMNSIONING N TOLRNCING PR SM Y.5M, CONTROLLING IMNSION:. 3. IMNSION b PPLIS TO PLT TRMINL N IS MSUR BTWN 0.5 N 0.20 MM FROM TRMINL TIP.. PCKG IMNSIONS XCLUSIV OF BURRS N MOL FLSH. IM MIN MX RF b BSC.00 BSC 0.35 BSC L L RCOMMN SOLRING FOOTPRINT* 5X b 0.0 M C B 0.05 M C NOT PKG OUTLIN 0.35 *For additional information on our Pb Fr stratgy and soldring dtails, plas download th ON Smiconductor Soldring and Mounting Tchniqus Rfrnc Manual, SOLRRM/.

7 NLU2G PCKG IMNSIONS UFN,.2x.0, 0.P CS 57 ISSU C 2X 0X PIN ON 0.0 C 2X 0.0 C 0.08 C 0.0 C L2 TOP VIW SI VIW 3 B (3) 5X L C L XPOS Cu STING PLN TIL Bottom Viw (Optional) É TIL B Sid Viw (Optional) G OF PCKG MOL CMP 3 NOTS:. IMNSIONING N TOLRNCING PR SM Y.5M, CONTROLLING IMNSION:. 3. IMNSION b PPLIS TO PLT TRMINL N IS MSUR BTWN 0.25 N 0.30 mm FROM TRMINL.. COPLNRITY PPLIS TO TH XPOS P S WLL S TH TRMINLS. IM MIN MX RF b BSC.00 BSC 0.0 BSC L L L MOUNTING FOOTPRINT* b 0.0 C B NOT *For additional information on our Pb Fr stratgy and soldring dtails, plas download th ON Smiconductor Soldring and Mounting Tchniqus Rfrnc Manual, SOLRRM/. 7

8 NLU2G PCKG IMNSIONS ULLG.0x.0, 0.35P CS 3 ISSU PIN ON 0.0 C 0.0 C TOP VIW SI VIW B C STING PLN NOTS:. IMNSIONING N TOLRNCING PR SM Y.5M, CONTROLLING IMNSION:. 3. IMNSION b PPLIS TO PLT TRMINL N IS MSUR BTWN 0.5 N 0.30 mm FROM TH TRMINL TIP.. MXIMUM OF 0.05 PULL BCK OF TH PLT TRMINL FROM TH G OF TH PCKG IS LLOW. IM MIN MX b BSC.00 BSC 0.35 BSC L L MOUNTING FOOTPRINT SOLRMSK FIN* 5X L 3 5X L NOT.8 b 0.0 C B NOT PKG OUTLIN 0.35 *For additional information on our Pb Fr stratgy and soldring dtails, plas download th ON Smiconductor Soldring and Mounting Tchniqus Rfrnc Manual, SOLRRM/. 8

9 NLU2G PCKG IMNSIONS ULLG.2x.0, 0.P CS 3 ISSU PIN ON 0.0 C 0.0 C TOP VIW B NOTS:. IMNSIONING N TOLRNCING PR SM Y.5M, CONTROLLING IMNSION:. 3. IMNSION b PPLIS TO PLT TRMINL N IS MSUR BTWN 0.5 N 0.30 mm FROM TH TRMINL TIP.. MXIMUM OF 0.05 PULL BCK OF TH PLT TRMINL FROM TH G OF TH PCKG IS LLOW. IM MIN MX b BSC.00 BSC 0.0 BSC L L SI VIW C STING PLN MOUNTING FOOTPRINT SOLRMSK FIN* 5X L 3 5X L NOT.2 b 0.0 C B NOT PKG OUTLIN 0.0 *For additional information on our Pb Fr stratgy and soldring dtails, plas download th ON Smiconductor Soldring and Mounting Tchniqus Rfrnc Manual, SOLRRM/. 9

10 NLU2G PCKG IMNSIONS ULLG.5x.0, 0.5P CS 3F ISSU PIN ON 0.0 C 0.0 C É É TOP VIW SI VIW B C STING PLN NOTS:. IMNSIONING N TOLRNCING PR SM Y.5M, CONTROLLING IMNSION:. 3. IMNSION b PPLIS TO PLT TRMINL N IS MSUR BTWN 0.5 N 0.30 mm FROM TH TRMINL TIP.. MXIMUM OF 0.05 PULL BCK OF TH PLT TRMINL FROM TH G OF TH PCKG IS LLOW. IM MIN MX b BSC.00 BSC 0.50 BSC L L MOUNTING FOOTPRINT SOLRMSK FIN* 5X L 3 5X L NOT.2 b 0.0 C B NOT PKG OUTLIN 0.50 *For additional information on our Pb Fr stratgy and soldring dtails, plas download th ON Smiconductor Soldring and Mounting Tchniqus Rfrnc Manual, SOLRRM/. MiniGat is a tradmark of Smiconductor Componnts Industris, LLC (SCILLC). ON Smiconductor and ar rgistrd tradmarks of Smiconductor Componnts Industris, LLC (SCILLC). SCILLC owns th rights to a numbr of patnts, tradmarks, copyrights, trad scrts, and othr intllctual proprty. listing of SCILLC s product/patnt covrag may b accssd at Marking.pdf. SCILLC rsrvs th right to mak changs without furthr notic to any products hrin. SCILLC maks no warranty, rprsntation or guarant rgarding th suitability of its products for any particular purpos, nor dos SCILLC assum any liability arising out of th application or us of any product or circuit, and spcifically disclaims any and all liability, including without limitation spcial, consquntial or incidntal damags. Typical paramtrs which may b providd in SCILLC data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including Typicals must b validatd for ach customr application by customr s tchnical xprts. SCILLC dos not convy any licns undr its patnt rights nor th rights of othrs. SCILLC products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th body, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th SCILLC product could crat a situation whr prsonal injury or dath may occur. Should Buyr purchas or us SCILLC products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold SCILLC and its officrs, mploys, subsidiaris, affiliats, and distributors harmlss against all claims, costs, damags, and xpnss, and rasonabl attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that SCILLC was nglignt rgarding th dsign or manufactur of th part. SCILLC is an qual Opportunity/ffirmativ ction mployr. This litratur is subjct to all applicabl copyright laws and is not for rsal in any mannr. PUBLICTION ORRING INFORMTION LITRTUR FULFILLMNT: Litratur istribution Cntr for ON Smiconductor P.O. Box 53, nvr, Colorado 8027 US Phon: or Toll Fr US/Canada Fax: or Toll Fr US/Canada mail: ordrlit@onsmi.com N. mrican Tchnical Support: Toll Fr US/Canada urop, Middl ast and frica Tchnical Support: Phon: Japan Customr Focus Cntr Phon: ON Smiconductor Wbsit: Ordr Litratur: For additional information, plas contact your local Sals Rprsntativ NLU2G/

NLU2G17. Dual Non-Inverting Schmitt-Trigger Buffer

NLU2G17. Dual Non-Inverting Schmitt-Trigger Buffer NLU2G7 ual Non-Invrting Schmitt-Triggr Buffr Th NLU2G7 MiniGat is an advancd high spd CMOS dual non invrting Schmitt triggr buffr in ultra small footprint. Th NLU2G7 input and output structurs provid protction