CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER
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- Phebe Carr
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1 4.-V to.-v V CC Opration s for BCD Cod Storag Blanking Capability Phas for Complmnting s Fanout (Ovr Tmpratur Rang) Standard s 0 LSTTL Loads Baland Propagation Dlay and Transition Tims Signifiant Powr Rdution, Compard to LSTTL Logi ICs Dirt LSTTL Logi Compatibility, V IL = 0.8 V Maximum, V IH = 2 V Minimum CMOS Compatibility, I I µa at V OL, V OH BCD s D2 D D D0 E PACKAGE (TOP VIEW) DISPLAY V CC f g d b a -Sgmnt s a f g b d dsription/ordring information Th CD4HCT44 high-spd silion-gat is a BCD-to- sgmnt lath/dodr/drivr dsignd primarily for dirtly driving liquid-rystal displays. Whil th lath nabl () is low, th laths ar nabld to stor th BCD inputs. Whn th lath nabl is high, th laths ar disabld, making th outputs transparnt to th BCD inputs. Th dvi has an ativ-high blanking input () and a phas input () to whih a squar wav is applid for liquid-rystal appliations. This squar wav also is applid to th bakplan of th liquid-rystal display. TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING C to 2 C PDIP E Tub CD4HCT44E CD4HCT44E Pakag drawings, standard paking quantitis, thrmal data, symbolization, and PCB dsign guidlins ar availabl at Plas b awar that an important noti onrning availability, standard warranty, and us in ritial appliations of Txas Instrumnts smiondutor produts and dislaimrs thrto appars at th nd of this data sht. PRODUCTION DATA information is urrnt as of publiation dat. Produts onform to spifiations pr th trms of Txas Instrumnts standard warranty. Prodution prossing dos not nssarily inlud tsting of all paramtrs. Copyright 200, Txas Instrumnts Inorporatd POST OFFICE BOX 60 DALLAS, TEXAS 26
2 funtional diagram FUNCTION TABLE D D2 D D0 a b d f g Display X H L X X X X L L L L L L L Blank H L L L L L L H H H H H H L 0 H L L L L L H L H H L L L L H L L L L H L H H L H H L H 2 H L L L L H H H H H H L L H H L L L H L L L H H L L H H 4 H L L L H L H H L H H L H H H L L L H H L H L H H H H H 6 H L L L H H H H H H L L L L H L L H L L L H H H H H H H 8 H L L H L L H H H L H L H H 9 H L L H L H L L L L L L L L Blank H L L H L H H L L L L L L L Blank H L L H H L L L L L L L L L Blank H L L H H L H L L L L L L L Blank H L L H H H L L L L L L L L Blank H L L H H H H L L L L L L L Blank L L L X X X X As abov H As abov Invrs of abov As abov Dpnds on BCD od prviously applid whn = high. BCD s D0 D D2 D 2 4 = 8 = 6 Dodr 6 Drivr a b d f g -Sgmnt s 2 POST OFFICE BOX 60 DALLAS, TEXAS 26
3 logi diagram 9 a D0 D0 Q0 0 b Q0 D D Q 2 D2 Q D2 Q2 Q2 Dn Dn 2 d P n P n 4 D D Q Q f 6 4 g POST OFFICE BOX 60 DALLAS, TEXAS 26
4 absolut maximum ratings ovr oprating fr-air tmpratur (unlss othrwis notd) Supply voltag rang, V CC V to V diod urrnt, I IK (V I < 0. V or V I > V CC + 0. V) ) (s Not ) ±20 ma diod urrnt, I OK (V O < 0. V or V O > V CC + 0.V) (s Not ) ±20 ma Continuous output sour or sink urrnt pr output, I O (V O = 0 to V CC ) ±2 ma Continuous urrnt through V CC or ±0 ma Pakag thrmal impdan, θ JA (s Not 2) C/W At distan /6 ± /2 in. (.9 ± 0.9 mm) from as for 0 s maximum C Unit insrtd into a PC board (min. thiknss /6 in.,.9 mm) with soldr ontating lad tips only C Storag tmpratur, T stg to 0 C Strsss byond thos listd undr absolut maximum ratings may aus prmannt damag to th dvi. Ths ar strss ratings only, and funtional opration of th dvi at ths or any othr onditions byond thos indiatd undr rommndd oprating onditions is not implid. Exposur to absolut-maximum-ratd onditions for xtndd priods may afft dvi rliability. NOTES:. Th input and output voltag ratings may b xdd if th input and output urrnt ratings ar obsrvd. 2. Th pakag thrmal impdan is alulatd in aordan with JESD -. rommndd oprating onditions (s Not ) TA = 2 C TA = C TO 2 C TO 8 C MIN MAX MIN MAX MIN MAX Supply voltag V VIH High-lvl input voltag V VIL Low-lvl input voltag V VI voltag V VO voltag V tt transition (ris and fall) tim ns NOTE : All unusd inputs of th dvi must b hld at or to nsur propr dvi opration. Rfr to th TI appliation rport, Impliations of Slow or Floating CMOS s, litratur numbr SCBA004. ltrial haratristis ovr rommndd oprating fr-air tmpratur rang (unlss othrwis notd) PARAMETER TEST CONDITIONS VI =VIH or VIL VI =VIH or VIL IOH = 20 µa IOH = 4 ma IOL = 20 µa IOL = 4 ma 4V 4. 4V 4. TA = 2 C TA = C TO 2 C TO 8 C MIN TYP MAX MIN MAX MIN MAX II VI = to. V ±0. ± ± µa ICC VI = or 0, IO = 0. V µa ICC On input at 2. V, Othr inputs at 0 or 4. V to. V µa Ci pf Additional quisnt supply urrnt pr input pin, TTL inputs high, unit load. For dual-supply systms, thortial worst-as (VI = 2.4 V, =. V) spifiation is.8 ma. V V 4 POST OFFICE BOX 60 DALLAS, TEXAS 26
5 HCT INPUT LOADING TABLE INPUT LOADS D0, D, D2 D, Unit Load is ICC limit spifid in ltrial haratristis tabl,.g., 60 µa maximum at 2 C. timing rquirmnts ovr rommndd oprating fr-air tmpratur rang V CC = 4. V (unlss othrwis notd) (s Figur ) TA = 2 C TA = C TO 2 C TO 8 C MIN MAX MIN MAX MIN MAX tw Puls duration, high 0 ns tsu Stup tim, BCD inputs bfor 2 8 ns th Hold tim, BCD inputs bfor ns swithing haratristis ovr rommndd oprating fr-air tmpratur rang (unlss othrwis notd) (s Figur 2) PARAMETER tpd FROM TO LOAD (INPUT) (OUTPUT) CAPACITANCE Dn TA = 2 C TA = C TO 2 C TO 8 C MIN TYP MAX MIN MAX MIN MAX CL = 0 pf 4. V CL = pf V CL = 0 pf 4. V 6 96 CL = pf V 2 CL = 0 pf 4. V CL = pf V 2 CL = 0 pf 4. V CL = pf V 2 tt Any CL = 0 pf 4. V 0 6 ns ns oprating haratristis, V CC = V, T A = 2 C PARAMETER TYP Cpd Powr dissipation apaitan 4 pf Cpd is usd to dtrmin th dynami powr onsumption, pr pakag. PD = Cpd 2 fi + CL 2 fo whr: fi = input frquny fo = output frquny CL = output load apaitan = supply voltag POST OFFICE BOX 60 DALLAS, TEXAS 26
6 PARAMETER MEASUREMENT INFORMATION PARAMETER S S2 From Undr Tst CL (s Not A) Tst Point RL = kω S S2 tpzh tn tpzl tz tdis tplz tpd or tt Closd Closd Closd Closd LOAD CIRCUIT tw PULSE DURATION CLR CLK tr Rfrn Data 0% tsu th 90% 90% tr tf RECOVERY TIME SETUP AND HO AND INPUT RISE AND FALL TIMES In-Phas Out-of-Phas tplh 0% tl 90% 90% 90% tf PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr tl 0% tf tplh 90% tr Control Wavform (s Not B) Wavform 2 (s Not B) NOTES: A. CL inluds prob and tst-fixtur apaitan. B. Wavform is for an output with intrnal onditions suh that th output is low xpt whn disabld by th output ontrol. Wavform 2 is for an output with intrnal onditions suh that th output is high xpt whn disabld by th output ontrol. C. Phas rlationships btwn wavforms wr hosn arbitrarily. All input pulss ar supplid by gnrators having th following haratristis: PRR MHz, ZO = 0 Ω, tr = 6 ns, tf = 6 ns. D. For lok inputs, fmax is masurd with th input duty yl at 0%. E. Th outputs ar masurd on at a tim with on input transition pr masurmnt. F. tplz and tz ar th sam as tdis. G. tpzl and tpzh ar th sam as tn. H. tplh and tl ar th sam as tpd. tpzl tpzh Figur. Load Ciruit and Voltag Wavforms 90% OUTPUT ENABLE AND DISABLE TIMES tplz tz 6 POST OFFICE BOX 60 DALLAS, TEXAS 26
7 APPLICATION CIRCUITS Appropriat Voltag HCT44 ÉÉÉÉÉ On of Svn Sgmnts Common Bakplan Squar Wav: to HCT44 Figur 2. Conntion to Liquid-Crystal Display (LCD) Figur. Conntion to Inandsnt Display Appropriat Voltag HCT44 HCT44 To Filamnt Supply or Appropriat Voltag Blow Figur 4. Conntion to Gas-Disharg Display Figur. Conntion to Fluorsnt Display POST OFFICE BOX 60 DALLAS, TEXAS 26
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5 ow Dropout Fast Rspons Positiv djustabl Rgulator and Fixd 3.3V Faturs Gnral Dsription Fast Transint Rspons Guarantd Dropout Voltag at Multipl Currnts oad Rgulation: 0.05% Typ. in Rgulation: 0.03% Typ.
MM74HC157 Quad 2-Input Multiplexer
Quad 2-Input Multiplexer General Description The MM74HC157 high speed Quad 2-to-1 Line data selector/multiplexers utilizes advanced silicon-gate CMOS technology. It possesses the high noise immunity and
MM74HC151 8-Channel Digital Multiplexer
8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation
HD74HC147FPEL. 10-to-4-line Priority Encoder. Description. Features. Function Table. REJ03D (Previous ADE ) Rev.2.
0-to-4-lin Priority nodr RJ030572-0200 (Prvious -205-446) Rv.2.00 Ot, 2005 sription Th H74HC47 faturs priority noding of th inputs to nsur that only th highst ordr data lin is nodd. Nin input lins ar nodd
MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity
PO54G74A, PO74G74A. Pin Configuration. Logic Block Diagram. Pin Description. 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: 1D 2
DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS FEATURES:. Patented technology. Specified From 0 C to 12 C, C to 12 C. Operating frequency is faster than 600MHz. VCC Operates from 1.6V to 3.6V. Propagation
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC148 M74HC148 8 TO 3 LINE PRIORITY ENCODER. tpd = 15 ns (TYP.
M54HC148 M74HC148 8 TO 3 LINE PRIORITY ENCODER. HIGH SPEED tpd = 15 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 1999 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
UNISONIC TECHNOLOGIES CO., LTD U74HC164
UNISONIC TECHNOLOGIES CO., LTD 8-BIT SERIAL-IN AND PARALLEL-OUT SHIFT REGISTER DIP-14 DESCRIPTION The is an 8-bit edge-triggered shift registers with serial input and parallel output. A LOW-to-HIGH transition
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. September 2001 S7C256 5V/3.3V 32K X 8 CMOS SRM (Common I/O) Features S7C256
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC133 M74HC INPUT NAND GATE. tpd = 13 ns (TYP.) at VCC =5V
M54HC133 M74HC133 13 INPUT NAND GATE. HIGH SPEED tpd = 13 ns (TYP.) at VCC =5V.LOW POWER DISSIPATION I CC =1µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC137 M74HC137 3 TO 8 LINE DECODER/LATCH (INVERTING) tpd = 11 ns (TYP.
M54HC137 M74HC137 3 TO 8 LINE DECODER/LATCH (INVERTING). HIGH SPEED tpd = 11 (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE
Description. For Fairchild s definition of Eco Status, please visit:
FSA2357 Low R ON 3:1 Analog Switch Features 10µA Maximum I CCT Current Over an Expanded Control Voltage Range: V IN=2.6V, V CC=4.5V On Capacitance (C ON): 70pF Typical 0.55Ω Typical On Resistance (R ON)
. HIGH SPEED .LOW POWER DISSIPATION .OUTPUT DRIVE CAPABILITY M54HCT138 M74HCT138 3 TO 8 LINE DECODER (INVERTING) t PD = 16 ns (TYP.
M54HCT138 M74HCT138 3 TO 8 LINE DECODER (INVERTING). HIGH SPEED t PD = 16 ns (TYP.) at V CC =5V.LOW POWER DISSIPATION ICC =4µAATTA =25 C.OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS
TC74LCX08F,TC74LCX08FN,TC74LCX08FT,TC74LCX08FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LCX08F/FN/FT/FK TC74LCX08F,TC74LCX08FN,TC74LCX08FT,TC74LCX08FK Low-Voltage Quad 2-Input AND Gate with 5-V Tolerant Inputs and Outputs The
74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting. Product data sheet
3-to-8 line decoder, demultiplexer with address latches; inverting Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky
74ACT825 8-Bit D-Type Flip-Flop
8-Bit D-Type Flip-Flop General Description The ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
Features. Description. Pin Description. Pin Configuration PI4GTL2107
Features Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver Operates at GTL, GTL+ or GTL levels 2.3 V to 3.6 V operation EN1 and EN2 enable control LVTTL I/O not 5 V tolerant ESD protection
74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:
Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
SRM2264L10/12 CMOS 64K-BIT STATIC RAM. Low Supply Current Access Time 100ns/120ns 8,192 Words 8 Bits, Asynchronous DESCRIPTION
DESCRIPTION SRM2264L10/12 CMOS 64K-BIT STATIC RAM Low Supply Current Access Time 100ns/120ns 8,192 Words 8 Bits, Asynchronous The SRM2264L10/12 is an 8,192-word 8-bit asynchronous, static, random access
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and
MM74HC374 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28
INTEGRATED CIRCUITS -to-8 line decoder/demultiplexer; inverting 998 Apr 8 FEATURES Wide supply voltage range of. to. V In accordance with JEDEC standard no. 8-A Inputs accept voltages up to. V CMOS lower
Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
TECHNICAL DATA IN74ACT74 Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT74 is identical in pinout to the LS/ALS74, HC/HCT74. The IN74ACT74 may be used as a level converter
INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1998 Apr 13 IC24 Data Handbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC06 74HC/HCT/HCU/HCMOS ogic Package Information The IC06 74HC/HCT/HCU/HCMOS
M74HC4543TTR BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER
BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER HIGH SPEED: t PD = 14 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
CM600HX-12A. APPLICATION General purpose Inverters, Servo Amplifiers, Power supply, etc. CM600HX-12A. IC...600A VCES...600V Single
MHX-1A MHX-1A I...A S... Single Flatbase Type / Insulated Package / opper (non-plating) base plate RoHS Directive compliant APPLIATION General purpose Inverters, Servo Amplifiers, Power supply, etc. OUTLIN
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate Description: The NTE4501 is a triple gate device in a 16 Lead DIP type package constructed with MOS P
SP490/SP491. Full Duplex RS-485 Transceivers. Now Available in Lead Free Packaging
SP490/SP491 Full uplx RS-485 Transcivrs FTURS +5V Only Low Powr icmos rivr/rcivr nal (SP491) RS-485 and RS-422 rivrs/rcivrs Pin Compatil with LTC490 and SN75179 (SP490) Pin Compatil with LTC491 and SN75180
74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset
Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard
HCC4543B HCF4543B BCD-TO-7 SEGMENT LATCH/DECODER/LCD DRIVER HCC/HCF4543B
HCC4543B HCF4543B BCD-TO-7 SEGMENT LATCH/DECODER/LCD DRIER DISPLAY BLANKING OF ALL ILLEGAL INPUT COMBINATIONS LATCH STORAGE OF CODE CAPABILITY OF DRIING TWO LOW POWER TTL LOADS, TWO HTL LOADS, OR ONE LOW
MM74HC00 Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption
54AC174/54ACT174 Hex D Flip-Flop with Master Reset
54AC174/54ACT174 Hex D Flip-Flop with Master Reset General Description The AC/ ACT174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information
TC74VHCT573AF,TC74VHCT573AFW,TC74VHCT573AFT
TOSHIBA CMOS igital Integrated Circuit Silicon Monolithic TC74HCT573AF/AFW/AFT TC74HCT573AF,TC74HCT573AFW,TC74HCT573AFT Octal -Type Latch with 3-State Output The TC74HCT573A is an advanced high speed CMOS
TC74HC148AP,TC74HC148AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC148AP,TC74HC148AF 8-to-3 Line Priority Encoder The TC74HC148A is a high speed CMOS 8-to-3 LINE ENCODER fabricated with silicon gate C2MOS
MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear
MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear General Description These J-K Flip-Flops utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power dissipation of
74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance