64-Kb I 2 C CMOS Serial EEPROM

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1 b I 2 MO rial EEPROM FEURE upports tandard and Fast I 2 Protocol 1.8 V to 5.5 V upply Voltag Rang 32-Byt Pag Writ Buffr (1) Hardwar Writ Protction for ntir mmory chmitt riggrs and Nois upprssion Filtrs on I 2 Bus Inputs (L and D). Low powr MO tchnology 1,000,000 program/ras cycls DEVIE DERIPION h 2464 is a 64-b MO rial EEPROM dvics, intrnally organizd as 8192 words of 8 bits ach. It faturs a 32-byt pag writ buffr and supports both th tandard (100 khz) as wll as Fast (400 khz) I 2 protocol. Extrnal addrss pins mak it possibl to addrss up to ight 2464 dvics on th sam bus. 100 yar data rtntion Industrial and Extndd tmpratur rang RoH-compliant 8-pin PDIP, OI, OP, MOP and DFN packags Not: (1) 2464 Rv. D (Not Rcommndd for Nw Dsigns) has 64-Byt Pag Writ Buffr. For Ordring Information dtails, s pag 16. PIN ONFIGURION FUNIONL YMBOL PDIP (L) OI (W, X) OP (Y), MOP (Z) DFN (ZD2*, VP2) V V L WP 2 V L D 2, 1, D For th location of Pin 1, plas consult th corrsponding packag drawing. * Not rcommndd for nw dsigns WP PIN FUNION V 0, 1, 2 D L WP V Dvic ddrss rial Data rial lock Writ Protct Powr upply V Ground * h Grn & Gold sal idntifis RoH-compliant packaging, using NiPdu pr-platd lad frams ILL. ll rights rsrvd. haractristics subjct to chang without notic 1 Doc. No. MD-1102, Rv. L

2 2464 BOLUE MXIMUM RING (1) torag mpratur Voltag on ny Pin with Rspct to Ground (2) -65 to V to +6.5 V RELIBILIY HRERII (3) ymbol Paramtr Min Units N (4) END Enduranc 1,000,000 Program/ Eras ycls DR Data Rtntion 100 Yars D.. OPERING HRERII V = 1.8 V to 5.5 V, = -40 to 125, unlss othrwis spcifid. ymbol Paramtr st onditions Min Max Units I R Rad urrnt Rad, f L = 400kHz 1 m I W Writ urrnt Writ, f L = 400kHz 2 m = -40 to I B tandby urrnt ll I/O Pins at GND or V = -40 to μ = -40 to I L I/O Pin Lakag Pin at GND or V = -40 to μ V IL Input Low Voltag -0.5 V x 0.3 V V IH Input High Voltag V x 0.7 V V V OL1 Output Low Voltag V < 2.5 V, I OL = 3.0m 0.4 V V OL2 Output Low Voltag V < 2.5 V, I OL = 1.0m 0.2 V PIN IMPEDNE HRERII V = 1.8 V to 5.5 V, = -40 to 125, unlss othrwis spcifid. ymbol Paramtr onditions Max Units (3) IN D I/O Pin apacitanc V IN = 0 V 8 pf (3) IN Input apacitanc (othr pins) V IN = 0 V 6 pf I (5) WP WP Input urrnt V IN < 0.5xV, V = 5.5 V 200 V IN < 0.5xV, V = 3.3 V 150 V IN < 0.5xV, V = 1.8 V 100 V IN > 0.5xV 1 μ Not: (1) trsss abov thos listd undr bsolut Maximum Ratings may caus prmannt damag to th dvic. hs ar strss ratings only, and functional opration of th dvic at ths or any othr conditions outsid of thos listd in th oprational sctions of this spcification is not implid. Exposur to any absolut maximum rating for xtndd priods may affct dvic prformanc and rliability. (2) h D input voltag on any pin should not b lowr than -0.5 V or highr than V V. During transitions, th voltag on any pin may undrshoot to no lss than -1.5 V or ovrshoot to no mor than V V, for priods of lss than 20 ns. (3) hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat E-Q100 and JEDE tst mthods. (4) Pag Mod, V = 5 V, 25 (5) Whn not drivn, th WP pin is pulld down to GND intrnally. For improvd nois immunity, th intrnal pull-down is rlativly strong; thrfor th xtrnal drivr must b abl to supply th pull-down currnt whn attmpting to driv th input HIGH. o consrv powr, as th input lvl xcds th trip point of th MO input buffr (~ 0.5 x V ), th strong pull-down rvrts to a wak currnt sourc. Doc. No. MD-1102, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic

3 HRERII (1) V = 1.8 V to 5.5 V, = -40 to 125. tandard Fast ymbol Paramtr Min Max Min Max Units F L lock Frquncy khz t HD: R ondition Hold im μs t LOW Low Priod of L lock μs t HIGH High Priod of L lock μs t U: R ondition tup im μs t HD:D Data In Hold im 0 0 μs t U:D Data In tup im ns t R D and L Ris im ns t (2) F D and L Fall im ns t U:O OP ondition tup im μs t BUF Bus Fr im Btwn OP and R μs t L Low to Data Out Valid μs t DH Data Out Hold im ns (2) i Nois Puls Filtrd at L and D Inputs ns t U:WP WP tup im 0 0 μs t HD:WP WP Hold im μs t WR Writ ycl im 5 5 ms t (2, 3) PU Powr-up to Rady Mod 1 1 ms Not: (1) st conditions according to.. st onditions tabl. (2) std initially and aftr a dsign or procss chang that affcts this paramtr. (3) t PU is th dlay btwn th tim V is stabl and th dvic is rady to accpt commands... E ONDIION Input Lvls Input Ris and Fall ims Input Rfrnc Lvls Output Rfrnc Lvls Output Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrnt ourc: I OL = 3 m (V 2.5 V); I OL = 1 m (V < 2.5 V); L = 100 pf 2009 ILL. ll rights rsrvd. haractristics subjct to chang without notic 3 Doc No. MD-1102, Rv. L

4 2464 POWER-ON REE (POR) Each 2464 incorporats Powr-On Rst (POR) circuitry which protcts th intrnal logic against powring up in th wrong stat. h dvic will powr up into tandby mod aftr V xcds th POR triggr lvl and will powr down into Rst mod whn V drops blow th POR triggr lvl. his bi-dirctional POR bhavior protcts th dvic against brown-out failur following a tmporary loss of powr. PIN DERIPION L: h rial lock input pin accpts th clock signal gnratd by th Mastr. D: h rial Data I/O pin accpts input data and dlivrs output data. In transmit mod, this pin is opn drain. Data is acquird on th positiv dg, and is dlivrd on th ngativ dg of L. 0, 1 and 2 : h ddrss inputs st th dvic addrss that must b matchd by th corrsponding lav addrss bits. h ddrss inputs ar hard-wird HIGH or LOW allowing for up to ight dvics to b usd (cascadd) on th sam bus. Whn lft floating, ths pins ar pulld LOW intrnally. WP: Whn pulld HIGH, th Writ Protct input pin inhibits all writ oprations. Whn lft floating, this pin is pulld LOW intrnally. FUNIONL DERIPION h 2464 supports th Intr-Intgratd ircuit (I 2 ) Bus protocol. h protocol rlis on th us of a Mastr dvic, which provids th clock and dircts bus traffic, and lav dvics which xcut rqusts. h 2464 oprats as a lav dvic. Both Mastr and lav can transmit or rciv, but only th Mastr can assign thos rols. I 2 BU PROOOL h 2-wir I 2 bus consists of two lins, L and D, connctd to th V supply via pull-up rsistors. h Mastr provids th clock to th L lin, and ithr th Mastr or th lavs driv th D lin. 0 is transmittd by pulling a lin LOW and a 1 by ltting it stay HIGH. Data transfr may b initiatd only whn th bus is not busy (s.. haractristics). During data transfr, D must rmain stabl whil L is HIGH. R/OP ondition n D transition whil L is HIGH crats a R or OP condition (Figur 1). h R consists of a HIGH to LOW D transition, whil L is HIGH. bsnt th R, a lav will not rspond to th Mastr. h OP complts all commands, and consists of a LOW to HIGH D transition, whil L is HIGH. Dvic ddrssing h Mastr addrsss a lav by crating a R condition and thn broadcasting an 8-bit lav addrss. For th 2464, th first four bits of th lav addrss ar st to 1010 (h); th nxt thr bits, 2, 1 and 0, must match th logic stat of th similarly namd input pins. h R/W bit tlls th lav whthr th Mastr intnds to rad (1) or writ (0) data (Figur 2). cknowldg During th 9 th clock cycl following vry byt snt to th bus, th transmittr rlass th D lin, allowing th rcivr to rspond. h rcivr thn ithr acknowldgs () by pulling D LOW, or dos not acknowldg (No) by ltting D stay HIGH (Figur 3). Bus timing is illustratd in Figur 4. Doc. No. MD-1102, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic

5 2464 Figur 1. tart/top iming L D R ONDIION OP ONDIION Figur 2. lav ddrss Bits R/W DEVIE DDRE Figur 3. cknowldg iming BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUPU FROM RNMIER D OUPU FROM REEIVER R DELY ( t) EUP ( t U:D ) Figur 4. Bus iming t F t HIGH t R t LOW t LOW L t U: t HD:D t HD: t U:D t U:O D IN t t DH t BUF D OU 2009 ILL. ll rights rsrvd. haractristics subjct to chang without notic 5 Doc No. MD-1102, Rv. L

6 2464 WRIE OPERION Byt Writ o writ data to mmory, th Mastr crats a R condition on th bus and thn broadcasts a lav addrss with th R/W bit st to 0. h Mastr thn snds two addrss byts and a data byt and concluds th sssion by crating a OP condition on th bus. h lav rsponds with aftr vry byt snt by th Mastr (Figur 5). h OP starts th intrnal Writ cycl, and whil this opration is in progrss (t WR ), th D output is tri-statd and th lav dos not acknowldg th Mastr (Figur 6). Pag Writ h Byt Writ opration can b xpandd to Pag Writ, by snding mor than on data byt to th lav bfor issuing th OP condition (Figur 7). Up to 32 (1) distinct data byts can b loadd into th intrnal Pag Writ Buffr starting at th addrss providd by th Mastr. h pag addrss is latchd, and as long as th Mastr kps snding data, th intrnal byt addrss is incrmntd up to th nd of pag, whr it thn wraps around (within th pag). Nw data can thrfor rplac data loadd arlir. Following th OP, data loadd during th Pag Writ sssion will b writtn to mmory in a singl intrnal Writ cycl (t WR ). cknowldg Polling s soon (and as long) as intrnal Writ is in progrss, th lav will not acknowldg th Mastr. his fatur nabls th Mastr to immdiatly follow-up with a nw Rad or Writ rqust, rathr than wait for th maximum spcifid Writ tim (t WR ) to laps. Upon rciving a No rspons from th lav, th Mastr simply rpats th rqust until th lav rsponds with. Hardwar Writ Protction With th WP pin hld HIGH, th ntir mmory is protctd against Writ oprations. If th WP pin is lft floating or is groundd, it has no impact on th Writ opration. h stat of th WP pin is strobd on th last falling dg of L immdiatly prcding th 1 st data byt (Figur 8). If th WP pin is HIGH during th strob intrval, th lav will not acknowldg th data byt and th Writ rqust will b rjctd. Dlivry tat h 2464 is shippd rasd, i.., all byts ar FFh. Not: (1) 2464 Rv. D (Not Rcommndd for Nw Dsigns) has 64-Byt Pag Writ Buffr. Doc. No. MD-1102, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic

7 2464 Figur 5. Byt Writ qunc BU IVIY: MER R LVE DDRE DDRE a15 a8 DDRE a7 a0 D d7 d0 O P * * * P LVE * a15 a13 ar don't car bits. Figur 6. Writ ycl iming L D 8 th Bit Byt n t WR OP ONDIION R ONDIION DDRE Figur 7. Pag Writ qunc BU IVIY: MER R LVE DDRE DDRE DDRE D n D n+1 D n+p O P P LVE Figur 8. WP iming DDRE D L D a7 a0 d7 d0 tu:wp WP thd:wp 2009 ILL. ll rights rsrvd. haractristics subjct to chang without notic 7 Doc No. MD-1102, Rv. L

8 2464 RED OPERION Immdiat Rad o rad data from mmory, th Mastr crats a R condition on th bus and thn broadcasts a lav addrss with th R/W bit st to 1. h lav rsponds with and starts shifting out data rsiding at th currnt addrss. ftr rciving th data, th Mastr rsponds with No and trminats th sssion by crating a OP condition on th bus (Figur 9). h lav thn rturns to tandby mod. lctiv Rad o rad data rsiding at a spcific addrss, th slctd addrss must first b loadd into th intrnal addrss rgistr. his is don by starting a Byt Writ squnc, whrby th Mastr crats a R condition, thn broadcasts a lav addrss with th R/W bit st to 0 and thn snds two addrss byts to th lav. Rathr than complting th Byt Writ squnc by snding data, th Mastr thn crats a R condition and broadcasts a lav addrss with th R/W bit st to 1. h lav rsponds with aftr vry byt snt by th Mastr and thn snds out data rsiding at th slctd addrss. ftr rciving th data, th Mastr rsponds with No and thn trminats th sssion by crating a OP condition on th bus (Figur 10). quntial Rad If, aftr rciving data snt by th lav, th Mastr rsponds with, thn th lav will continu transmitting until th Mastr rsponds with No followd by OP (Figur 11). During quntial Rad th intrnal byt addrss is automatically incrmntd up to th nd of mmory, whr it thn wraps around to th bginning of mmory. Doc. No. MD-1102, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic

9 2464 Figur 9. Immdiat Rad qunc and iming BU IVIY: MER R LVE DDRE N O O P P LVE D L 8 9 D 8th Bit D OU NO OP Figur 10. lctiv Rad qunc BU IVIY: MER R LVE DDRE DDRE DDRE R LVE DDRE N O O P P LVE D Figur 11. quntial Rad qunc BU IVIY: MER LVE DDRE N O O P P LVE D n D n+1 D n+2 D n+x 2009 ILL. ll rights rsrvd. haractristics subjct to chang without notic 9 Doc No. MD-1102, Rv. L

10 2464 PGE OULINE DRWING MOP 8-Lad 3.0 x 3.0mm (Z) E E1 YMBOL MIN NOM MX b c D E E B L L REF L B θ 0º 6º OP VIEW D 2 DEIL 1 b c IDE VIEW END VIEW θ L2 L1 L DEIL For currnt ap and Rl information, download th PDF fil from: Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs (2) omplis with JEDE standard MO-187. Doc. No. MD-1102, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic

11 2464 PDIP 8-Lad 300mils (L) PIN # 1 IDENIFIION D E1 YMBOL MIN NOM MX b b c D E B E B L OP VIEW E 2 1 L b2 c b B IDE VIEW END VIEW For currnt ap and Rl information, download th PDF fil from: Nots: (1) ll dimnsions ar in millimtrs. (2) omplis with JEDE standard M ILL. ll rights rsrvd. haractristics subjct to chang without notic 11 Doc No. MD-1102, Rv. L

12 2464 OI 8-Lad 150mils (W) PIN # 1 IDENIFIION E1 E YMBOL MIN NOM MX b c D E E B h L θ 0º 8º OP VIEW D h 1 θ b L c IDE VIEW END VIEW For currnt ap and Rl information, download th PDF fil from: Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with JEDE standard M-012. Doc. No. MD-1102, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic

13 2464 OI 8-Lad 208mils (X) E1 E PIN#1 IDENIFIION OP VIEW D b 1 L c IDE VIEW END VIEW For currnt ap and Rl information, download th PDF fil from: Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with EIJ standard EDR ILL. ll rights rsrvd. haractristics subjct to chang without notic 13 Doc No. MD-1102, Rv. L

14 2464 OP 8-Lad (Y) b E1 E YMBOL MIN NOM MX b c D E E B L 1.00 REF L θ1 0 8 OP VIEW D 2 θ1 c 1 L1 L IDE VIEW END VIEW For currnt ap and Rl information, download th PDF fil from: Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with JEDE standard MO-153. Doc. No. MD-1102, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic

15 2464 DFN 8-Pad 3 x 4.9mm (ZD2) D DEIL DP IZE 2.6 x 3.3mm E E2 PIN #1 IDENIFIION PIN #1 IDENIFIION 1 D2 OP VIEW IDE VIEW BOOM VIEW YMBOL MIN NOM MX FRON VIEW REF b b D D E L E YP L DEIL For currnt ap and Rl information, download th PDF fil from: Nots: 1. ll dimnsions ar in millimtrs. ngls in dgr. 2. omplis with JEDE MO ILL. ll rights rsrvd. haractristics subjct to chang without notic 15 Doc No. MD-1102, Rv. L

16 2464 DFN 8-Pad 2 x 3mm (VP2) D b E E2 PIN#1 IDENIFIION PIN#1 INDEX RE 1 D2 L OP VIEW IDE VIEW BOOM VIEW YMBOL MIN NOM MX REF b FRON VIEW D D E E YP L For currnt ap and Rl information, download th PDF fil from: Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with JEDE spcification MO-229. Doc. No. MD-1102, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic

17 2464 EXMPLE OF ORDERING INFORMION Prfix Dvic # uffix 2464 Y I G 3 ompany ID Product Numbr 2464 mpratur Rang I = Industrial (-40 to +85 ) E = Extndd (-40 to +125 ) : ap & Rl 2: 2,000/Rl (4)(6) 3: 3,000/Rl Packag L: PDIP W: OI, JEDE X: OI, EIJ (4) Y: OP Z: MOP (5) ZD2: DFN (3x4.9) (6) VP2: DFN (2x3) Lad Finish G: NiPdu Blank: Matt-in (4) For Product op Mark ods, click hr: Nots: (1) ll packags ar RoH-compliant (Lad-fr, Halogn-fr). (2) h standard lad finish is NiPdu on pr-platd (PPF) lad frams. (3) h dvic usd in th abov xampl is a 2464YI-G3 (OP, Industrial mpratur, NiPdu, ap & Rl, 3,000/Rl). (4) For OI, EIJ (X) packag th standard lad finish is Mattw-in. his packag is availabl in 2,000/Rl, i XI-2. (5) For availability, plas contact your narst ON miconductor als offic. (6) DFN, ZD2 is only availabl in 2000 pcs/rl, i.., 2464ZD2I-G2. h DFN 3 x 4.9mm (ZD2) packag is not rcommndd for nw dsigns. (7) For additional packag and tmpratur options, plas contact your narst ON miconductor als offic ILL. ll rights rsrvd. haractristics subjct to chang without notic 17 Doc No. MD-1102, Rv. L

18 2464 REVIION HIORY Dat Rvision Dscription 07-Oct-2005 Initial Issu 16-Nov-2005 B Updat Ordring Information dd ap and Rl pcifications 02-Fb-2006 Updat Ordring Information 23-ug-2006 D Updatd dvic dscription, supporting txt and figurs, packag outlins, packag marking and ordring information. Updatd and r-formattd D.. haractristics prsntation. Updatd and r-formattd.. haractristics prsntation to rflct tandard (100 khz) and Fast (400 khz) opration ovr th full voltag rang. 08-p-2006 E Rmov Packag Marking 13-Fb-2007 F Updat DFN 8 Lad (3x4.9mm) packag 20-Mar-2007 G dd DFN 8 Lad (2x3mm) packag 29-Mar-2007 H Updat Pag Writ Buffr to 32-Byts (for 2464 Rv. E) 17-ug-2007 I Updat all Packag Outlin Drawings dd Extndd mpratur Rang Updat D.. Oprating haractristics tabl dd MD- to documnt numbr 25-pr-2008 J dd X Packag Updat Pin Impdanc haractristics dd op Mark wb link box 24-Oct-2008 hang logo and fin print to ON miconductor 14-Jan-2009 L dd MOP Packag ON miconductor and ar rgistrd tradmarks of miconductor omponnts Industris, LL (ILL). ILL rsrvs th right to mak changs without furthr notic to any products hrin. ILL maks no warranty, rprsntation or guarant rgarding th suitability of its products for any particular purpos, nor dos ILL assum any liability arising out of th application or us of any product or circuit, and spcifically disclaims any and all liability, including without limitation spcial, consquntial or incidntal damags. ypical paramtrs which may b providd in ILL data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including ypicals must b validatd for ach customr application by customr's tchnical xprts. ILL dos not convy any licns undr its patnt rights nor th rights of othrs. ILL products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th body, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th ILL product could crat a situation whr prsonal injury or dath may occur. hould Buyr purchas or us ILL products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold ILL and its officrs, mploys, subsidiaris, affiliats, and distributors harmlss against all claims, costs, damags, and xpnss, and rasonabl attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that ILL was nglignt rgarding th dsign or manufactur of th part. ILL is an Equal Opportunity/ffirmativ ction Employr. his litratur is subjct to all applicabl copyright laws and is not for rsal in any mannr. PUBLIION ORDERING INFORMION LIERURE FULFILLMEN: Litratur Distribution ntr for ON miconductor P.O. Box 5163, Dnvr, olorado U Phon: or oll Fr U/anada Fax: or oll Fr U/anada N. mrican chnical upport: oll Fr U/anada Europ, Middl East and frica chnical upport: Phon: Japan ustomr Focus ntr: Phon: ON miconductor Wbsit: Ordr Litratur: For additional information, plas contact your local als Rprsntativ Doc. No. MD-1102, Rv. L ILL. ll rights rsrvd. haractristics subjct to chang without notic