CAT24C Kb I 2 C CMOS Serial EEPROM

Transcription

1 b I 2 MO rial ROM scription h 2464 is a 64 b MO rial ROM dvic, intrnally organizd as 8192 words of 8 bits ach. It faturs a 32 byt pag writ buffr and supports th tandard (100 khz), Fast (400 khz) and Fast lus (1 MHz) I 2 protocol. xtrnal addrss pins mak it possibl to addrss up to ight 2464 dvics on th sam bus. Faturs upports tandard, Fast and Fast lus I 2 rotocol 1.7 V to 5.5 V upply Voltag Rang 32 Byt ag Writ Buffr Hardwar Writ rotction for ntir Mmory chmitt riggrs and Nois upprssion Filtrs on I 2 Bus Inputs (L and ) Low owr MO chnology 1,000,000 rogram/ras ycls 100 Yar ata Rtntion Industrial and xtndd mpratur Rang OI, O, UFN 8 pad and Ultra thin WL 4 bump ackags his vic is b Fr, Halogn Fr/BFR Fr, and RoH ompliant L 2, 1, 0 W V 2464 V Figur 1. Functional ymbol OI 8 W UFFIX 751B UFN 8 HU4 UFFIX 517Z IN ONFIGURION (op Viws) V OI (W), O (Y), UFN (HU4) MRING IGRM (WL 4) in Nam 0, 1, 2 L W V V O 8 Y UFFIX 948L WL 4 4 UFFIX 567JY V W L V 1 L (4) X YM X = pcific vic od = (s ordring information) Y = roduction Yar (Last igit) M = roduction Month (1 9, O, N, ) W = roduction Wk od For th location of in 1, plas consult th corrsponding packag drawing. IN FUNION 1 Function vic ddrss rial ata rial lock Writ rotct owr upply Ground WL 4 4U UFFIX 567B 2 B1 B2 WL (4U) X YW V ORRING INFORMION dtaild ordring and shipping information in th packag dimnsions sction on pag 13 of this data sht. For srial ROM in a U8 packag, plas consult th N2464 datasht. miconductor omponnts Industris, LL, 2018 pril, 2018 Rv ublication Ordr Numbr: 2464/

2 2464 abl 1. BOLU MXIMUM RING aramtrs Ratings Units torag mpratur 65 to +150 Voltag on ny in with Rspct to Ground (Not 1) 0.5 to +6.5 V trsss xcding thos listd in th Maximum Ratings tabl may damag th dvic. If any of ths limits ar xcdd, dvic functionality should not b assumd, damag may occur and rliability may b affctd. 1. h input voltag on any pin should not b lowr than 0.5 V or highr than V V. uring transitions, th voltag on any pin may undrshoot to no lss than 1.5 V or ovrshoot to no mor than V V, for priods of lss than 20 ns. abl 2. RLIBILIY HRRII (Not 2) ymbol aramtr Min Units N N (Not 3) nduranc 1,000,000 rogram/ras ycls R ata Rtntion 100 Yars 2. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat Q100 and J tst mthods. 3. ag Mod, V = 5 V, 25. abl 3... ORING HRRII (V = 1.8 V to 5.5 V, = 40 to +125 and V = 1.7 V to 5.5 V, = 40 to +85, unlss othrwis spcifid.) ymbol aramtr st onditions Min Max Units I R Rad urrnt Rad, f L = 400 khz 1 m I W Writ urrnt Writ, f L = 400 khz 2 m I B tandby urrnt ll I/O ins at GN or V = 40 to +85 V 3.3 V = 40 to +85 V > 3.3 V 1 3 = 40 to I L I/O in Lakag in at GN or V 2 V IL Input Low Voltag 0.5 V x 0.3 V V IH Input High Voltag V x 0.7 V V V OL1 Output Low Voltag V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltag V < 2.5 V, I OL = 1.0 m 0.2 V abl 4. IN IMN HRRII (V = 1.8 V to 5.5 V, = 40 to +125 and V = 1.7 V to 5.5 V, = 40 to +85, unlss othrwis spcifid.) ymbol aramtr onditions Max Units IN (Not 4) I/O in apacitanc V IN = 0 V 8 pf IN (Not 4) Input apacitanc (othr pins) V IN = 0 V 6 pf I W (Not 5) W Input urrnt V IN < V IH, V = 5.5 V 130 I (Not 5) ddrss Input urrnt (0, 1, 2) roduct Rv F V IN < V IH, V = 3.3 V 120 V IN < V IH, V = 1.8 V 80 V IN > V IH 2 V IN < V IH, V = 5.5 V 50 V IN < V IH, V = 3.3 V 35 V IN < V IH, V = 1.8 V 25 V IN > V IH 2 4. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat Q100 and J tst mthods. 5. Whn not drivn, th W, 0, 1 and 2 pins ar pulld down to GN intrnally. For improvd nois immunity, th intrnal pull down is rlativly strong; thrfor th xtrnal drivr must b abl to supply th pull down currnt whn attmpting to driv th input HIGH. o consrv powr, as th input lvl xcds th trip point of th MO input buffr (~ 0.5 x V ), th strong pull down rvrts to a wak currnt sourc. 2

3 2464 abl 5... HRRII (V = 1.8 V to 5.5 V, = 40 to +125 and V = 1.7 V to 5.5 V, = 40 to +85.) (Not 6) ymbol aramtr tandard V = 1.7 V 5.5 V Fast V = 1.7 V 5.5 V Fast lus V = 1.7 V 5.5 V = 40 to +85 Min Max Min Max Min Max F L lock Frquncy ,000 khz t H: R ondition Hold im s t LOW Low riod of L lock s t HIGH High riod of L lock s t U: R ondition tup im s t H: ata In Hold im s t U: ata In tup im ns t R (Not 7) and L Ris im 1, ns t F (Not 7) and L Fall im ns t U:O O ondition tup im s t BUF Bus Fr im Btwn O and R Units s t L Low to ata Out Valid s t H ata Out Hold im ns i (Not 7) Nois uls Filtrd at L and Inputs ns t U:W W tup im s t H:W W Hold im s t WR Writ ycl im ms t U (Nots 7, 8) owr up to Rady Mod ms roduct paramtric prformanc is indicatd in th lctrical haractristics for th listd tst conditions, unlss othrwis notd. roduct prformanc may not b indicatd by th lctrical haractristics if opratd undr diffrnt conditions. 6. st conditions according to.. st onditions tabl. 7. std initially and aftr a dsign or procss chang that affcts this paramtr. 8. t U is th dlay btwn th tim V is stabl and th dvic is rady to accpt commands. abl 6... ONIION Input Lvls Input Ris and Fall ims Input Rfrnc Lvls Output Rfrnc Lvls Output Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrnt ourc: I OL = 3 m (V 2.5 V); I OL = 1 m (V < 2.5 V); L = 100 pf 3

4 2464 owr On Rst (OR) ach 2464 incorporats owr On Rst (OR) circuitry which protcts th intrnal logic against powring up in th wrong stat. h dvic will powr up into tandby mod aftr V xcds th OR triggr lvl and will powr down into Rst mod whn V drops blow th OR triggr lvl. his bi dirctional OR bhavior protcts th dvic against brown out failur following a tmporary loss of powr. in scription L: h rial lock input pin accpts th clock signal gnratd by th Mastr. : h rial ata I/O pin accpts input data and dlivrs output data. In transmit mod, this pin is opn drain. ata is acquird on th positiv dg, and is dlivrd on th ngativ dg of L. 0, 1 and 2 : h ddrss inputs st th dvic addrss that must b matchd by th corrsponding lav addrss bits. h ddrss inputs ar hard wird HIGH or LOW allowing for up to ight dvics to b usd (cascadd) on th sam bus. Whn lft floating, ths pins ar pulld LOW intrnally. h ddrss inputs ar not availabl for us with WL 4 bumps. W: Whn pulld HIGH, th Writ rotct input pin inhibits all writ oprations. Whn lft floating, this pin is pulld LOW intrnally. h W input is not availabl for th WL 4 bumps, thrfor all writ oprations ar allowd for th dvic in this packag. Functional scription h 2464 supports th Intr Intgratd ircuit (I 2 ) Bus protocol. h protocol rlis on th us of a Mastr dvic, which provids th clock and dircts bus traffic, and lav dvics which xcut rqusts. h 2464 oprats as a lav dvic. Both Mastr and lav can transmit or rciv, but only th Mastr can assign thos rols. I 2 Bus rotocol h 2 wir I 2 bus consists of two lins, L and, connctd to th V supply via pull up rsistors. h Mastr provids th clock to th L lin, and ithr th Mastr or th lavs driv th lin. 0 is transmittd by pulling a lin LOW and a 1 by ltting it stay HIGH. ata transfr may b initiatd only whn th bus is not busy (s.. haractristics). uring data transfr, must rmain stabl whil L is HIGH. R/O ondition n transition whil L is HIGH crats a R or O condition (Figur 2). h R consists of a HIGH to LOW transition, whil L is HIGH. bsnt th R, a lav will not rspond to th Mastr. h O complts all commands, and consists of a LOW to HIGH transition, whil L is HIGH. vic ddrssing h Mastr addrsss a lav by crating a R condition and thn broadcasting an 8 bit lav addrss. For th 2464, th first four bits of th lav addrss ar st to 1010 (h); th nxt thr bits, 2, 1 and 0, must match th logic stat of th similarly namd input pins. h dvics in WL 4 bumps rspond only to th lav ddrss with = 000 (24644xR). h R/W bit tlls th lav whthr th Mastr intnds to rad (1) or writ (0) data (Figur 3). cknowldg uring th 9 th clock cycl following vry byt snt to th bus, th transmittr rlass th lin, allowing th rcivr to rspond. h rcivr thn ithr acknowldgs () by pulling LOW, or dos not acknowldg (No) by ltting stay HIGH (Figur 4). Bus timing is illustratd in Figur 5. L R ONIION Figur 2. tart/top iming O ONIION R/W VI R* * h dvics in WL 4 bumps rspond only to th lav ddrss with: = 000, 24644xR Figur 3. lav ddrss Bits 4

5 2464 BU RL LY (RNMIR) BU RL LY (RIVR) L FROM MR OUU FROM RNMIR OUU FROM RIVR R LY ( t ) Figur 4. cknowldg iming U ( t U: ) t F t HIGH t R t LOW t LOW L t U: t H: t H: t U: t U:O IN t t H t BUF OU Figur 5. Bus iming WRI ORION Byt Writ o writ data to mmory, th Mastr crats a R condition on th bus and thn broadcasts a lav addrss with th R/W bit st to 0. h Mastr thn snds two addrss byts and a data byt and concluds th sssion by crating a O condition on th bus. h lav rsponds with aftr vry byt snt by th Mastr (Figur 6). h O starts th intrnal Writ cycl, and whil this opration is in progrss (t WR ), th output is tri statd and th lav dos not acknowldg th Mastr (Figur 7). ag Writ h Byt Writ opration can b xpandd to ag Writ, by snding mor than on data byt to th lav bfor issuing th O condition (Figur 8). Up to 32 distinct data byts can b loadd into th intrnal ag Writ Buffr starting at th addrss providd by th Mastr. h pag addrss is latchd, and as long as th Mastr kps snding data, th intrnal byt addrss is incrmntd up to th nd of pag, whr it thn wraps around (within th pag). Nw data can thrfor rplac data loadd arlir. Following th O, data loadd during th ag Writ sssion will b writtn to mmory in a singl intrnal Writ cycl (t WR ). cknowldg olling s soon (and as long) as intrnal Writ is in progrss, th lav will not acknowldg th Mastr. his fatur nabls th Mastr to immdiatly follow up with a nw Rad or Writ rqust, rathr than wait for th maximum spcifid Writ tim (t WR ) to laps. Upon rciving a No rspons from th lav, th Mastr simply rpats th rqust until th lav rsponds with. Hardwar Writ rotction With th W pin hld HIGH, th ntir mmory is protctd against Writ oprations. If th W pin is lft floating or is groundd, it has no impact on th Writ opration. h stat of th W pin is strobd on th last falling dg of L immdiatly prcding th 1 st data byt (Figur 9). If th W pin is HIGH during th strob intrval, th lav will not acknowldg th data byt and th Writ rqust will b rjctd. livry tat h 2464 is shippd rasd, i.., all byts ar FFh. 5

6 2464 BU IVIY: MR R LV LV R *a 15 a 13 ar don t car bits. R R * * * a 15 a 8 a 7 a 0 d 7 d 0 Figur 6. Byt Writ qunc O L 8th Bit Byt n t WR O ONIION R ONIION R Figur 7. Writ ycl iming BU IVIY: MR R LV R R R n n+1 n+ O LV Figur 8. ag Writ qunc R L a 7 a 0 d 7 d 0 t U:W W t H:W Figur 9. W iming 6

7 2464 R ORION Immdiat Rad o rad data from mmory, th Mastr crats a R condition on th bus and thn broadcasts a lav addrss with th R/W bit st to 1. h lav rsponds with and starts shifting out data rsiding at th currnt addrss. ftr rciving th data, th Mastr rsponds with No and trminats th sssion by crating a O condition on th bus (Figur 10). h lav thn rturns to tandby mod. lctiv Rad o rad data rsiding at a spcific addrss, th slctd addrss must first b loadd into th intrnal addrss rgistr. his is don by starting a Byt Writ squnc, whrby th Mastr crats a R condition, thn broadcasts a lav addrss with th R/W bit st to 0 and thn snds two addrss byts to th lav. Rathr than complting th Byt Writ squnc by snding data, th Mastr thn crats a R condition and broadcasts a lav addrss with th R/W bit st to 1. h lav rsponds with aftr vry byt snt by th Mastr and thn snds out data rsiding at th slctd addrss. ftr rciving th data, th Mastr rsponds with No and thn trminats th sssion by crating a O condition on th bus (Figur 11). quntial Rad If, aftr rciving data snt by th lav, th Mastr rsponds with, thn th lav will continu transmitting until th Mastr rsponds with No followd by O (Figur 12). uring quntial Rad th intrnal byt addrss is automatically incrmntd up to th nd of mmory, whr it thn wraps around to th bginning of mmory. BU IVIY: MR R LV R N O O LV L 8 9 8th Bit OU NO Figur 10. Immdiat Rad qunc and iming O BU IVIY: MR R LV R R R R LV R N O O LV Figur 11. lctiv Rad qunc BU IVIY: MR LV R N O O LV n n+1 n+2 n+x Figur 12. quntial Rad qunc 7

8 2464 G IMNION OI 8, 150 mils 751B IU O YMBOL MIN NOM MX b c B h IN # 1 INIFIION L θ 0º 8º O VIW h 1 θ c b L I VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J M

9 2464 G IMNION b O8, 4.4x3 948L IU O YMBOL MIN NOM MX b c B L 1.00 RF L1 θ º 8º O VIW 2 1 c I VIW 1 L1 N VIW L Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J MO

10 2464 G IMNION UFN8, 2x3 XN 517Z IU IN ON RFRN NO IL 0.10 ÇÇ ÇÇ O VIW 1 I VIW IL B L B 3 L1 XO u ING LN L IL LRN ONRUION MOL M IL B LRN ONRUION L ÇÇÇ 1 3 8X 0.68 NO: 1. IMNIONING N OLRNING R M Y14.5M, ONROLLING IMNION: MILLIMR. 3. IMNION b LI O L RMINL N I MUR BWN 0.15 N 0.25MM FROM H RMINL I. 4. OLNRIY LI O H XO WLL H RMINL. MILLIMR IM MIN MX RF b B B B L L ROMMN OLRING FOORIN* BOOM VIW 8X b 0.10 M 0.05 M B NO IH 8X 0.30 IMNION: MILLIMR *For additional information on our b Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. 10

11 2464 G IMNION WL4, 0.76x JY IU NO 5 IN 1 RFRN NO 4 4X 0.05 b 0.05 B 0.03 IL B O VIW I VIW 1 2 BOOM VIW 2 B NO 3 ING LN NO 6 I O (OIONL) IL 3 2 NO: 1. IMNIONING N OLRNING R M Y14.5M, ONROLLING IMNION: MILLIMR. 3. UM, H ING LN, I FIN BY H HRIL ROWN OF H OLR BLL. 4. OLNRIY LI O HRIL ROWN OF H OLR BLL. 5. IMNION b I MUR H MXIMUM ON BLL IMR RLLL O UM. 6. BI OING I OIONL. MILLIMR IM MIN NOM MX RF RF b B ROMMN OLRING FOORIN* 0.40 IH 1 G OULIN 4X IH IMNION: MILLIMR *For additional information on our b Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. 11

12 2464 G IMNION NO 5 IN 1 RFRN NO 4 4X b 0.05 B 0.03 IL 1 B O VIW I VIW 1 2 BOOM VIW 2 B NO 3 ING LN WL4, 0.77x B IU NO 6 I O (OIONL) IL 3 2 NO: 1. IMNIONING N OLRNING R M Y14.5M, ONROLLING IMNION: MILLIMR. 3. UM, H ING LN, I FIN BY H HRIL ROWN OF H OLR BLL. 4. OLNRIY LI O HRIL ROWN OF H OLR BLL. 5. IMNION b I MUR H MXIMUM ON BLL IMR RLLL O UM. 6. BI OING I OIONL. MILLIMR IM MIN NOM MX RF RF b B ROMMN OLRING FOORIN* 0.40 IH 1 G OULIN 4X IH IMNION: MILLIMR *For additional information on our b Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. 12

13 2464 ORRING INFORMION vic Ordr Numbr pcific vic Marking ackag yp mpratur Rang Lad Finish hipping 2464WI G3 2464F OI 8, J I = Industrial ( 40 to +85 ) 2464YI G3 64F O 8 I = Industrial ( 40 to +85 ) 2464HU4I G3 6U UFN 8 I = Industrial ( 40 to +85 ) 24644R WL 4 with i oat 24644UR WL 4 with i oat Industrial ( 40 to +85 ) Industrial ( 40 to +85 ) Nidu Nidu Nidu N/ N/ ap & Rl, 3,000 Units / Rl ap & Rl, 3,000 Units / Rl ap & Rl, 3,000 Units / Rl ap & Rl, 5,000 Units / Rl ap & Rl, 5,000 Units / Rl 9. ll packags ar RoH compliant (Lad fr, Halogn fr). 10. h standard lad finish is Nidu. 11. For information on tap and rl spcifications, including part orintation and tap sizs, plas rfr to our ap and Rl ackaging pcifications Brochur, BR8011/. 12.aution: h ROM dvics dlivrd in WL must nvr b xposd to ultra violt light. Whn xposd to ultra violt light th ROM clls los thir stord data. ON miconductor is licnsd by hilips orporation to carry th I 2 Bus rotocol. ON miconductor and ar tradmarks of miconductor omponnts Industris, LL dba ON miconductor or its subsidiaris in th Unitd tats and/or othr countris. ON miconductor owns th rights to a numbr of patnts, tradmarks, copyrights, trad scrts, and othr intllctual proprty. listing of ON miconductor s product/patnt covrag may b accssd at /sit/pdf/atnt Marking.pdf. ON miconductor rsrvs th right to mak changs without furthr notic to any products hrin. ON miconductor maks no warranty, rprsntation or guarant rgarding th suitability of its products for any particular purpos, nor dos ON miconductor assum any liability arising out of th application or us of any product or circuit, and spcifically disclaims any and all liability, including without limitation spcial, consquntial or incidntal damags. Buyr is rsponsibl for its products and applications using ON miconductor products, including complianc with all laws, rgulations and safty rquirmnts or standards, rgardlss of any support or applications information providd by ON miconductor. ypical paramtrs which may b providd in ON miconductor data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including ypicals must b validatd for ach customr application by customr s tchnical xprts. ON miconductor dos not convy any licns undr its patnt rights nor th rights of othrs. ON miconductor products ar not dsignd, intndd, or authorizd for us as a critical componnt in lif support systms or any F lass 3 mdical dvics or mdical dvics with a sam or similar classification in a forign jurisdiction or any dvics intndd for implantation in th human body. hould Buyr purchas or us ON miconductor products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold ON miconductor and its officrs, mploys, subsidiaris, affiliats, and distributors harmlss against all claims, costs, damags, and xpnss, and rasonabl attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that ON miconductor was nglignt rgarding th dsign or manufactur of th part. ON miconductor is an qual Opportunity/ffirmativ ction mployr. his litratur is subjct to all applicabl copyright laws and is not for rsal in any mannr. UBLIION ORRING INFORMION LIRUR FULFILLMN: Litratur istribution ntr for ON miconductor nd kwy, urora, olorado U hon: or oll Fr U/anada Fax: or oll Fr U/anada mail: ordrlit@onsmi.com N. mrican chnical upport: oll Fr U/anada urop, Middl ast and frica chnical upport: hon: ON miconductor Wbsit: Ordr Litratur: For additional information, plas contact your local als Rprsntativ 2464/