CAT24C Kb I 2 C CMOS Serial EEPROM

Transcription

1 I 2 MO rial PROM scription h 2464 is a 64 MO rial PROM dvic, intrnally organizd as 8192 words of 8 its ach. It faturs a 32 yt pag writ uffr and supports th tandard (100 khz), Fast (400 khz) and Fast Plus (1 MHz) I 2 protocol. xtrnal addrss pins mak it possil to addrss up to ight 2464 dvics on th sam us. Faturs upports tandard, Fast and Fast Plus I 2 Protocol 1.7 V to 5.5 V upply Voltag Rang 32 Byt Pag Writ Buffr Hardwar Writ Protction for ntir Mmory chmitt riggrs and Nois upprssion Filtrs on I 2 Bus Inputs (L and ) Low Powr MO chnology 1,000,000 Program/ras ycls 100 Yar ata Rtntion Industrial and xtndd mpratur Rang PIP, OI, OP, U 8 lad, UFN 8 pad and Ultra thin WLP 4 ump Packags his vic is P Fr, Halogn Fr/BFR Fr, and RoH ompliant L 2, 1, 0 WP V 2464 V Figur 1. Functional ymol OI 8 W UFFIX 751B OI 8* X UFFIX 751B WLP 4 4 UFFIX 567JY OP 8 Y UFFIX 948L V PIP (L), OI (W, X), U (U), OP (Y), UFN (HU4) MRING IGRM (WLP 4) X Pin Nam 0, 1, 2 L WP V V UFN 8 HU4 UFFIX 517Z WLP 4 4U UFFIX 567PB PIN FUNION Function vic ddrss rial ata rial lock Writ Protct Powr upply Ground PIP 8 L UFFIX 646 PIN ONFIGURION (op Viws) V V WP 2 L L (4) X YM = pcific vic od U8** U UFFIX 493 B1 B2 WLP (4U) X YW = (s ordring information) Y = Production Yar (Last igit) M = Production Month (1 9, O, N, ) W = Production Wk od For th location of Pin 1, plas consult th corrsponding packag drawing. V ORRING INFORMION dtaild ordring and shipping information in th packag dimnsions sction on pag 16 of this data sht. * Not rcommndd for nw dsigns ** Prliminary; plas contact factory for availaility miconductor omponnts Industris, LL, 2015 Novmr, 2016 Rv Pulication Ordr Numr: 2464/

2 2464 al 1. BOLU MXIMUM RING Paramtrs Ratings Units torag mpratur 65 to +150 Voltag on ny Pin with Rspct to Ground (Not 1) 0.5 to +6.5 V trsss xcding thos listd in th Maximum Ratings tal may damag th dvic. If any of ths limits ar xcdd, dvic functionality should not assumd, damag may occur and rliaility may affctd. 1. h input voltag on any pin should not lowr than 0.5 V or highr than V V. uring transitions, th voltag on any pin may undrshoot to no lss than 1.5 V or ovrshoot to no mor than V V, for priods of lss than 20 ns. al 2. RLIBILIY HRRII (Not 2) ymol Paramtr Min Units N N (Not 3) nduranc 1,000,000 Program/ras ycls R ata Rtntion 100 Yars 2. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat Q100 and J tst mthods. 3. Pag Mod, V = 5 V, 25. al 3... OPRING HRRII (V = 1.8 V to 5.5 V, = 40 to +125 and V = 1.7 V to 5.5 V, = 40 to +85, unlss othrwis spcifid.) ymol Paramtr st onditions Min Max Units I R Rad urrnt Rad, f L = 400 khz 1 m I W Writ urrnt Writ, f L = 400 khz 2 m I B tandy urrnt ll I/O Pins at GN or V = 40 to +85 V 3.3 V = 40 to +85 V > 3.3 V 1 3 = 40 to I L I/O Pin Lakag Pin at GN or V 2 V IL Input Low Voltag 0.5 V x 0.3 V V IH Input High Voltag V x 0.7 V V V OL1 Output Low Voltag V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltag V < 2.5 V, I OL = 1.0 m 0.2 V al 4. PIN IMPN HRRII (V = 1.8 V to 5.5 V, = 40 to +125 and V = 1.7 V to 5.5 V, = 40 to +85, unlss othrwis spcifid.) ymol Paramtr onditions Max Units IN (Not 4) I/O Pin apacitanc V IN = 0 V 8 pf IN (Not 4) Input apacitanc (othr pins) V IN = 0 V 6 pf I WP (Not 5) WP Input urrnt V IN < V IH, V = 5.5 V 130 I (Not 5) ddrss Input urrnt (0, 1, 2) Product Rv F V IN < V IH, V = 3.3 V 120 V IN < V IH, V = 1.8 V 80 V IN > V IH 2 V IN < V IH, V = 5.5 V 50 V IN < V IH, V = 3.3 V 35 V IN < V IH, V = 1.8 V 25 V IN > V IH 2 4. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat Q100 and J tst mthods. 5. Whn not drivn, th WP, 0, 1 and 2 pins ar pulld down to GN intrnally. For improvd nois immunity, th intrnal pull down is rlativly strong; thrfor th xtrnal drivr must al to supply th pull down currnt whn attmpting to driv th input HIGH. o consrv powr, as th input lvl xcds th trip point of th MO input uffr (~ 0.5 x V ), th strong pull down rvrts to a wak currnt sourc. 2

3 2464 al 5... HRRII (V = 1.8 V to 5.5 V, = 40 to +125 and V = 1.7 V to 5.5 V, = 40 to +85.) (Not 6) ymol Paramtr tandard V = 1.7 V 5.5 V Fast V = 1.7 V 5.5 V Fast Plus (Not 9) V = 2.5 V 5.5 V = 40 to +85 Min Max Min Max Min Max F L lock Frquncy ,000 khz t H: R ondition Hold im s t LOW Low Priod of L lock s t HIGH High Priod of L lock s t U: R ondition tup im s t H: ata In Hold im s t U: ata In tup im ns t R (Not 7) and L Ris im 1, ns t F (Not 7) and L Fall im ns t U:O OP ondition tup im s t BUF Bus Fr im Btwn OP and R Units s t L Low to ata Out Valid s t H ata Out Hold im ns i (Not 7) Nois Puls Filtrd at L and Inputs ns t U:WP WP tup im s t H:WP WP Hold im s t WR Writ ycl im ms t PU (Nots 7, 8) Powr up to Rady Mod ms Product paramtric prformanc is indicatd in th lctrical haractristics for th listd tst conditions, unlss othrwis notd. Product prformanc may not indicatd y th lctrical haractristics if opratd undr diffrnt conditions. 6. st conditions according to.. st onditions tal. 7. std initially and aftr a dsign or procss chang that affcts this paramtr. 8. t PU is th dlay twn th tim V is stal and th dvic is rady to accpt commands. 9. Fast Plus (1 MHz) spd class availal for product rvision F. h di rvision F is idntifid y lttr F or a ddicatd marking cod on top of th packag. al 6... ONIION Input Lvls Input Ris and Fall ims Input Rfrnc Lvls Output Rfrnc Lvls Output Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrnt ourc: I OL = 3 m (V 2.5 V); I OL = 1 m (V < 2.5 V); L = 100 pf 3

4 2464 Powr On Rst (POR) ach 2464 incorporats Powr On Rst (POR) circuitry which protcts th intrnal logic against powring up in th wrong stat. h dvic will powr up into tandy mod aftr V xcds th POR triggr lvl and will powr down into Rst mod whn V drops low th POR triggr lvl. his i dirctional POR havior protcts th dvic against rown out failur following a tmporary loss of powr. Pin scription L: h rial lock input pin accpts th clock signal gnratd y th Mastr. : h rial ata I/O pin accpts input data and dlivrs output data. In transmit mod, this pin is opn drain. ata is acquird on th positiv dg, and is dlivrd on th ngativ dg of L. 0, 1 and 2 : h ddrss inputs st th dvic addrss that must matchd y th corrsponding lav addrss its. h ddrss inputs ar hard wird HIGH or LOW allowing for up to ight dvics to usd (cascadd) on th sam us. Whn lft floating, ths pins ar pulld LOW intrnally. h ddrss inputs ar not availal for us with WLP 4 umps. WP: Whn pulld HIGH, th Writ Protct input pin inhiits all writ oprations. Whn lft floating, this pin is pulld LOW intrnally. h WP input is not availal for th WLP 4 umps, thrfor all writ oprations ar allowd for th dvic in this packag. Functional scription h 2464 supports th Intr Intgratd ircuit (I 2 ) Bus protocol. h protocol rlis on th us of a Mastr dvic, which provids th clock and dircts us traffic, and lav dvics which xcut rqusts. h 2464 oprats as a lav dvic. Both Mastr and lav can transmit or rciv, ut only th Mastr can assign thos rols. I 2 Bus Protocol h 2 wir I 2 us consists of two lins, L and, connctd to th V supply via pull up rsistors. h Mastr provids th clock to th L lin, and ithr th Mastr or th lavs driv th lin. 0 is transmittd y pulling a lin LOW and a 1 y ltting it stay HIGH. ata transfr may initiatd only whn th us is not usy (s.. haractristics). uring data transfr, must rmain stal whil L is HIGH. R/OP ondition n transition whil L is HIGH crats a R or OP condition (Figur 2). h R consists of a HIGH to LOW transition, whil L is HIGH. snt th R, a lav will not rspond to th Mastr. h OP complts all commands, and consists of a LOW to HIGH transition, whil L is HIGH. vic ddrssing h Mastr addrsss a lav y crating a R condition and thn roadcasting an 8 it lav addrss. For th 2464, th first four its of th lav addrss ar st to 1010 (h); th nxt thr its, 2, 1 and 0, must match th logic stat of th similarly namd input pins. h dvics in WLP 4 umps rspond only to th lav ddrss with = 000 (24644R) or to = 100 (24644R). h R/W it tlls th lav whthr th Mastr intnds to rad (1) or writ (0) data (Figur 3). cknowldg uring th 9 th clock cycl following vry yt snt to th us, th transmittr rlass th lin, allowing th rcivr to rspond. h rcivr thn ithr acknowldgs () y pulling LOW, or dos not acknowldg (No) y ltting stay HIGH (Figur 4). Bus timing is illustratd in Figur 5. L R ONIION Figur 2. tart/top iming OP ONIION R/W VI R* * h dvics in WLP 4 umps rspond only to th lav ddrss with: = 000, 24644R * h dvics in WLP 4 umps rspond only to th lav ddrss with: = 100, 24644R Figur 3. lav ddrss Bits 4

5 2464 BU RL LY (RNMIR) BU RL LY (RIVR) L FROM MR OUPU FROM RNMIR OUPU FROM RIVR R LY ( t ) Figur 4. cknowldg iming UP ( t U: ) t F t HIGH t R t LOW t LOW L t U: t H: t H: t U: t U:O IN t t H t BUF OU Figur 5. Bus iming WRI OPRION Byt Writ o writ data to mmory, th Mastr crats a R condition on th us and thn roadcasts a lav addrss with th R/W it st to 0. h Mastr thn snds two addrss yts and a data yt and concluds th sssion y crating a OP condition on th us. h lav rsponds with aftr vry yt snt y th Mastr (Figur 6). h OP starts th intrnal Writ cycl, and whil this opration is in progrss (t WR ), th output is tri statd and th lav dos not acknowldg th Mastr (Figur 7). Pag Writ h Byt Writ opration can xpandd to Pag Writ, y snding mor than on data yt to th lav for issuing th OP condition (Figur 8). Up to 32 distinct data yts can loadd into th intrnal Pag Writ Buffr starting at th addrss providd y th Mastr. h pag addrss is latchd, and as long as th Mastr kps snding data, th intrnal yt addrss is incrmntd up to th nd of pag, whr it thn wraps around (within th pag). Nw data can thrfor rplac data loadd arlir. Following th OP, data loadd during th Pag Writ sssion will writtn to mmory in a singl intrnal Writ cycl (t WR ). cknowldg Polling s soon (and as long) as intrnal Writ is in progrss, th lav will not acknowldg th Mastr. his fatur nals th Mastr to immdiatly follow up with a nw Rad or Writ rqust, rathr than wait for th maximum spcifid Writ tim (t WR ) to laps. Upon rciving a No rspons from th lav, th Mastr simply rpats th rqust until th lav rsponds with. Hardwar Writ Protction With th WP pin hld HIGH, th ntir mmory is protctd against Writ oprations. If th WP pin is lft floating or is groundd, it has no impact on th Writ opration. h stat of th WP pin is strod on th last falling dg of L immdiatly prcding th 1 st data yt (Figur 9). If th WP pin is HIGH during th stro intrval, th lav will not acknowldg th data yt and th Writ rqust will rjctd. livry tat h 2464 is shippd rasd, i.., all yts ar FFh. 5

6 2464 BU IVIY: MR R LV LV R *a 15 a 13 ar don t car its. R R * * * a 15 a 8 a 7 a 0 d 7 d 0 Figur 6. Byt Writ qunc O P P L 8th Bit Byt n t WR OP ONIION R ONIION R Figur 7. Writ ycl iming BU IVIY: MR R LV R R R n n+1 n+p O P P LV Figur 8. Pag Writ qunc R L a 7 a 0 d 7 d 0 t U:WP WP t H:WP Figur 9. WP iming 6

7 2464 R OPRION Immdiat Rad o rad data from mmory, th Mastr crats a R condition on th us and thn roadcasts a lav addrss with th R/W it st to 1. h lav rsponds with and starts shifting out data rsiding at th currnt addrss. ftr rciving th data, th Mastr rsponds with No and trminats th sssion y crating a OP condition on th us (Figur 10). h lav thn rturns to tandy mod. lctiv Rad o rad data rsiding at a spcific addrss, th slctd addrss must first loadd into th intrnal addrss rgistr. his is don y starting a Byt Writ squnc, whry th Mastr crats a R condition, thn roadcasts a lav addrss with th R/W it st to 0 and thn snds two addrss yts to th lav. Rathr than complting th Byt Writ squnc y snding data, th Mastr thn crats a R condition and roadcasts a lav addrss with th R/W it st to 1. h lav rsponds with aftr vry yt snt y th Mastr and thn snds out data rsiding at th slctd addrss. ftr rciving th data, th Mastr rsponds with No and thn trminats th sssion y crating a OP condition on th us (Figur 11). quntial Rad If, aftr rciving data snt y th lav, th Mastr rsponds with, thn th lav will continu transmitting until th Mastr rsponds with No followd y OP (Figur 12). uring quntial Rad th intrnal yt addrss is automatically incrmntd up to th nd of mmory, whr it thn wraps around to th ginning of mmory. BU IVIY: MR R LV R N O OP P LV L 8 9 8th Bit OU NO Figur 10. Immdiat Rad qunc and iming OP BU IVIY: MR R LV R R R R LV R N O O P P LV Figur 11. lctiv Rad qunc BU IVIY: MR LV R N O O P P LV n n+1 n+2 n+x Figur 12. quntial Rad qunc 7

8 2464 PG IMNION PIP 8, 300 mils IU YMBOL MIN NOM MX PIN # 1 INIFIION c B B L OP VIW 2 1 L 2 c B I VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. (2) omplis with J M

9 2464 PG IMNION OI 8, 150 mils 751B 01 IU O YMBOL MIN NOM MX c B h PIN # 1 INIFIION L θ 0º 8º OP VIW h 1 θ c L I VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J M

10 2464 PG IMNION OI 8, 208 mils 751B 01 IU O YMBOL MIN NOM MX 1 1 c B L θ 0º 8º PIN#1 INIFIION OP VIW 1 L c I VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with IJ R

11 2464 PG IMNION OP8, 4.4x3 948L 01 IU O YMBOL MIN NOM MX c B L 1.00 RF L1 θ º 8º OP VIW 2 1 c I VIW 1 L1 N VIW L Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J MO

12 2464 PG IMNION UFN8, 2x3 XN P 517Z 01 IU O L P IZ 1.8 x PIN #1 INIFIION PIN #1 INX R 1 2 OP VIW I VIW BOOM VIW YMBOL MIN NOM MX RF RF IL FRON VIW RF L Nots: (1) ll dimnsions ar in millimtrs. (2) Rfr J MO-236/MO IL RF oppr xposd 12

13 2464 PG IMNION B 8 5 X L Y J U IU B IL NO: 1. IMNIONING N OLRNING PR NI Y14.5M, ONROLLING IMNION: MILLIMR. 3. IMNION O NO INLU MOL FLH, PRORUION OR G BURR. MOL FLH. PRORUION N G BURR HLL NO X MM ( ) PR I. 4. IMNION B O NO INLU INR L FLH OR PRORUION. INR L FLH N PRORUION HLL NO 3X ( ) PR I. 5. L FINIH I OLR PLING WIH HIN OF MM. ( ). 6. LL OLRN UNL OHRWI PIFI ± ( ). P ING PLN 1 4 G 0.10 (0.004) M X Y V R 0.10 (0.004) U N H R 0.10 YP M MILLIMR INH IM MIN MX MIN MX B F G 0.50 B B H 0.40 RF RF J L M N P R U V 0.12 B B IL F OLRING FOOPRIN* mm L 8:1 inchs *For additional information on our P Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. 13

14 2464 PG IMNION PIN 1 RFRN 2X 2X NO ÈÈ IL OP VIW I VIW 2 B ING PLN WLP4, 0.76x JY IU O I O (OPIONL) 3 IL 2 NO: 1. IMNIONING N OLRNING PR M Y14.5M, ONROLLING IMNION: MILLIMR. 3. OPLNRIY PPLI O PHRIL ROWN OF OLR BLL. MILLIMR IM MIN MX RF RF B 0.76 B 0.40 B ROMMN OLRING FOOPRIN* 1 PG OULIN 4X 0.05 B 0.03 B 1 2 BOOM VIW 0.40 PIH 4X PIH IMNION: MILLIMR *For additional information on our P Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. 14

15 2464 PG IMNION PIN 1 RFRN NO IL 1 OP VIW I VIW 2 B NO 3 ING PLN WLP4, 0.76x PB IU O NO 6 I O (OPIONL) IL 3 2 NO: 1. IMNIONING N OLRNING PR M Y14.5M, ONROLLING IMNION: MILLIMR. 3. UM, H ING PLN, I FIN BY H PHRIL ROWN OF H OLR BLL. 4. OPLNRIY PPLI O PHRIL ROWN OF H OLR BLL. 5. IMNION I MUR H MXIMUM ON BLL IMR PRLLL O UM. 6. BI OING I OPIONL. MILLIMR IM MIN NOM MX RF RF B NO 5 4X 0.05 B 0.03 B ROMMN OLRING FOOPRIN* 1 PG OULIN 1 2 BOOM VIW 0.40 PIH 4X PIH IMNION: MILLIMR *For additional information on our P Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. 15

16 2464 ORRING INFORMION vic Ordr Numr pcific vic Marking Packag yp mpratur Rang Lad Finish hipping 2464LI G 2464F PIP 8 I = Industrial ( 40 to +85 ) 2464W G3 (Not 12) 2464F OI 8, J = xtndd ( 40 to +125 ) 2464WI G3 2464F OI 8, J I = Industrial ( 40 to +85 ) 2464WI G 2464F OI 8, J I = Industrial ( 40 to +85 ) 2464XI F OI 8, IJ I = Industrial ( 40 to +85 ) 2464Y G3 (Not 12) 64F OP 8 = xtndd ( 40 to +125 ) 2464YI G3 64F OP 8 I = Industrial ( 40 to +85 ) 2464YI G 64F OP 8 I = Industrial ( 40 to +85 ) 2464HU4 G3 (Not 12) 6U UFN 8 = xtndd ( 40 to +125 ) 2464HU4I G3 6U UFN 8 I = Industrial ( 40 to +85 ) 24644R WLP 4 with i oat 24644R (Not 14) B WLP 4 with i oat 24644UR WLP 4 with i oat Industrial ( 40 to +85 ) Industrial ( 40 to +85 ) Industrial ( 40 to +85 ) 2464UI 3 (Not 12) B U8 I = Industrial ( 40 to +85 ) NiPdu NiPdu NiPdu NiPdu Matt in NiPdu NiPdu NiPdu NiPdu NiPdu N/ N/ N/ Matt in u, 50 Units / u ap & Rl, 3,000 Units / Rl ap & Rl, 3,000 Units / Rl u, 100 Units / u ap & Rl, 2,000 Units / Rl ap & Rl, 3,000 Units / Rl ap & Rl, 3,000 Units / Rl u, 100 Units / u ap & Rl, 3,000 Units / Rl ap & Rl, 3,000 Units / Rl ap & Rl, 5,000 Units / Rl ap & Rl, 5,000 Units / Rl ap & Rl, 5,000 Units / Rl ap & Rl, 3,000 Units / Rl 10. ll packags ar RoH compliant (Lad fr, Halogn fr). 11. h standard lad finish is NiPdu. 12. ontact factory for availaility. 13. For information on tap and rl spcifications, including part orintation and tap sizs, plas rfr to our ap and Rl Packaging pcifications Brochur, BR8011/. 14. Product in dvlopmnt; this WLP 4 option rsponds to a diffrnt lav ddrss compard to 24644R. 15.aution: h PROM dvics dlivrd in WLP must nvr xposd to ultra violt light. Whn xposd to ultra violt light th PROM clls los thir stord data. ON miconductor is licnsd y Philips orporation to carry th I 2 Bus Protocol. ON miconductor and ar tradmarks of miconductor omponnts Industris, LL da ON miconductor or its susidiaris in th Unitd tats and/or othr countris. ON miconductor owns th rights to a numr of patnts, tradmarks, copyrights, trad scrts, and othr intllctual proprty. listing of ON miconductor s product/patnt covrag may accssd at /sit/pdf/patnt Marking.pdf. ON miconductor rsrvs th right to mak changs without furthr notic to any products hrin. ON miconductor maks no warranty, rprsntation or guarant rgarding th suitaility of its products for any particular purpos, nor dos ON miconductor assum any liaility arising out of th application or us of any product or circuit, and spcifically disclaims any and all liaility, including without limitation spcial, consquntial or incidntal damags. Buyr is rsponsil for its products and applications using ON miconductor products, including complianc with all laws, rgulations and safty rquirmnts or standards, rgardlss of any support or applications information providd y ON miconductor. ypical paramtrs which may providd in ON miconductor data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including ypicals must validatd for ach customr application y customr s tchnical xprts. ON miconductor dos not convy any licns undr its patnt rights nor th rights of othrs. ON miconductor products ar not dsignd, intndd, or authorizd for us as a critical componnt in lif support systms or any F lass 3 mdical dvics or mdical dvics with a sam or similar classification in a forign jurisdiction or any dvics intndd for implantation in th human ody. hould Buyr purchas or us ON miconductor products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold ON miconductor and its officrs, mploys, susidiaris, affiliats, and distriutors harmlss against all claims, costs, damags, and xpnss, and rasonal attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that ON miconductor was nglignt rgarding th dsign or manufactur of th part. ON miconductor is an qual Opportunity/ffirmativ ction mployr. his litratur is sujct to all applical copyright laws and is not for rsal in any mannr. PUBLIION ORRING INFORMION LIRUR FULFILLMN: Litratur istriution ntr for ON miconductor nd Pkwy, urora, olorado U Phon: or oll Fr U/anada Fax: or oll Fr U/anada mail: ordrlit@onsmi.com N. mrican chnical upport: oll Fr U/anada urop, Middl ast and frica chnical upport: Phon: Japan ustomr Focus ntr Phon: ON miconductor Wsit: Ordr Litratur: For additional information, plas contact your local als Rprsntativ 2464/