CAT24C02, CAT24C04, CAT24C08, CAT24C16. EEPROM Serial 2/4/8/16 Kb I 2 C

Transcription

1 2402, 2404, 2408, 2416 PROM rial 2/4/8/16 b I 2 scription h 2402/04/08/16 ar 2 b, 4 b, 8 b and 16 b rspctivly I 2 rial PROM dvics organizd intrnally as 16/32/64 and 128 pags rspctivly of 16 byts ach. ll dvics support both th tandard (100 khz) as wll as Fast (400 khz) I 2 protocol. ata is writtn by providing a starting addrss, thn loading 1 to 16 contiguous byts into a Pag Writ Buffr, and thn writing all data to non volatil mmory in on intrnal writ cycl. ata is rad by providing a starting addrss and thn shifting out data srially whil automatically incrmnting th intrnal addrss count. xtrnal addrss pins mak it possibl to addrss up to ight 2402, four 2404, two 2408 and on 2416 dvic on th sam bus. Faturs upports tandard and Fast I 2 Protocol 1.7 V to 5.5 V upply Voltag Rang 16 Byt Pag Writ Buffr Hardwar Writ Protction for ntir Mmory chmitt riggrs and Nois upprssion Filtrs on I 2 Bus Inputs (L and ) Low powr MO chnology Mor than 1,000,000 Program/ras ycls 100 Yar ata Rtntion Industrial and xtndd mpratur Rang hs vics ar Pb Fr, Halogn Fr/BFR Fr and ar RoH ompliant his documnt contains information on som products that ar still undr dvlopmnt. ON miconductor rsrvs th right to chang or discontinu ths products without notic. OI 8 WI X UFFIX 751B OP 8 Y UFFIX 948L OI 8 W UFFIX 751B WLP 5** 5 UFFIX 567 UFN8 P HU4 UFFIX 517Z O 23 UFFIX 419 WLP 4** 4 UFFIX 567 WLP 4** 4U UFFIX 567NX ** WLP ar availabl for th 2404, 2408 and 2416 only. For srial PROM in th U8 packag, plas consult th N2402 datasht ORRING INFORMION dtaild ordring and shipping information in th packag dimnsions sction on pag 18 of this data sht. miconductor omponnts Industris, LL, 2016 May, 2018 Rv Publication Ordr Numbr: 2401/

2 2402, 2404, 2408, 2416 PIN ONFIGURION N MRING INFORMION V L 2, 1, 0 24xx WP V Figur 1. Functional ymbol abl 1. PIN FUNION Pin Nam Function 0, 1, 2 vic ddrss Input L WP V V N rial ata Input/Output rial lock Input Writ Protct Input Powr upply Ground No onnct h xposd pad for th UFN packags can b lft floating or connctd to Ground / 08 / 04 / 02 N / N / N / 0 N / N / 1 / 1 N / 2 / 2 / 2 V V WP L Pin 1 B 1 2 V V L Pin V V WP L B OI (W, X), OP (Y), UFN P (HU4) (op Viw) WLP 4*** (op Viws) WLP 5*** *** WLP ar availabl for th 2404, 2408 and 2416 only. L 1 5 WP Pin 1 OP MRING FOR WLP (Ball own) Pin 1 Pin 1 V V O 23 () (op Viw) X X X Y M Y W Y M WLP 4 (4) WLP 4 (4U) WLP 5 X = pcific vic X = od 4 or R = or = or V = 2416 Y = Production Yar (Last igit) M = Production Month (1 9, O, N, ) W = Production Wk 2

3 2402, 2404, 2408, 2416 abl 2. BOLU MXIMUM RING Paramtrs Ratings Units torag mpratur 65 to +150 Voltag on any pin with rspct to Ground (Not 1) 0.5 to +6.5 V trsss xcding thos listd in th Maximum Ratings tabl may damag th dvic. If any of ths limits ar xcdd, dvic functionality should not b assumd, damag may occur and rliability may b affctd. 1. uring input transitions, voltag undrshoot on any pin should not xcd 1 V for mor than 20 ns. Voltag ovrshoot on pins 0, 1, 2 and WP should not xcd V + 1 V for mor than 20 ns, whil voltag on th I 2 bus pins, L and, should not xcd th absolut maximum ratings, irrspctiv of V. abl 3. RLIBILIY HRRII (Not 2) ymbol Paramtr Min Units N N (Not 3) nduranc 1,000,000 Program / ras ycls R ata Rtntion 100 Yars 2. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat Q100 and J tst mthods. 3. Pag Mod, V = 5 V, 25. abl 4... OPRING HRRII (V = 1.8 V to 5.5 V, = 40 to +125 and V = 1.7 V to 5.5 V, = 40 to +85, unlss othrwis spcifid.) ymbol Paramtr st onditions Min Max Units I R Rad urrnt Rad, f L = 400 khz 1 m I W Writ urrnt Writ, f L = 400 khz 2 m I B tandby urrnt ll I/O Pins at GN or V = 40 to +85 V 3.3 V 1 = 40 to +85 V > 3.3 V 3 = 40 to I L I/O Pin Lakag Pin at GN or V 2 V IL Input Low Voltag x V V V IH Input High Voltag 0, 1, 2 and WP 0.7 x V V V V OL Output Low Voltag L and 0.7 x V 5.5 V > 2.5 V, I OL = 3 m 0.4 V < 2.5 V, I OL = 1 m 0.2 Product paramtric prformanc is indicatd in th lctrical haractristics for th listd tst conditions, unlss othrwis notd. Product prformanc may not b indicatd by th lctrical haractristics if opratd undr diffrnt conditions. 3

4 2402, 2404, 2408, 2416 abl 5. PIN IMPN HRRII (V = 1.8 V to 5.5 V, = 40 to +125 and V = 1.7 V to 5.5 V, = 40 to +85, unlss othrwis spcifid.) ymbol Paramtr onditions Max Units IN (Not 4) Pin apacitanc V IN = 0 V, f = 1.0 MHz, V = 5.0 V 8 pf Othr Pins 6 pf I WP (Not 5) WP Input urrnt V IN < V IH, V = 5.5 V 130 I (Not 5) ddrss Input urrnt (0, 1, 2) Product Rv H: 2402 Product Rv : 2404, 2408, 2416 V IN < V IH, V = 3.3 V 120 V IN < V IH, V = 1.7 V 80 V IN > V IH 2 V IN < V IH, V = 5.5 V 50 V IN < V IH, V = 3.3 V 35 V IN < V IH, V = 1.7 V 25 V IN > V IH 2 4. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat Q100 and J tst mthods. 5. Whn not drivn, th WP, 0, 1 and 2 pins ar pulld down to GN intrnally. For improvd nois immunity, th intrnal pull down is rlativly strong; thrfor th xtrnal drivr must b abl to supply th pull down currnt whn attmpting to driv th input HIGH. o consrv powr, as th input lvl xcds th trip point of th MO input buffr (~ 0.5 x V), th strong pull down rvrts to a wak currnt sourc. abl 6... HRRII (Not 6) (V = 1.8 V to 5.5 V, = 40 to +125 and V = 1.7 V to 5.5 V, = 40 to +85, unlss othrwis spcifid.) ymbol Paramtr tandard Fast Min Max Min Max F L lock Frquncy khz t H: R ondition Hold im s t LOW Low Priod of L lock s t HIGH High Priod of L lock s t U: R ondition tup im s t H: ata In Hold im 0 0 s t U: ata In tup im ns t R and L Ris im ns t F (Not 6) and L Fall im ns t U:O OP ondition tup im s t BUF Bus Fr im Btwn OP and R s t L Low to ata Out Valid s t H ata Out Hold im ns i (Not 6) Nois Puls Filtrd at L and Inputs ns t U:WP WP tup im 0 0 s t H:WP WP Hold im s t WR Writ ycl im 5 5 ms t PU (Nots 7, 8) Powr up to Rady Mod 1 1 ms 6. st conditions according to st onditions tabl. 7. std initially and aftr a dsign or procss chang that affcts this paramtr. 8. t PU is th dlay btwn th tim V is stabl and th dvic is rady to accpt commands. Units 4

5 2402, 2404, 2408, 2416 abl 7... ONIION Input riv Lvls Input Ris and Fall im Input Rfrnc Lvls Output Rfrnc Lvl Output st Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrnt ourc I OL = 3 m (V 2.5 V); I OL = 1 m (V < 2.5 V); L = 100 pf Powr On Rst (POR) ach 24xx* incorporats Powr On Rst (POR) circuitry which protcts th intrnal logic against powring up in th wrong stat. 24xx dvic will powr up into tandby mod aftr V xcds th POR triggr lvl and will powr down into Rst mod whn V drops blow th POR triggr lvl. his bi dirctional POR fatur protcts th dvic against brown out failur following a tmporary loss of powr. *For common faturs, th 2402/04/08/16 will b rfrrd to as 24xx. Pin scription L: h rial lock input pin accpts th rial lock gnratd by th Mastr. : h rial ata I/O pin rcivs input data and transmits data stord in PROM. In transmit mod, this pin is opn drain. ata is acquird on th positiv dg, and is dlivrd on th ngativ dg of L. 0, 1 and 2: h ddrss inputs st th dvic addrss whn cascading multipl dvics. Whn not drivn, ths pins ar pulld LOW intrnally. WP: h Writ Protct input pin inhibits all writ oprations, whn pulld HIGH. Whn not drivn, this pin is pulld LOW intrnally. Functional scription h 24xx supports th Intr Intgratd ircuit (I 2 ) Bus data transmission protocol, which dfins a dvic that snds data to th bus as a transmittr and a dvic rciving data as a rcivr. ata flow is controlld by a Mastr dvic, which gnrats th srial clock and all R and OP conditions. h 24xx acts as a lav dvic. Mastr and lav altrnat as ithr transmittr or rcivr. I 2 Bus Protocol h I 2 bus consists of two wirs, L and. h two wirs ar connctd to th V supply via pull up rsistors. Mastr and lav dvics connct to th 2 wir bus via thir rspctiv L and pins. h transmitting dvic pulls down th lin to transmit a 0 and rlass it to transmit a 1. ata transfr may b initiatd only whn th bus is not busy (s haractristics). uring data transfr, th lin must rmain stabl whil th L lin is high. n transition whil L is high will b intrprtd as a R or OP condition (Figur 2). h R condition prcds all commands. It consists of a HIGH to LOW transition on whil L is HIGH. h R acts as a wak up call to all rcivrs. bsnt a R, a lav will not rspond to commands. h OP condition complts all commands. It consists of a LOW to HIGH transition on whil L is HIGH. NO: h I/O pins of 24xx do not obstruct th L and lins if th V supply is switchd off. uring powr up, th L and pins (connctd with pull up rsistors to V) will follow th V monotonically from V (0 V) to nominal V valu, rgardlss of pull up rsistor valu. h dlta btwn th V and th instantanous voltag lvls during powr ramping will b dtrmind by th rlation btwn bus tim constant (dtrmind by pull up rsistanc and bus capacitanc) and actual V ramp rat. vic ddrssing h Mastr initiats data transfr by crating a R condition on th bus. h Mastr thn broadcasts an 8 bit srial lav addrss. For normal Rad/Writ oprations, th first 4 bits of th lav addrss ar fixd at 1010 (h). h nxt 3 bits ar usd as programmabl addrss bits whn cascading multipl dvics and/or as intrnal addrss bits. h last bit of th slav addrss, R/W, spcifis whthr a Rad (1) or Writ (0) opration is to b prformd. h 3 addrss spac xtnsion bits ar assignd as illustratd in Figur 3. 2, 1 and 0 must match th stat of th xtrnal addrss pins, and a 10, a 9 and a 8 ar intrnal addrss bits. cknowldg ftr procssing th lav addrss, th lav rsponds with an acknowldg () by pulling down th lin during th 9th clock cycl (Figur 4). h lav will also acknowldg th addrss byt and vry data byt prsntd in Writ mod. In Rad mod th lav shifts out a data byt, and thn rlass th lin during th 9 th clock cycl. s long as th Mastr acknowldgs th data, th lav will continu transmitting. h Mastr trminats th sssion by not acknowldging th last data byt (No) and by issuing a OP condition. Bus timing is illustratd in Figur 5. 5

6 2402, 2404, 2408, 2416 L R ONIION OP ONIION Figur 2. tart/top iming R/W a 8 R/W a 9 a 8 R/W a 10 a 9 a 8 R/W 2416 Figur 3. lav ddrss Bits L FROM MR BU RL LY (RNMIR) BU RL LY (RIVR) OUPU FROM RNMIR OUPU FROM RIVR R LY ( t ) Figur 4. cknowldg iming UP ( t U: ) t F t HIGH t R t LOW t LOW L t U: t H: t H: t U: t U:O IN t t H t BUF OU Figur 5. Bus iming 6

7 2402, 2404, 2408, 2416 WRI OPRION Byt Writ In Byt Writ mod, th Mastr snds th R condition and th lav addrss with th R/W bit st to zro to th lav. ftr th lav gnrats an acknowldg, th Mastr snds th byt addrss that is to b writtn into th addrss pointr of th 24xx. ftr rciving anothr acknowldg from th lav, th Mastr transmits th data byt to b writtn into th addrssd mmory location. h 24xx dvic will acknowldg th data byt and th Mastr gnrats th OP condition, at which tim th dvic bgins its intrnal Writ cycl to nonvolatil mmory (Figur 6). Whil this intrnal cycl is in progrss (t WR ), th output will b tri statd and th 24xx will not rspond to any rqust from th Mastr dvic (Figur 7). Pag Writ h 24xx writs up to 16 byts of data in a singl writ cycl, using th Pag Writ opration (Figur 8). h Pag Writ opration is initiatd in th sam mannr as th Byt Writ opration, howvr instad of trminating aftr th data byt is transmittd, th Mastr is allowd to snd up to fiftn additional byts. ftr ach byt has bn transmittd th 24xx will rspond with an acknowldg and intrnally incrmnts th four low ordr addrss bits. h high ordr bits that dfin th pag addrss rmain unchangd. If th Mastr transmits mor than sixtn byts prior to snding th OP condition, th addrss countr wraps around to th bginning of pag and prviously transmittd data will b ovrwrittn. Onc all sixtn byts ar rcivd and th OP condition has bn snt by th Mastr, th intrnal Writ cycl bgins. t this point all rcivd data is writtn to th 24xx in a singl writ cycl. cknowldg Polling h acknowldg () polling routin can b usd to tak advantag of th typical writ cycl tim. Onc th stop condition is issud to indicat th nd of th host s writ opration, th 24xx initiats th intrnal writ cycl. h polling can b initiatd immdiatly. his involvs issuing th start condition followd by th slav addrss for a writ opration. If th 24xx is still busy with th writ opration, No will b rturnd. If th 24xx has compltd th intrnal writ opration, an will b rturnd and th host can thn procd with th nxt rad or writ opration. Hardwar Writ Protction With th WP pin hld HIGH, th ntir mmory is protctd against Writ oprations. If th WP pin is lft floating or is groundd, it has no impact on th opration of th 24xx. h stat of th WP pin is strobd on th last falling dg of L immdiatly prcding th first data byt (Figur 9). If th WP pin is HIGH during th strob intrval, th 24xx will not acknowldg th data byt and th Writ rqust will b rjctd. livry tat h 24xx is shippd rasd, i.., all byts ar FFh. BU IVIY: MR R LV R R a 7 a 0 d 7 d 0 O P P LV Figur 6. Byt Writ qunc 7

8 2402, 2404, 2408, 2416 L 8th Bit Byt n t WR OP ONIION Figur 7. Writ ycl iming R ONIION R BU IVIY: MR R LV R R n n+1 n+p O P P LV n = 1 P 15 Figur 8. Pag Writ qunc R L a 7 a 0 d 7 d 0 t U:WP WP t H:WP Figur 9. WP iming 8

9 Immdiat Rad Upon rciving a lav addrss with th R/W bit st to 1, th 24xx will intrprt this as a rqust for data rsiding at th currnt byt addrss in mmory. h 24xx will acknowldg th lav addrss, will immdiatly shift out th data rsiding at th currnt addrss, and will thn wait for th Mastr to rspond. If th Mastr dos not acknowldg th data (No) and thn follows up with a OP condition (Figur 10), th 24xx rturns to tandby mod. lctiv Rad lctiv Rad oprations allow th Mastr dvic to slct at random any mmory location for a rad opration. h Mastr dvic first prforms a dummy writ opration by snding th R condition, slav addrss and byt 2402, 2404, 2408, 2416 R OPRION addrss of th location it wishs to rad. ftr th 24xx acknowldgs th byt addrss, th Mastr dvic rsnds th R condition and th slav addrss, this tim with th R/W bit st to on. h 24xx thn rsponds with its acknowldg and snds th rqustd data byt. h Mastr dvic dos not acknowldg th data (No) but will gnrat a OP condition (Figur 11). quntial Rad If during a Rad sssion, th Mastr acknowldgs th 1 st data byt, thn th 24xx will continu transmitting data rsiding at subsqunt locations until th Mastr rsponds with a No, followd by a OP (Figur 12). In contrast to Pag Writ, during quntial Rad th addrss count will automatically incrmnt to and thn wrap around at nd of mmory (rathr than nd of pag). BU IVIY: N O MR R LV R OP P LV L 8 9 8th Bit OU NO Figur 10. Immdiat Rad qunc and iming OP BU IVIY: MR R LV R R R LV R N O O P P BU IVIY: LV Figur 11. lctiv Rad qunc N O MR LV R O P P LV n n+1 n+2 n+x Figur 12. quntial Rad qunc 9

10 2402, 2404, 2408, 2416 PG IMNION OI 8, 208 mils 751B 01 IU O YMBOL MIN NOM MX 1 1 b c B L θ 0º 8º PIN#1 INIFIION OP VIW b 1 L c I VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with IJ R

11 2402, 2404, 2408, 2416 PG IMNION OI 8, 150 mils 751B IU O YMBOL MIN NOM MX b c B h PIN # 1 INIFIION L θ 0º 8º OP VIW h 1 θ c b L I VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J M

12 2402, 2404, 2408, 2416 PG IMNION b OP8, 4.4x3 948L IU O YMBOL MIN NOM MX b c B L 1.00 RF L1 θ º 8º OP VIW 2 1 c I VIW 1 L1 N VIW L Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J MO

13 2402, 2404, 2408, 2416 PG IMNION O 23, 5 L 419 IU O YMBOL 1 MIN NOM MX b c B 2.80 B B 0.95 YP L L RF L B OP VIW θ 0º 8º 2 b 1 L1 L c L2 I VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J MO

14 2402, 2404, 2408, 2416 PG IMNION UFN8, 2x3 XN P 517Z IU O b L P IZ 1.8 x PIN #1 INIFIION PIN #1 INX R 1 2 OP VIW I VIW BOOM VIW YMBOL MIN NOM MX RF b RF IL FRON VIW RF L Nots: (1) ll dimnsions ar in millimtrs. (2) Rfr J MO-236/MO IL RF oppr xposd 14

15 2402, 2404, 2408, 2416 PG IMNION PIN 1 RFRN NO 4 IL ÈÈ B OP VIW 1 I VIW OPIONL BI O ING PLN NO 3 WLP4, 0.84x NX IU IL 3 2 NO: 1. IMNIONING N OLRNING PR M Y14.5M, ONROLLING IMNION: MILLIMR. 3. UM, H ING PLN, I FIN BY H PHRIL ROWN OF H ON BLL. 4. OPLNRIY PPLI O PHRIL ROWN OF H ON BLL. 5. IMNION b I MUR H MXIMUM ON BLL IMR PRLLL O UM. MILLIMR IM MIN NOM MX RF RF b B 4X b 0.05 B 0.03 NO 5 B 1 2 BOOM VIW ROMMN OLRING FOOPRIN* PIH PG OULIN 4X PIH IMNION: MILLIMR *For additional information on our Pb Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. 15

16 2402, 2404, 2408, 2416 PG IMNION WLP4, 0.84x IU PIN 1 RFRN 2X 2X NO IL ÈÈ B OP VIW 1 I VIW 2 * i oat (Optional) ING PLN NO 3 IL 3* 2 NO: 1. IMNIONING N OLRNING PR M Y14.5M, ONROLLING IMNION: MILLIMR. 3. UM, H ING PLN, I FIN BY H PHRIL ROWN OF H ON BLL. 4. OPLNRIY PPLI O PHRIL ROWN OF H ON BLL. 5. IMNION b I MUR H MXIMUM ON BLL IMR PRLLL O UM. MILLIMR IM MIN MX RF 3* RF b B 0.86 B 0.40 B * i oat (Optional) 4X b 0.10 M B NO 5 B ROMMN OLRING FOOPRIN* 1 PG OULIN 1 2 BOOM VIW 0.40 PIH 4X PIH IMNION: MILLIMR *For additional information on our Pb Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. 16

17 2402, 2404, 2408, 2416 PG IMNION WLP5, 0.86x IU 5X PIN 1 RFRN 2X 2X NO ÈÈ B OP VIW 1 I VIW 2 ING PLN NO: 1. IMNIONING N OLRNING PR M Y14.5M, ONROLLING IMNION: MILLIMR. 3. UM, H ING PLN, I FIN BY H PHRIL ROWN OF H ON BLL. 4. OPLNRIY PPLI O PHRIL ROWN OF H ON BLL. 5. IMNION b I MUR H MXIMUM ON- BLL IMR PRLLL O UM. MILLIMR IM MIN MX RF b B 0.84 B 0.30 B B NO 4 5X b 0.10 M B PIN 1 RFRN B BOOM VIW 1 ROMMN OLRING FOOPRIN* PIH PG OULIN 5X PIH IMNION: MILLIMR *For additional information on our Pb Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. 17

18 Ordring Information 2402 Ordring Information (Nots 10, 11) vic Ordr Numbr 2402, 2404, 2408, 2416 pcific vic Marking Packag yp mpratur Rang (Not 9) Lad Finish hipping 2402I G3 1 O 23 5 Industrial NiPdu ap & Rl, 3,000 Units / Rl 2404 Ordring Information vic Ordr Numbr pcific vic Marking Packag yp mpratur Rang (Not 9) Lad Finish hipping 2404WI G OI 8 Industrial NiPdu ap & Rl, 3,000 Units / Rl 2404XI 2 (Not 17) B OI 8 Industrial Matt in ap & Rl, 2,000 Units / Rl 2404YI G3 04 OP 8 Industrial NiPdu ap & Rl, 3,000 Units / Rl 24044UR R WLP 4 Industrial N/ (Nots 12 and 13) 24044R 4 WLP 4 Industrial N/ ap & Rl, 5,000 Units / Rl 24045R 4 WLP 5 Industrial N/ ap & Rl, 5,000 Units / Rl 2404I G3 2 O 23 5 Industrial NiPdu ap & Rl, 3,000 Units / Rl 2404HU4I G3 2U UFN8 P Industrial NiPdu ap & Rl, 3,000 Units / Rl 2408 Ordring Information vic Ordr Numbr pcific vic Marking Packag yp mpratur Rang (Not 9) Lad Finish hipping 2408WI G OI 8 Industrial NiPdu ap & Rl, 3,000 Units / Rl 2408XI 2 (Not 17) B OI 8 Industrial Matt in ap & Rl, 2,000 Units / Rl 2408YI G3 08 OP 8 Industrial NiPdu ap & Rl, 3,000 Units / Rl 24084UR WLP 4 Industrial N/ (Nots 12 and 13) 24084R 8 WLP 4 Industrial N/ ap & Rl, 5,000 Units / Rl 24084R** 8 WLP 4 Industrial N/ ap & Rl, 5,000 Units / Rl 24085R 8 WLP 5 Industrial N/ ap & Rl, 5,000 Units / Rl 2408I G3 3 O 23 5 Industrial NiPdu ap & Rl, 3,000 Units / Rl 2408HU4I G3 3U UFN8 P Industrial NiPdu ap & Rl, 3,000 Units / Rl 2416 Ordring Information vic Ordr Numbr pcific vic Marking Packag yp mpratur Rang (Not 9) Lad Finish hipping 2416WI G OI 8 Industrial NiPdu ap & Rl, 3,000 Units / Rl 2416XI 2 (Not 17) B OI 8 Industrial Matt in ap & Rl, 2,000 Units / Rl 2416YI G3 16 OP 8 Industrial NiPdu ap & Rl, 3,000 Units / Rl 24164UR 6 WLP 4 Industrial N/ (Nots 12 and 13) 24164R 6 WLP 4 Industrial N/ ap & Rl, 5,000 Units / Rl 24165R 6 WLP 5 Industrial N/ ap & Rl, 5,000 Units / Rl 2416I G3 4 O 23 5 Industrial NiPdu ap & Rl, 3,000 Units / Rl 2416HU4I G3 4U UFN8 P Industrial NiPdu ap & Rl, 3,000 Units / Rl 9. Industrial tmpratur rang is 40 to +85 and xtndd tmpratur rang is 40 to Part numbrs nding with for th 2402 ar for Grsham (Product Rv H) only di. 11. h 2402 non vic Ordr Numbrs us Grsham di (Rv H) for dat cods, starting ugust 1st, hrfor th pcific vic Marking for ths OPNs rflct Rv H di. 12. ontact local sals offic for availability. 13. UION: h PROM dvics dlivrd in WLP must nvr b xposd to ultraviolt light. Whn xposd to ultraviolt light th PROM clls los thir stord data. 14. ll packags ar RoH compliant (Lad fr, Halogn fr). 15. For information on tap and rl spcifications, including part orintation and tap sizs, plas rfr to our ap and Rl Packaging pcifications Brochur, BR8011/. 16. For dtaild information and a brakdown of dvic nomnclatur and numbring systms, plas s th ON miconductor vic Nomnclatur documnt, N310/, availabl at 17. In vlopmnt ** 24084R is a backsid coatd vrsion. ontact factory for othr dnsitis. 18

19 2402, 2404, 2408, 2416 ON miconductor and ar tradmarks of miconductor omponnts Industris, LL dba ON miconductor or its subsidiaris in th Unitd tats and/or othr countris. ON miconductor owns th rights to a numbr of patnts, tradmarks, copyrights, trad scrts, and othr intllctual proprty. listing of ON miconductor s product/patnt covrag may b accssd at /sit/pdf/patnt Marking.pdf. ON miconductor rsrvs th right to mak changs without furthr notic to any products hrin. ON miconductor maks no warranty, rprsntation or guarant rgarding th suitability of its products for any particular purpos, nor dos ON miconductor assum any liability arising out of th application or us of any product or circuit, and spcifically disclaims any and all liability, including without limitation spcial, consquntial or incidntal damags. Buyr is rsponsibl for its products and applications using ON miconductor products, including complianc with all laws, rgulations and safty rquirmnts or standards, rgardlss of any support or applications information providd by ON miconductor. ypical paramtrs which may b providd in ON miconductor data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including ypicals must b validatd for ach customr application by customr s tchnical xprts. ON miconductor dos not convy any licns undr its patnt rights nor th rights of othrs. ON miconductor products ar not dsignd, intndd, or authorizd for us as a critical componnt in lif support systms or any F lass 3 mdical dvics or mdical dvics with a sam or similar classification in a forign jurisdiction or any dvics intndd for implantation in th human body. hould Buyr purchas or us ON miconductor products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold ON miconductor and its officrs, mploys, subsidiaris, affiliats, and distributors harmlss against all claims, costs, damags, and xpnss, and rasonabl attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that ON miconductor was nglignt rgarding th dsign or manufactur of th part. ON miconductor is an qual Opportunity/ffirmativ ction mployr. his litratur is subjct to all applicabl copyright laws and is not for rsal in any mannr. PUBLIION ORRING INFORMION LIRUR FULFILLMN: Litratur istribution ntr for ON miconductor nd Pkwy, urora, olorado U Phon: or oll Fr U/anada Fax: or oll Fr U/anada mail: ordrlit@onsmi.com N. mrican chnical upport: oll Fr U/anada urop, Middl ast and frica chnical upport: Phon: ON miconductor Wbsit: Ordr Litratur: For additional information, plas contact your local als Rprsntativ 2401/