CAT24C kb CMOS Serial EEPROM, Cascadable

Transcription

1 kb MO rial EEROM, ascadabl Dscription h is a 16 kb MO cascadabl rial EEROM dvic organizd intrnally as 128 pags of 16 byts ach, for a total of 2048 x 8 bits. h dvic supports both th tandard (100 khz) as wll as Fast (400 khz) I 2 protocol. Data is writtn by providing a starting addrss, thn loading 1 to 16 contiguous byts into a ag Writ Buffr, and thn writing all data to non volatil mmory in on intrnal writ cycl. Data is rad by providing a starting addrss and thn shifting out data srially whil automatically incrmnting th intrnal addrss count. Extrnal addrss pins mak it possibl to addrss up to ight dvics on th sam bus. Faturs upports tandard and Fast I 2 rotocol 1.8 V to 5.5 V upply Voltag Rang 16 Byt ag Writ Buffr Hardwar Writ rotction for Entir Mmory chmitt riggrs and Nois upprssion Filtrs on I 2 Bus Inputs (L and D) Low owr MO chnology 1,000,000 rogram/eras ycls 100 Yar Data Rtntion Industrial mpratur Rang DI, OI, O and DFN 8 lad ackags his Dvic is b Fr, Halogn Fr/BFR Fr, and RoH ompliant V OI 8 W UFFIX E 751BD DI 8 L UFFIX E 646 IN ONFIGURION V DFN 8 V2 UFFIX E 511 O 8 Y UFFIX E 948L DI (L), OI (W), O (Y), DFN (V2) (op Viw) V W L D For th location of in 1, plas consult th corrsponding packag drawing. IN FUNION L in Nam Function 2, 1, D 0, 1, 2 D Dvic ddrss Inputs rial Data Input/Output W L rial lock Input W Writ rotct Input V Figur 1. Functional ymbol V V owr upply Ground ORDERING INFORMION dtaild ordring and shipping information in th packag dimnsions sction on pag 14 of this data sht. miconductor omponnts Industris, LL, 2009 Octobr, 2009 Rv. 2 1 ublication Ordr Numbr: 24164/D

2 24164 abl 1. BOLUE MXIMUM RING aramtrs Ratings Units torag mpratur 65 to +150 Voltag on ny in with Rspct to Ground (Not 1) 0.5 to +6.5 V trsss xcding Maximum Ratings may damag th dvic. Maximum Ratings ar strss ratings only. Functional opration abov th Rcommndd Oprating onditions is not implid. Extndd xposur to strsss abov th Rcommndd Oprating onditions may affct dvic rliability. 1. h D input voltag on any pin should not b lowr than 0.5 V or highr than V V. During transitions, th voltag on any pin may undrshoot to no lss than 1.5 V or ovrshoot to no mor than V V, for priods of lss than 20 ns. abl 2. RELIBILIY HRERII (Not 2) ymbol aramtr Min Units N END (Not 3) Enduranc 1,000,000 rogram/eras ycls DR Data Rtntion 100 Yars 2. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat E Q100 and JEDE tst mthods. 3. ag Mod, V = 5 V, 25. abl 3. D.. OERING HRERII (V = 1.8 V to 5.5 V, = 40 to +85, unlss othrwis spcifid.) ymbol aramtr st onditions Min Max Units I R Rad urrnt Rad, f L = 400 khz 1 m I W Writ urrnt Writ, f L = 400 khz 1 m I B tandby urrnt ll I/O ins at GND or V 1 I L I/O in Lakag in at GND or V 1 V IL Input Low Voltag 0.5 V x 0.3 V V IH Input High Voltag V x 0.7 V V V OL1 Output Low Voltag V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltag V < 2.5 V, I OL = 1.0 m 0.2 V abl 4. IN IMEDNE HRERII (V = 1.8 V to 5.5 V, = 40 to +85, unlss othrwis spcifid.) ymbol aramtr onditions Max Units IN (Not 4) D I/O in apacitanc V IN = 0 V 8 pf IN (Not 4) Input apacitanc (othr pins) V IN = 0 V 6 pf I W (Not 5) W Input urrnt V IN < V IH, V = 5.5 V 200 V IN < V IH, V = 3.3 V 150 V IN < V IH, V = 1.8 V 100 V IN > V IH 1 4. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat E Q100 and JEDE tst mthods. 5. Whn not drivn, th W pin is pulld down to GND intrnally. For improvd nois immunity, th intrnal pull down is rlativly strong; thrfor th xtrnal drivr must b abl to supply th pull down currnt whn attmpting to driv th input HIGH. o consrv powr, as th input lvl xcds th trip point of th MO input buffr (~ 0.5 x V ), th strong pull down rvrts to a wak currnt sourc. 2

3 24164 abl 5... HRERII (V = 1.8 V to 5.5 V, = 40 to +85.) (Not 6) ymbol aramtr tandard Fast Min Max Min Max F L lock Frquncy khz t HD: R ondition Hold im s t LOW Low riod of L lock s t HIGH High riod of L lock s t U: R ondition tup im s t HD:D Data In Hold im 0 0 s t U:D Data In tup im ns t R D and L Ris im ns t F (Not 7) D and L Fall im ns t U:O O ondition tup im s t BUF Bus Fr im Btwn O and R s t L Low to Data Out Valid s t DH Data Out Hold im ns i (Not 7) Nois uls Filtrd at L and D Inputs ns t U:W W tup im 0 0 s t HD:W W Hold im s t WR Writ ycl im 5 5 ms t U (Nots 7, 8) owr-up to Rady Mod 1 1 ms 6. st conditions according to.. st onditions tabl. 7. std initially and aftr a dsign or procss chang that affcts this paramtr. 8. t U is th dlay btwn th tim V is stabl and th dvic is rady to accpt commands. Units abl 6... E ONDIION Input Lvls Input Ris and Fall ims Input Rfrnc Lvls Output Rfrnc Lvls Output Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrnt ourc: I OL = 3 m (V 2.5 V); I OL = 1 m (V < 2.5 V); L = 100 pf 3

4 24164 owr-on Rst (OR) incorporats owr On Rst (OR) circuitry which protcts th intrnal logic against powring up in th wrong stat dvic will powr up into tandby mod aftr V xcds th OR triggr lvl and will powr down into Rst mod whn V drops blow th OR triggr lvl. his bi dirctional OR fatur protcts th dvic against brown out failur following a tmporary loss of powr. in Dscription L: h rial lock input pin accpts th rial lock gnratd by th Mastr. D: h rial Data I/O pin rcivs input data and transmits data stord in EEROM. In transmit mod, this pin is opn drain. Data is acquird on th positiv dg, and is dlivrd on th ngativ dg of L. 0, 1 and 2 : h ddrss inputs st th dvic addrss whn cascading multipl dvics. Whn not drivn, ths pins ar pulld LOW intrnally. h can b mad compatibl with th 2416 by tying 2, 1 and 0 to V or by laving 2, 1 and 0 float. W: h Writ rotct input pin inhibits all writ oprations, whn pulld HIGH. Whn not drivn, this pin is pulld LOW intrnally. Functional Dscription h supports th Intr Intgratd ircuit (I 2 ) Bus data transmission protocol, which dfins a dvic that snds data to th bus as a transmittr and a dvic rciving data as a rcivr. Data flow is controlld by a Mastr dvic, which gnrats th srial clock and all R and O conditions. h acts as a lav dvic. Mastr and lav altrnat as ithr transmittr or rcivr. I 2 Bus rotocol h I 2 bus consists of two wirs, L and D. h two wirs ar connctd to th V supply via pull up rsistors. Mastr and lav dvics connct to th 2 wir bus via thir rspctiv L and D pins. h transmitting dvic pulls down th D lin to transmit a 0 and rlass it to transmit a 1. Data transfr may b initiatd only whn th bus is not busy (s.. haractristics). During data transfr, th D lin must rmain stabl whil th L lin is HIGH. n D transition whil L is HIGH will b intrprtd as a R or O condition (Figur 2). h R condition prcds all commands. It consists of a HIGH to LOW transition on D whil L is HIGH. h R acts as a wak up call to all rcivrs. bsnt a R, a lav will not rspond to commands. h O condition complts all commands. It consists of a LOW to HIGH transition on D whil L is HIGH. Dvic ddrssing h bus Mastr bgins a transmission by snding a R condition. h Mastr thn snds th addrss of th particular lav dvic it is rqusting. h most significant bit of th 8 bit slav addrss is fixd as 1. (s Figur 3). h nxt thr significant bits ( 2, 1, 0 ) ar th dvic addrss bits and dfin which dvic or which part of th dvic th Mastr is accssing (h 1 bit must b th complimnt of th 1 input pin signal). Up to ight dvics may b individually addrssd by th systm. h nxt thr bits ar usd as th thr most significant bits of th data word addrss. h last bit of th slav addrss spcifis whthr a Rad or Writ opration is to b prformd. Whn this bit is st to 1, a Rad opration is slctd, and whn st to 0, a Writ opration is slctd. cknowldg ftr procssing th lav addrss, th lav rsponds with an acknowldg () by pulling down th D lin during th 9 th clock cycl (Figur 4). h lav will also acknowldg th addrss byt and vry data byt prsntd in Writ mod. In Rad mod th lav shifts out a data byt, and thn rlass th D lin during th 9 th clock cycl. s long as th Mastr acknowldgs th data, th lav will continu transmitting. h Mastr trminats th sssion by not acknowldging th last data byt (No) and by issuing a O condition. Bus timing is illustratd in Figur 5. 4

5 24164 L D R ONDIION Figur 2. R/O onditions O ONDIION a 10 a 9 a 8 R/W Figur 3. lav ddrss Bits BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUU FROM RNMIER D OUU FROM REEIVER R DELY ( t ) Figur 4. cknowldg iming EU ( t U:D ) t F t HIGH t R t LOW t LOW L t U: t HD: t HD:D t U:D t U:O D IN t t DH t BUF D OU Figur 5. Bus iming 5

6 24164 WRIE OERION Byt Writ In Byt Writ mod, th Mastr snds th R condition and th lav addrss with th R/W bit st to zro to th lav. ftr th lav gnrats an acknowldg, th Mastr snds th byt addrss that is to b writtn into th addrss pointr of th ftr rciving anothr acknowldg from th lav, th Mastr transmits th data byt to b writtn into th addrssd mmory location. h dvic will acknowldg th data byt and th Mastr gnrats th O condition, at which tim th dvic bgins its intrnal Writ cycl to nonvolatil mmory (Figur 6). Whil this intrnal cycl is in progrss (t WR ), th D output will b tri statd and th will not rspond to any rqust from th Mastr dvic (Figur 7). ag Writ h writs up to 16 byts of data in a singl writ cycl, using th ag Writ opration (Figur 8). h ag Writ opration is initiatd in th sam mannr as th Byt Writ opration, howvr instad of trminating aftr th data byt is transmittd, th Mastr is allowd to snd up to fiftn additional byts. ftr ach byt has bn transmittd th will rspond with an acknowldg and intrnally incrmnts th four low ordr addrss bits. h high ordr bits that dfin th pag addrss rmain unchangd. If th Mastr transmits mor than sixtn byts prior to snding th O condition, th addrss countr wraps around to th bginning of pag and prviously transmittd data will b ovrwrittn. Onc all sixtn byts ar rcivd and th O condition has bn snt by th Mastr, th intrnal Writ cycl bgins. t this point all rcivd data is writtn to th in a singl writ cycl. cknowldg olling h acknowldg () polling routin can b usd to tak advantag of th typical writ cycl tim. Onc th stop condition is issud to indicat th nd of th host s writ opration, th initiats th intrnal writ cycl. h polling can b initiatd immdiatly. his involvs issuing th start condition followd by th slav addrss for a writ opration. If th is still busy with th writ opration, No will b rturnd. If th has compltd th intrnal writ opration, an will b rturnd and th host can thn procd with th nxt rad or writ opration. Hardwar Writ rotction With th W pin hld HIGH, th ntir mmory is protctd against Writ oprations. If th W pin is lft floating or is groundd, it has no impact on th opration of th h stat of th W pin is strobd on th last falling dg of L immdiatly prcding th first data byt (Figur 9). If th W pin is HIGH during th strob intrval, th will not acknowldg th data byt and th Writ rqust will b rjctd. Dlivry tat h is shippd rasd, i.., all byts ar FFh. 6

7 24164 BU IVIY: MER R LVE DDRE DDRE D a 7 a 0 d 7 d 0 O LVE Figur 6. Byt Writ qunc L D 8th Bit Byt n t WR O ONDIION R ONDIION DDRE Figur 7. Writ ycl iming BU IVIY: MER R LVE DDRE DDRE D n D n+1 D n+ O LVE n = 1 15 Figur 8. ag Writ qunc DDRE D L D a 7 a 0 d 7 d 0 t U:W W t HD:W Figur 9. W iming 7

8 24164 RED OERION Immdiat Rad Upon rciving a lav addrss with th R/W bit st to 1, th will intrprt this as a rqust for data rsiding at th currnt byt addrss in mmory. h will acknowldg th lav addrss, will immdiatly shift out th data rsiding at th currnt addrss, and will thn wait for th Mastr to rspond. If th Mastr dos not acknowldg th data (No) and thn follows up with a O condition (Figur 10), th rturns to tandby mod. lctiv Rad lctiv Rad oprations allow th Mastr dvic to slct at random any mmory location for a rad opration. h Mastr dvic first prforms a dummy writ opration by snding th R condition, slav addrss and byt addrss of th location it wishs to rad. ftr th acknowldgs th byt addrss, th Mastr dvic rsnds th R condition and th slav addrss, this tim with th R/W bit st to on. h thn rsponds with its acknowldg and snds th rqustd data byt. h Mastr dvic dos not acknowldg th data (No) but will gnrat a O condition (Figur 11). quntial Rad If during a Rad sssion, th Mastr acknowldgs th 1 st data byt, thn th will continu transmitting data rsiding at subsqunt locations until th Mastr rsponds with a No, followd by a O (Figur 12). In contrast to ag Writ, during quntial Rad th addrss count will automatically incrmnt to and thn wrap around at nd of mmory (rathr than nd of pag). BU IVIY: N O MER R LVE DDRE O LVE D L 8 9 D 8th Bit D OU NO Figur 10. Immdiat Rad qunc and iming O BU IVIY: MER R LVE DDRE DDRE R LVE DDRE N O O LVE D Figur 11. lctiv Rad qunc BU IVIY: MER LVE DDRE N O O LVE D n D n+1 D n+2 D n+x Figur 12. quntial Rad qunc 8

9 24164 GE DIMENION DI 8, 300 mils E IUE YMBOL MIN NOM MX IN # 1 IDENIFIION D E b b2 c D E E1 B B L O VIEW E 2 1 L b2 c b B IDE VIEW END VIEW Nots: (1) ll dimnsions ar in millimtrs. (2) omplis with JEDE M

10 24164 GE DIMENION OI 8, 150 mils E 751BD 01 IUE O YMBOL MIN NOM MX b E1 E c D E E B h IN # 1 IDENIFIION L θ 0º 8º O VIEW D h 1 θ c b L IDE VIEW END VIEW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with JEDE M

11 24164 GE DIMENION b O8, 4.4x3 E 948L 01 IUE O YMBOL MIN NOM MX b E1 E c D E E B L 1.00 REF L1 θ º 8º O VIEW D 2 1 c IDE VIEW 1 L1 END VIEW L Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with JEDE MO

12 24164 GE DIMENION DFN8, 2x3 E IUE D b E E2 IN#1 IDENIFIION IN#1 INDEX RE 1 D2 L O VIEW IDE VIEW BOOM VIEW YMBOL MIN NOM MX REF b D D FRON VIEW E E Y L Nots: (1) ll dimnsions ar in millimtrs. (2) omplis with JEDE MO

13 24164 ackag Marking 8 Lad DI 8 Lad OI 24164LI FYYWW G 24164WI FYYWWG I YY WW G F = mpratur Rang = roduction Yar = roduction Wk = roduct Rvision = Lad Finish = 4 = Nidu I YY WW G F = mpratur Rang = roduction Yar = roduction Wk = roduct Rvision = Lad Finish = 4 = Nidu 8 Lad O 8 ad DFN YMGF X X N 24164I N N N Y M G I F = roduction Yar = roduction Month = Di Rvision = mpratur Rang = Lad Finish = 4 = Nidu XX N Y M YM = Dvic od = FR = Nidu = racabl od = roduction Yar = roduction Month 9. h circl on th packag marking indicats th location of in For DFN packag, th roduct Rvision marking is includd in th Dvic od (XX). 13

14 24164 Exampl of Ordring Information rfix Dvic # uffix Y I G 3 ompany ID roduct Numbr mpratur Rang I = Industrial ( 40 to +85 ) E = Extndd ( 40 to +125 ) Lad Finish G: Nidu ap & Rl (Not 16) : ap & Rl 3: 3,000 / Rl ackag L: DI W: OI, JEDE Y: O V2: DFN ORDERING INFORMION Ordrabl art Numbrs 24164LI G 24164LE G 24164WI G WE G YI G YE G V2IG3 (Not 15) 24164V2EG3 (Not 15) 11. ll packags ar RoH-compliant (Lad-fr, Halogn-fr). 12. h standard lad finish is Nidu. 13. h dvic usd in th abov xampl is a 24164YI G3 (O, Industrial mpratur, Nidu, ap & Rl, 3,000/Rl). 14. For additional packag and tmpratur options, plas contact your narst ON miconductor als offic. 15.art numbr is not xactly th sam as th Exampl of Ordring Information shown abov. For th part numbrs indicatd thr ar NO hyphns in th ordrabl part numbrs. 16. For information on tap and rl spcifications, including part orintation and tap sizs, plas rfr to our ap and Rl ackaging pcifications Brochur, BRD8011/D. ON miconductor is licnsd by hilips orporation to carry th I 2 Bus rotocol. ON miconductor and ar rgistrd tradmarks of miconductor omponnts Industris, LL (ILL). ILL rsrvs th right to mak changs without furthr notic to any products hrin. ILL maks no warranty, rprsntation or guarant rgarding th suitability of its products for any particular purpos, nor dos ILL assum any liability arising out of th application or us of any product or circuit, and spcifically disclaims any and all liability, including without limitation spcial, consquntial or incidntal damags. ypical paramtrs which may b providd in ILL data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including ypicals must b validatd for ach customr application by customr s tchnical xprts. ILL dos not convy any licns undr its patnt rights nor th rights of othrs. ILL products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th body, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th ILL product could crat a situation whr prsonal injury or dath may occur. hould Buyr purchas or us ILL products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold ILL and its officrs, mploys, subsidiaris, affiliats, and distributors harmlss against all claims, costs, damags, and xpnss, and rasonabl attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that ILL was nglignt rgarding th dsign or manufactur of th part. ILL is an Equal Opportunity/ffirmativ ction Employr. his litratur is subjct to all applicabl copyright laws and is not for rsal in any mannr. UBLIION ORDERING INFORMION LIERURE FULFILLMEN: Litratur Distribution ntr for ON miconductor.o. Box 5163, Dnvr, olorado U hon: or oll Fr U/anada Fax: or oll Fr U/anada ordrlit@onsmi.com N. mrican chnical upport: oll Fr U/anada Europ, Middl East and frica chnical upport: hon: Japan ustomr Focus ntr hon: ON miconductor Wbsit: Ordr Litratur: For additional information, plas contact your local als Rprsntativ 24164/D