CAT24C01/02/04/08/16. 1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM DEVICE DESCRIPTION FEATURES PIN FUNCTIONS

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Alicia Brooks
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1 2401/02/04/08/16 1-, 2-, 4-, 8- and 16- MO rial PROM FUR upports tandard and Fast I 2 Protocol 1.8 V to 5.5 V upply Voltag Rang 16-Byt Pag Writ Buffr Hardwar Writ Protction for ntir mmory chmitt riggrs and Nois upprssion Filtrs on I 2 Bus Inputs ( and ). ow powr MO tchnology 1,000,000 program/ras cycls 100 yar data rtntion Industrial tmpratur rang RoH-compliant 8-lad PIP, OI, and OP, 8-pad FN and 5-lad O-23 packags. For Ordring Information dtails, s pag 17. VI RIPION h 2401/02/04/08/16 ar 1-, 2-, 4-, 8- and 16- rspctivly MO rial PROM dvics organizd intrnally as 8/16/32/64 and 128 pags rspctivly of 16 yts ach. ll dvics support oth th tandard (100 khz) as wll as Fast (400 khz) I 2 protocol. ata is writtn y providing a starting addrss, thn loading 1 to 16 contiguous yts into a Pag Writ Buffr, and thn writing all data to non-volatil mmory in on intrnal writ cycl. ata is rad y providing a starting addrss and thn shifting out data srially whil automatically incrmnting th intrnal addrss count. xtrnal addrss pins mak it possil to addrss up to ight 2401 or 2402, four 2404, two 2408 and on 2416 dvic on th sam us. PIN ONFIGURION FUNION YMBO PIP () OI (W) OP (Y) FN (VP2) O-23 () V 2416 / 08 / 04 / 02 / 01 N / N / N / 0 / 0 N / N / 1 / 1 / 1 N / 2 / 2 / 2 / 2 V V WP V WP V 2, 1, 0 24xx For th location of Pin 1, plas consult th corrsponding packag drawing. WP PIN FUNION 0, 1, 2 WP V V N vic ddrss Inputs rial ata Input/Output rial lock Input Writ Protct Input Powr upply Ground No onnct V * atalyst carris th I 2 protocol undr a licns from th Philips orporation y atalyst miconductor, Inc. haractristics sujct to chang without notic 1 oc. No. 1115, Rv. B

2 2401/02/04/08/16 BOU MXIMUM RING (1) torag mpratur Voltag on ny Pin with Rspct to Ground (2) -65 to V to +6.5 V RIBIIY HRRII (3) ymol Paramtr Min Units N (4) N nduranc 1,000,000 Program/ ras ycls R ata Rtntion 100 Yars.. OPRING HRRII V = 1.8 V to 5.5 V, = -40 to 85, unlss othrwis spcifid. ymol Paramtr st onditions Min Max Units I R Rad urrnt Rad, f = 400 khz 1 m I W Writ urrnt Writ, f = 400 khz 1 m I B tandy urrnt ll I/O Pins at GN or V 1 μ I I/O Pin akag Pin at GN or V 1 μ V I Input ow Voltag -0.5 V x 0.3 V V IH Input High Voltag V x 0.7 V V V O1 Output ow Voltag V 2.5 V, I O = 3.0 m 0.4 V V O2 Output ow Voltag V < 2.5 V, I O = 1.0 m 0.2 V PIN IMPN HRRII V = 1.8 V to 5.5 V, = -40 to 85, unlss othrwis spcifid. ymol Paramtr onditions Max Units (3) IN I/O Pin apacitanc V IN = 0 V 8 pf (3) IN Input apacitanc (othr pins) V IN = 0 V 6 pf I (5) WP WP Input urrnt V IN < V IH, V = 5.5 V 200 V IN < V IH, V = 3.3 V 150 V IN < V IH, V = 1.8 V 100 V IN > V IH 1 μ Not: (1) trsss aov thos listd undr solut Maximum Ratings may caus prmannt damag to th dvic. hs ar strss ratings only, and functional opration of th dvic at ths or any othr conditions outsid of thos listd in th oprational sctions of this spcification is not implid. xposur to any asolut maximum rating for xtndd priods may affct dvic prformanc and rliaility. (2) h input voltag on any pin should not lowr than -0.5 V or highr than V V. uring transitions, th voltag on any pin may undrshoot to no lss than -1.5 V or ovrshoot to no mor than V V, for priods of lss than 20 ns. (3) hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat -Q100 and J tst mthods. (4) Pag Mod, V = 5 V, 25 (5) Whn not drivn, th WP pin is pulld down to GN intrnally. For improvd nois immunity, th intrnal pull-down is rlativly strong; thrfor th xtrnal drivr must al to supply th pull-down currnt whn attmpting to driv th input HIGH. o consrv powr, as th input lvl xcds th trip point of th MO input uffr (~ 0.5 x V ), th strong pull-down rvrts to a wak currnt sourc. oc. No. 1115, Rv. B y atalyst miconductor, Inc. haractristics sujct to chang without notic

3 2401/02/04/08/16.. HRRII (1) V = 1.8 V to 5.5 V, = -40 to 85. tandard Fast ymol Paramtr Min Max Min Max Units F lock Frquncy khz t H: R ondition Hold im μs t OW ow Priod of lock μs t HIGH High Priod of lock μs t U: R ondition tup im μs t H: ata In Hold im 0 0 μs t U: ata In tup im ns t R and Ris im ns t (2) F and Fall im ns t U:O OP ondition tup im μs t BUF Bus Fr im Btwn OP and R μs t ow to ata Out Valid μs t H ata Out Hold im ns (2) i Nois Puls Filtrd at and Inputs ns t U:WP WP tup im 0 0 μs t H:WP WP Hold im μs t WR Writ ycl im 5 5 ms t (2, 3) PU Powr-up to Rady Mod 1 1 ms Not: (1) st conditions according to.. st onditions tal. (2) std initially and aftr a dsign or procss chang that affcts this paramtr. (3) t PU is th dlay twn th tim V is stal and th dvic is rady to accpt commands... ONIION Input vls Input Ris and Fall ims Input Rfrnc vls Output Rfrnc vls Output oad 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrnt ourc: I O = 3 m (V 2.5 V); I O = 1 m (V < 2.5 V); = 100 pf 2006 y atalyst miconductor, Inc. haractristics sujct to chang without notic 3 oc No. 1115, Rv. B

4 2401/02/04/08/16 POWR-ON R (POR) ach 24xx* incorporats Powr-On Rst (POR) circuitry which protcts th intrnal logic against powring up in th wrong stat. 24xx dvic will powr up into tandy mod aftr V xcds th POR triggr lvl and will powr down into Rst mod whn V drops low th POR triggr lvl. his i-dirctional POR fatur protcts th dvic against rown-out failur following a tmporary loss of powr. * For common faturs, th 2401/02/04/08/16 will rfrd to as 24xx PIN RIPION : h rial lock input pin accpts th rial lock gnratd y th Mastr. : h rial ata I/O pin rcivs input data and transmits data stord in PROM. In transmit mod, this pin is opn drain. ata is acquird on th positiv dg, and is dlivrd on th ngativ dg of. 0, 1 and 2: h ddrss inputs st th dvic addrss whn cascading multipl dvics. Whn not drivn, ths pins ar pulld OW intrnally. WP: h Writ Protct input pin inhiits all writ oprations, whn pulld HIGH. Whn not drivn, this pin is pulld OW intrnally. FUNION RIPION h 24xx supports th Intr-Intgratd ircuit (I 2 ) Bus data transmission protocol, which dfins a dvic that snds data to th us as a transmittr and a dvic rciving data as a rcivr. ata flow is controlld y a Mastr dvic, which gnrats th srial clock and all R and OP conditions. h 24xx acts as a lav dvic. Mastr and lav altrnat as ithr transmittr or rcivr. I 2 BU PROOO h I 2 us consists of two wirs, and. h two wirs ar connctd to th V supply via pull-up rsistors. Mastr and lav dvics connct to th 2- wir us via thir rspctiv and pins. h transmitting dvic pulls down th lin to transmit a 0 and rlass it to transmit a 1. ata transfr may initiatd only whn th us is not usy (s.. haractristics). uring data transfr, th lin must rmain stal whil th lin is HIGH. n transition whil is HIGH will intrprtd as a R or OP condition (Figur 1). h R condition prcds all commands. It consists of a HIGH to OW transition on whil is HIGH. h R acts as a wak-up call to all rcivrs. snt a R, a lav will not rspond to commands. h OP condition complts all commands. It consists of a OW to HIGH transition on whil is HIGH. vic ddrssing h Mastr initiats data transfr y crating a R condition on th us. h Mastr thn roadcasts an 8-it srial lav addrss. For normal Rad/Writ oprations, th first 4 its of th lav addrss ar fixd at 1010 (h). h nxt 3 its ar usd as programmal addrss its whn cascading multipl dvics and/or as intrnal addrss its. h last it of th slav addrss, R/W, spcifis whthr a Rad (1) or Writ (0) opration is to prformd. h 3 addrss spac xtnsion its ar assignd as illustratd in Figur 2. 2, 1 and 0 must match th stat of th xtrnal addrss pins, and a 10, a 9 and a 8 ar intrnal addrss its. cknowldg ftr procssing th lav addrss, th lav rsponds with an acknowldg () y pulling down th lin during th 9 th clock cycl (Figur 3). h lav will also acknowldg th addrss yt and vry data yt prsntd in Writ mod. In Rad mod th lav shifts out a data yt, and thn rlass th lin during th 9 th clock cycl. s long as th Mastr acknowldgs th data, th lav will continu transmitting. h Mastr trminats th sssion y not acknowldging th last data yt (No) and y issuing a OP condition. Bus timing is illustratd in Figur 4. oc. No. 1115, Rv. B y atalyst miconductor, Inc. haractristics sujct to chang without notic

5 2401/02/04/08/16 Figur 1. R/OP onditions R ONIION OP ONIION Figur 2. lav ddrss Bits R/W 2401 and a 8 R/W a 9 a 8 R/W a10 a9 a8 R/W 2416 Figur 3. cknowldg iming BU R Y (RNMIR) BU R Y (RIVR) FROM MR OUPU FROM RNMIR OUPU FROM RIVR R Y ( t) UP ( t U: ) Figur 4. Bus iming t F t HIGH t R t OW t OW t U: t H: t H: t U: t U:O IN t t H t BUF OU 2006 y atalyst miconductor, Inc. haractristics sujct to chang without notic 5 oc No. 1115, Rv. B

6 2401/02/04/08/16 WRI OPRION Byt Writ In Byt Writ mod, th Mastr snds th R condition and th lav addrss with th R/W it st to zro to th lav. ftr th lav gnrats an acknowldg, th Mastr snds th yt addrss that is to writtn into th addrss pointr of th 24xx. ftr rciving anothr acknowldg from th lav, th Mastr transmits th data yt to writtn into th addrssd mmory location. h 24xx dvic will acknowldg th data yt and th Mastr gnrats th OP condition, at which tim th dvic gins its intrnal Writ cycl to nonvolatil mmory (Figur 5). Whil this intrnal cycl is in progrss (t WR ), th output will tri-statd and th 24xx will not rspond to any rqust from th Mastr dvic (Figur 6). Hardwar Writ Protction With th WP pin hld HIGH, th ntir mmory is protctd against Writ oprations. If th WP pin is lft floating or is groundd, it has no impact on th opration of th 24xx. h stat of th WP pin is strod on th last falling dg of immdiatly prcding th first data yt (Figur 8). If th WP pin is HIGH during th stro intrval, th 24xx will not acknowldg th data yt and th Writ rqust will rjctd. livry tat h 24xx is shippd rasd, i.., all yts ar FFh. Pag Writ h 24xx writs up to 16 yts of data in a singl writ cycl, using th Pag Writ opration (Figur 7). h Pag Writ opration is initiatd in th sam mannr as th Byt Writ opration, howvr instad of trminating aftr th data yt is transmittd, th Mastr is allowd to snd up to fiftn additional yts. ftr ach yt has n transmittd th 24xx will rspond with an acknowldg and intrnally incrmnts th four low ordr addrss its. h high ordr its that dfin th pag addrss rmain unchangd. If th Mastr transmits mor than sixtn yts prior to snding th OP condition, th addrss countr wraps around to th ginning of pag and prviously transmittd data will ovrwrittn. Onc all sixtn yts ar rcivd and th OP condition has n snt y th Mastr, th intrnal Writ cycl gins. t this point all rcivd data is writtn to th 24xx in a singl writ cycl. cknowldg Polling h acknowldg () polling routin can usd to tak advantag of th typical writ cycl tim. Onc th stop condition is issud to indicat th nd of th host s writ opration, th 24xx initiats th intrnal writ cycl. h polling can initiatd immdiatly. his involvs issuing th start condition followd y th slav addrss for a writ opration. If th 24xx is still usy with th writ opration, No will rturnd. If th 24xx has compltd th intrnal writ opration, an will rturnd and th host can thn procd with th nxt rad or writ opration. oc. No. 1115, Rv. B y atalyst miconductor, Inc. haractristics sujct to chang without notic

7 2401/02/04/08/16 Figur 5. Byt Writ qunc BU IVIY: MR R V R R a7 a0 d7 d0 O P P V * For th 2401 a7 = 0 Figur 6. Writ ycl iming 8 th Bit Byt n t WR OP ONIION R ONIION R Figur 7. Pag Writ qunc BU IVIY: MR R V R R n n+1 n+p O P P V n = 1 P 15 Figur 8. WP iming R a7 a0 d7 d0 tu:wp WP th:wp 2006 y atalyst miconductor, Inc. haractristics sujct to chang without notic 7 oc No. 1115, Rv. B

8 2401/02/04/08/16 R OPRION Immdiat Rad Upon rciving a lav addrss with th R/W it st to 1, th 24xx will intrprt this as a rqust for data rsiding at th currnt yt addrss in mmory. h 24xx will acknowldg th lav addrss, will immdiatly shift out th data rsiding at th currnt addrss, and will thn wait for th Mastr to rspond. If th Mastr dos not acknowldg th data (No) and thn follows up with a OP condition (Figur 9), th 24xx rturns to tandy mod. lctiv Rad lctiv Rad oprations allow th Mastr dvic to slct at random any mmory location for a rad opration. h Mastr dvic first prforms a dummy writ opration y snding th R condition, slav addrss and yt addrss of th location it wishs to rad. ftr th 24xx acknowldgs th yt addrss, th Mastr dvic rsnds th R condition and th slav addrss, this tim with th R/W it st to on. h 24xx thn rsponds with its acknowldg and snds th rqustd data yt. h Mastr dvic dos not acknowldg th data (No) ut will gnrat a OP condition (Figur 10). quntial Rad If during a Rad sssion, th Mastr acknowldgs th 1 st data yt, thn th 24xx will continu transmitting data rsiding at susqunt locations until th Mastr rsponds with a No, followd y a OP (Figur 11). In contrast to Pag Writ, during quntial Rad th addrss count will automatically incrmnt to and thn wrap-around at nd of mmory (rathr than nd of pag). In th 2401, th intrnal addrss count will not wrap around at th nd of th 128 yt mmory spac. oc. No. 1115, Rv. B y atalyst miconductor, Inc. haractristics sujct to chang without notic

9 2401/02/04/08/16 Figur 9. Immdiat Rad qunc and iming BU IVIY: MR R V R N O O P P V 8 9 8th Bit OU NO OP Figur 10. lctiv Rad qunc BU IVIY: MR R V R R R V R N O O P P V Figur 11. quntial Rad qunc BU IVIY: MR V R N O O P P V n n+1 n+2 n+x 2006 y atalyst miconductor, Inc. haractristics sujct to chang without notic 9 oc No. 1115, Rv. B

10 2401/02/04/08/ MI WI PI IP () B 2 YMBO B MIN NOM MX B _8-_IP_(300P).ps Nots: 1. ll dimnsions ar in millimtrs. 2. omplis with J tandard M imnsioning and tolrancing pr NI Y14.5M-1982 oc. No. 1115, Rv. B y atalyst miconductor, Inc. haractristics sujct to chang without notic

11 2401/02/04/08/ MI WI OI (W) 1 h x 45 θ1 1 YMBO 1 1 h MIN NOM 1.27 B MX θ _8-_OI.ps For currnt ap and Rl information, download th PF fil from: Nots: 1. ll dimnsions ar in millimtrs. 2. omplis with J spcification M-012 dimnsions y atalyst miconductor, Inc. haractristics sujct to chang without notic 11 oc No. 1115, Rv. B

12 2401/02/04/08/16 8- OP (Y) 8 5 I c 1 /2 1 4 GG PN PIN #1 IN. 2 θ1 I ING PN YMBO 1 2 c 1 θ1 MIN NOM B 0.50 MX For currnt ap and Rl information, download th PF fil from: Nots: 1. ll dimnsions ar in millimtrs. 2. omplis with J spcification MO-153. oc. No. 1115, Rv. B y atalyst miconductor, Inc. haractristics sujct to chang without notic

13 2401/02/04/08/16 8-P FN 2X3 PG (VP2) PIN 1 INX R YMBO MIN NOM MX RF YP PIN 1 I 3 x For currnt ap and Rl information, download th PF fil from: FN2X3 (03).ps Nots: 1. ll dimnsions ar in millimtrs. 2. omplis with J spcification MO y atalyst miconductor, Inc. haractristics sujct to chang without notic 13 oc No. 1115, Rv. B

14 2401/02/04/08/16 5-ad O-23 () c GUG PN θ YMBO 1 2 c θ MIN NOM B 2.80 B 1.60 B 0.95 B 1.90 B RF 0.25 B MX For currnt ap and Rl information, download th PF fil from: Nots: 1. ll dimnsions ar in millimtrs. 2. omplis with J spcification MO-193. oc. No. 1115, Rv. B y atalyst miconductor, Inc. haractristics sujct to chang without notic

15 2401/02/04/08/16 PG MRING 8-ad PIP 8-ad OI 24XXI FYYWWR 24XXWI FYYWWR I = atalyst miconductor, Inc. XX = vic od (s Marking od tal low) I = mpratur Rang YY = Production Yar WW = Production Wk R = Product Rvision (s Marking od tal low) F = ad Finish 4 = NiPdu 3 = Matt-in I = atalyst miconductor, Inc. XX = vic od (s Marking od tal low) I = mpratur Rang YY = Production Yar WW = Production Wk R = Product Rvision (s Marking od tal low) F = ad Finish 4 = NiPdu 3 = Matt-in 8-ad OP YMRF 24XXI Y = Production Yar M = Production Month R = i Rvision (s Marking od tal low) XX = vic od (s Marking od tal low) I = mpratur Rang WW = Production Wk F = ad Finish 4 = NiPdu 3 = Matt-in vic od XX Marking ods Product Rvision R G G J H G Not: (1) h circl on th packag marking indicats th location of Pin y atalyst miconductor, Inc. haractristics sujct to chang without notic 15 oc No. 1115, Rv. B

16 2401/02/04/08/16 PG MRING 8-Pad FN 5-ad O X X N N N N XXYM Y M XX = N = Y = M = vic od Matt-in NiPdu 2401 Rv. G P 2402 Rv. G R B 2404 Rv. J 2408 Rv. H 2416 Rv. G U Z racal od Production Yar Production Month XX = Y = M = vic od Matt-in NiPdu 2401 Rv. G R MM 2402 Rv. G RB MN 2404 Rv. J R MP 2408 Rv. H R MR 2416 Rv. G R M Production Yar Production Month Nots: (1) h circl on th packag marking indicats th location of Pin 1. (2) For FN and OP packags, th Product Rvision marking is includd in th vic od (XX). oc. No. 1115, Rv. B y atalyst miconductor, Inc. haractristics sujct to chang without notic

17 2401/02/04/08/16 XMP OF ORRING INFORMION Prfix vic # uffix 2416 Y I G 3 ompany I Product Numr Packag : PIP W: OI, J Y: OP VP2: FN : O mpratur Rang I = Industrial (-40 to +85 ) ad Finish G: NiPdu Blank: Matt-in : ap & Rl 3: 3000/Rl Nots: (1) ll packags ar RoH-compliant (ad-fr, Halogn-fr). (2) h standard lad finish is NiPdu pr-platd (PPF) lad frams. (3) h dvic usd in th aov xampl is a 2416YI-G3 (OP, Industrial mpratur, NiPdu, ap & Rl). (4) For additional packag and tmpratur options, plas contact your narst atalyst miconductor als offic y atalyst miconductor, Inc. haractristics sujct to chang without notic 17 oc No. 1115, Rv. B

18 RVIION HIORY at Rvision ommnts 07/18/06 omin 5 data shts into on data sht. 07/31/06 B Updat Packag Marking opyrights, radmarks and Patnts radmarks and rgistrd tradmarks of atalyst miconductor includ ach of th following: PP 2 MiniPot atalyst miconductor has n issud U.. and forign patnts and has patnt applications pnding that protct its products. Y MIONUOR M NO WRRNY, RPRNION OR GURN, XPR OR IMPI, RGRING H UIBIIY OF I PROU FOR NY PRIUR PURPO, NOR H H U OF I PROU WI NO INFRING I INU PROPRY RIGH OR H RIGH OF HIR PRI WIH RP O NY PRIUR U OR PPIION N PIFIY IIM NY N IBIIY RIING OU OF NY UH U OR PPIION, INUING BU NO IMI O, ONQUNI OR ININ MG. atalyst miconductor products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th ody, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th atalyst miconductor product could crat a situation whr prsonal injury or dath may occur. atalyst miconductor rsrvs th right to mak changs to or discontinu any product or srvic dscrid hrin without notic. Products with data shts lald dvanc Information or Prliminary and othr products dscrid hrin may not in production or offrd for sal. atalyst miconductor adviss customrs to otain th currnt vrsion of th rlvant product information for placing ordrs. ircuit diagrams illustrat typical smiconductor applications and may not complt. atalyst miconductor, Inc. orporat Hadquartrs 2975 tndr Way anta lara, Phon: Fax: Pulication #: 1115 Rvison: B Issu dat: 07/31/06

CAT24C Kb I 2 C CMOS Serial EEPROM

CAT24C Kb I 2 C CMOS Serial EEPROM 2432 32- I 2 MO rial ROM scription h 2432 is a 32 MO rial ROM dvics, intrnally organizd as 128 pags of 32 yts ach. It faturs a 32 yt pag writ uffr and supports oth th tandard (100 khz) as wll as Fast (400