CENG3420 Lab 3-1: LC-3b Datapath
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1 CENG3420 Lab 3-1: LC-3b Datapath Bei Yu Department of Computer Science and Engineering The Chinese University of Hong Kong Spring / 22
2 Overview Introduction Lab3-1 Assignment Golden Results 2 / 22
3 Overview Introduction Lab3-1 Assignment Golden Results 3 / 22
4 The Slides are self-contained? NO! Do please refer to following document: LC-3b-datapath.pdf LC-3b-ISA.pdf 3 / 22
5 LC-3b Microarchitecture 4 / 22
6 Input of Control Structure (7 bits) R: indicate whether memory data is ready (System_Latches::READY) BEN: indicate whether BR been taken (System_Latches::BEN) IR[15:11]: current instruction (System_Latches::IR) 5 / 22
![Output of Control Structure: (35 bits) 26 bits to control data path J[5:0],](/docs-images/95/122605889/images/7-0.jpg "COND[1:0],IRD: generate address of control structure for next clock cycle 6 /")
7 Output of Control Structure: (35 bits) 26 bits to control data path J[5:0], COND[1:0],IRD: generate address of control structure for next clock cycle 6 / 22
8 LC-3b Control Structure 7 / 22
9 LC-3b Control Structure 7 / 22
10 How s Microsequencer Actually Working? MAR < PC PC < PC , 19 MDR < M 33 R R IR < MDR 35 To 8 RTI ADD BEN< IR[11] & N + IR[10] & Z + IR[9] & P [IR[15:12]] BR To 11 To 10 To 18 1 DR< SR1+OP2* set CC 5 DR< SR1&OP2* set CC AND XOR TRAP SHF LEA LDB LDW STW STB JSR JMP 0 [BEN] PC< PC+LSHF(off9,1) 9 To 18 DR< SR1 XOR OP2* set CC 12 PC< BaseR To 18 To 18 MAR< LSHF(ZEXT[IR[7:0]],1) 15 4 [IR[11]] To 18 To 18 To 18 R MDR< M[MAR] R7< PC R PC< MDR DR< SHF(SR,A,D,amt4) set CC DR< PC+LSHF(off9,1) set CC 14 2 MAR< B+off R7< PC PC< BaseR 21 R7< PC To 18 PC< PC+LSHF(off11,1) To MAR< B+LSHF(off6,1) MAR< B+LSHF(off6,1) MAR< B+off6 To NOTES B+off6 : Base + SEXT[offset6] PC+off9 : PC + SEXT[offset9] *OP2 may be SR2 or SEXT[imm5] ** [15:8] or [7:0] depending on MAR[0] MDR< M[MAR[15:1] 0] MDR< M[MAR] R R R R DR< SEXT[BYTE.DATA] DR< MDR set CC set CC MDR< SR 16 M[MAR]< MDR R R MDR< SR[7:0] 17 M[MAR]< MDR** R R To 18 To 18 To 18 To 19 8 / 22
11 How s Control Store Actually Implemented? Finite-State-Machine (FSM) States 10, 11 are empty 6 bits input enough Per state, output 35 bits 9 / 22
12 How s Control Store Actually Implemented? Finite-State-Machine (FSM) States 10, 11 are empty 6 bits input enough Per state, output 35 bits Hard to implement 9 / 22
13 Good News! Part of FSM has been provided See file ucode3 10 / 22
14 Overview Introduction Lab3-1 Assignment Golden Results 11 / 22
15 Operations in One Clock Cycle In lc3bsim3-1.c : void cycle() { eval_micro_sequencer(); cycle_memory(); eval_bus_drivers(); drive_bus(); latch_datapath_values(); CURRENT_LATCHES = NEXT_LATCHES; } CYCLE_COUNT++; 11 / 22
16 Lab3-1 Assignment Input: CURRENT_LATCHES Output: NEXT_LATCHES.MICROINSTRUCTION 12 / 22
17 Lab3-1 Assignment Tips 13 / 22
18 Lab3-1 Assignment Tips (cont.) Some functions may help: GetCOND() GetIRD() GetJ() partval() 14 / 22
19 Overview Introduction Lab3-1 Assignment Golden Results 15 / 22
20 Assignment Package lc3bsim3-1.c, lc3bsim3-1.h: codes to work on libems3-1.a: library ucode3: FSM Makefile bench: folder with benchmarks Run the simulator: 1. make, then binary lc3bsim3-1 is generated 2../lc3bsim3-1 ucode3 bench/toupper.cod 15 / 22
21 Golden Results case toupper.cod 1. run 6 Simulating for 6 cycles... MemCycleCnt = 0 MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0 MemCycleCnt = 0 MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0 MemCycleCnt = 1 MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0 MemCycleCnt = 2 MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0 MemCycleCnt = 3 MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0 MemCycleCnt = 4 MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0 16 / 22
22 Golden Results case toupper.cod (cont.) 2. rdump Current register/bus values : Cycle Count : 6 PC : 0x3002 IR : 0x0000 STATE_NUMBER : 0x0023 BUS : 0x0000 MDR : 0xe00f MAR : 0x3000 CCs: N = 0 Z = 1 P = 0 Registers: 0: 0x0000 1: 0x0000 2: 0x0000 3: 0x0000 4: 0x0000 5: 0x0000 6: 0x0000 7: 0x / 22
23 Golden Results case toupper.cod (cont.) 3. Go on run 1 Simulating for 1 cycles... MemCycleCnt = 1 MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0 18 / 22
24 Golden Results case toupper.cod (cont.) 4. rdump Current register/bus values : Cycle Count : 7 PC : 0x3002 IR : 0xe00f STATE_NUMBER : 0x0020 BUS : 0xe00f MDR : 0xe00f MAR : 0x3000 CCs: N = 0 Z = 1 P = 0 Registers: 0: 0x0000 1: 0x0000 2: 0x0000 3: 0x0000 4: 0x0000 5: 0x0000 6: 0x0000 7: 0x / 22
25 Golden Results case toupper.cod (cont.) 5. Go on run 5 Simulating for 5 cycles... MemCycleCnt = 0 MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0 MemCycleCnt = 0 MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0 MemCycleCnt = 0 MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0 MemCycleCnt = 0 MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0 MemCycleCnt = 1 MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0 20 / 22
26 Golden Results case toupper.cod (cont.) 6. rdump Current register/bus values : Cycle Count : 12 PC : 0x3004 IR : 0xe00f STATE_NUMBER : 0x0021 BUS : 0x0000 MDR : 0x0000 MAR : 0x3002 CCs: N = 0 Z = 1 P = 0 Registers: 0: 0x3020 1: 0x0000 2: 0x0000 3: 0x0000 4: 0x0000 5: 0x0000 6: 0x0000 7: 0x / 22
27 22 / 22 Thanks. For any question: byu@cse.cuhk.edu.hk
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