ADD B,W,L s = Dn d = x x x x x x x x (Add) d = Dn s = x x x x x x x x x x x x
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1 T ABLE C instruction set Addressing mode Mnemonic (Name) Size Addressing mo de Dn An ABCD B s = Dn d = x (Add BCD) s = d = x + d d(an,xi) Abs.W Abs.L d(pc) ADD B,W,L s = Dn d = x x x x x x x x (Add) d = Dn s = x x x x x x x x x x x x ADD A W d = An s = x x x x x x x x x x x x (Add address) L d = An s = x x x x x x x x x x x x ADDI B,W,L s = Immed d = x x x x x x x x (Add immediate) ADDQ B,W,L s = Immed3 d = x x x x x x x x x (Add quick) ADD X B,W,L s = Dn d = x (Add extended) s = d = x AND B,W,L s = Dn d = x x x x x x x x (Logical AND) d = Dn s = x x x x x x x x x x x ANDI B,W,L s = Immed d = x x x x x x x x x (AND immediate) d(pc,xi) Immed SR or CCR ASL (Arithmetic shift left) ASR (Arithmetic shift right) B,W,L coun t = [Dn] d = x coun t = 1 d = x x x x x x x B,W,L coun t = [Dn] d = x coun t = 1 d = x x x x x x x BCHG* B bit# = [Dn] d = x x x x x x x (Test a bit and bit# = Immed d = x x x x x x x c hange it) L bit# = [Dn] d = x bit# = Immed d = x BCLR* B bit# = [Dn] d = x x x x x x x (T est a bit and bit# = Immed d = x x x x x x x clear it) L bit# = [Dn] d = x bit# = Immed d = x Left side of page 1
2 Condition flags OP co de b 15 b 0 Operation performed X N Z V C 1100 RRR rrr d [s]+[d]+[x] x u x u x 1100 RRR rrr Binary-co ded decimal addition 1101 DDD1 SSEE EEEE d [Dn]+[d] x x x x x 1101 DDD0 SSee eeee Dn [s]+[dn] x x x x x 1101 AAA0 11ee eeee An [s]+[an] 1101 AAA1 11ee eeee SSEE EEEE d s+[d] x x x x x 0101 QQQ0 SSEE EEEE d QQQ+[d] x x x x x 1101 RRR1 SS00 0rrr d [s]+[d]+[x] x x x x x 1101 RRR1 SS00 1rrr Multiprecision addition 1100 DDD1 SSEE EEEE d [Dn] ^ [d] x x DDD0 SSee eeee SSEE EEEE d s ^ [d] x x rrr1 SS10 0DDD 1110 QQQ1 SS00 0DDD EE EEEE 1110 rrr0 SS10 0DDD 1110 QQQ0 SS00 0DDD EE EEEE C X operand operand C X 0 x x x x x x x x x x 0000 rrr1 01EE EEEE Z (bit# of d) ; x EE EEEE then complement the tested 0000 rrr1 01EE EEEE bit in d EE EEEE 0000 rrr1 10EE EEEE Z (bit# of d) ; x EE EEEE then clear the tested bit 0000 rrr1 10EE EEEE in d EE EEEE Right side of page 1
3 T ABLE C.4 ( Continued) Addressing mode Mnemonic (Name) Size Addressing mo de BSET* B bit# = [Dn] d = x x x x x x x (T est a bit and bit# = Immed d = x x x x x x x set it) L bit# = [Dn] d = x bit# = Immed d = x BTST* B bit# = [Dn] d = x x x x x x x (T est a bit) bit# = Immed d = x x x x x x x L bit# = [Dn] d = x bit# = Immed d = x CHK W d = Dn s = x x x x x x x x x x x (Check register) CLR B,W,L d = x x x x x x x x (Clear) CMP B,W,L d = Dn s = x x x x x x x x x x x x (Compare) CMP A W d = An s = x x x x x x x x x x x x (Compare address) L d = An s = x x x x x x x x x x x x CMPI B,W,L s = Immed d = x x x x x x x x (Compare immed) CMPM B,W,L s = + d = x (Compare memory) DIVS W d = Dn s = x x x x x x x x x x x (Divide signed) DIVU W d = Dn s = x x x x x x x x x x x (Divide unsigned) EOR B,W,L s = Dn d = x x x x x x x x (Logical X OR) EORI B,W,L s = Immed d = x x x x x x x x x (X OR immediate) Dn An + d d(an,xi) Abs.W Abs.L d(pc) d(pc,xi) Immed SR or CCR EX G L s = Dn d = x x (Exchange s = An d = x x EXT W d = x (Sign extend) L d = x Left side of page 2
4 Condition flags OP co de b 15 b 0 Operation performed X N Z V C 0000 rrr1 11EE EEEE Z (bit# of d) ; x EE EEEE then set to 1 the tested bit 0000 rrr1 11EE EEEE in d EE EEEE 0000 rrr1 00EE EEEE Z (bit# of d) ; x EE EEEE 0000 rrr1 00EE EEEE EE EEEE 0100 DDD1 10ee eeee If [Dn] < 0 or [Dn] > [s], x u u u then raise an in terrupt SSEE EEEE d DDD0 SSee eeee [d] [s] x x x x 1011 AAA0 11ee eeee [An] [s] x x x x 1011 AAA1 11ee eeee SSEE EEEE [d] [s] x x x x 1011 RRR1 SS00 1rrr [d] [s] x x x x 1000 DDD1 11ee eeee d [d] [s], using x x x 0 32 bits of d and 16 bits of s DDD0 11ee eeee d [d] [s], using x x x 0 32 bits of d and 16 bits of s rrr1 SSEE EEEE d [Dn] [d] x x SSEE EEEE d s [d] x x DDD DDD [s] [d] 1100 AAA AAA 1100 DDD AAA DDD (bits 15 8 of d) (bit 7 of d) x x DDD (bits of d) (bit 15 of d) x x 0 0 Right side of page 2
5 T ABLE C.4 ( Continued) Addressing mo de Mnemonic (Name) Size Addressing mode Dn An + d d(an,xi) Abs.W Abs.L d(pc) d(pc,xi) Immed SR or CCR JMP d= x x x x x x x (Jump) JSR d = x x x x x x x (Jump to subroutine) LEA L d = An s = x x x x x x x (Load effective address) LINK disp = Immed s = x (Link and allo cate) LSL B,W,L coun t = [Dn] d = x (Logical shift left) W coun t = I d = x x x x x x x LSR B,W,L coun t = [Dn] d = x (Logical shift right) W coun t = I d = x x x x x x x MO VE B,W,L s = Dn d = x x x x x x x x (Mo v e) s = An d = x x x x x x x x s = d = x x x x x x x x s = + d = x x x x x x x x s = d = x x x x x x x x s = d d = x x x x x x x x s = d(an,xi) d = x x x x x x x x s = Abs.W d = x x x x x x x x s = Abs.L d = x x x x x x x x s = d(pc) d = x x x x x x x x s = d(pc,xi) d = x x x x x x x x s = Immed d = x x x x x x x x W d = CCR s = x x x x x x x x x x x d = SR s = x x x x x x x x x x x s = SR d = x x x x x x x x L s = SP d = x d = SP s = x MO VEA W,L d = An s = x x x x x x x x x x x x (Mo v e address) Left side of page 3
6 Condition flags OP co de b 15 b 0 Operation performed X N Z V C EE EEEE PC effective address of d EE EEEE SP [SP] 4; [SP] [PC]; PC effective address of d 0100 AAA1 11ee eeee An effective address of s AAA SP [SP] 4; [SP] [An]; An [SP]; SP [SP] + disp 1110 rrr1 SS10 1DDD 1110 QQQ1 SS00 1DDD EE EEEE C X operand 0 x x x 0 x 1110 rrr0 SS10 1DDD 1110 QQQ0 SS00 1DDD EE EEEE 0 operand C x x x 0 x 00SS RRRM MMee eeee d [s] x x 0 0 X ee eeee CCR [bits 7-0 of s] x x x x x ee eeee SR [s] x x x x x EE EEEE d [SR] AAA d [SP] AAA SP [d] 00SS AAA0 01ee eeee An [s] Right side of page 3
7 T ABLE C.4 ( Continued) Addressing mo de Mnemonic (Name) Size Addressing mo de Dn An + d d(an,xi) Abs.W Abs.L d(pc) d(pc,xi) Immed SR or CCR MO VEM* W s = Xn d = x x x x x x (Mo v e m ultiple d = Xn s = x x x x x x x x registers) L s = Xn d = x x x x x x d = Xn s = x x x x x x x x MO VEP* W s = Dn d = x (Mo v e p eripheral L s = Dn d = x data) W s = d d = x L s = d d = x MO VEQ L s = Immed8 d = x (Mo v e quic k) MULS W d = Dn s = x x x x x x x x x x x (Multiply signed) MULU W d = Dn s = x x x x x x x x x x x (Multiply unsigned) NBCD B d = x x x x x x x x (Negate BCD) NEG B,W,L d = x x x x x x x x (Negate) NEGX B,W,L d = x x x x x x x x (Negate extended) NOP (No operation) NOT B,W,L d = x x x x x x x x (Complement) OR B,W,L s = Dn d = x x x x x x x (Logical OR) d = Dn s = x x x x x x x x x x x ORI B,W,L s = Immed d = x x x x x x x x x (OR immediate) PEA L s = x x x x x x x (Push effective address) Left side of page 4
8 Condition flags OP co de b 15 b 0 Operation performed X N Z V C EE EEEE ee eeee EE EEEE ee eeee d [Xn] Xn [s] d [Xn] Xn [s] A second w ord is used to sp ecify the registers in v olv ed : 0000 DDD AAA Alternate b ytes of d [Dn] 0000 DDD AAA 0000 DDD AAA Dn alternate b ytes of d 0000 DDD AAA 0111 DDD0 QQQQ QQQQ Dn QQQQQQQQ x x DDD1 11ee eeee Dn [s] [Dn] x x DDD0 11ee eeee Dn [s] [Dn] x x EE EEEE d 0 [d] [X] x u x u x using BCD arithmetic SSEE EEEE d 0 [d] x x x x x SSEE EEEE d 0 [d] [X] x x x x x none SSEE EEEE d [d] x x DDD1 SSEE EEEE d [s] [d] x x DDD0 SSee eeee SSEE EEEE d s [d] x x ee eeee SP [SP] 4; [SP] effectiv e address of s
9 T ABLE C.4 ( Continued) Addressing mo de Mnemonic (Name) RESET Size Addressing mo de Dn An + d d(an,xi) Abs.W Abs.L d(pc) d(pc,xi) Immed SR or CCR R OL B,W,L coun t = [Dn] d = x (Rotate left without X) W coun t = 1 d = x x x x x x x R OR B,W,L coun t = [Dn] d = x (Rotate right without X) W coun t = 1 x x x x x x x R O XL B,W,L coun t = [Dn] d = x (Rotate left with X) W coun t = 1 d = x x x x x x x R O XR B,W,L coun t = [Dn] d = x (Rotate right with X) W coun t = 1 d = x x x x x x x R TE (Return from exception) R TR (Return and restore CCR) R TS (Return from subroutine) SBCD B s = Dn d = x (Subtract BCD) s = d = x Scc B d = x x x x x x x x (Set on condition) STOP s = x (Load SR and stop) Left side of page 5
10 Condition flags OP code b 15 b 0 Operation performed X N Z V C Assert RESET output line rrr1 SS11 1DDD 1110 QQQ1 SS01 1DDD EE EEEE 1100 rrr1 SS11 1DDD 1110 QQQ0 SS01 1DDD EE EEEE 1110 rrr1 SS11 0DDD 1110 QQQ1 SS01 0DDD EE EEEE C operand x x 0 x operand C x x 0 x x x x 0 x C operand X 1110 rrr0 SS11 0DDD 1110 QQQ0 SS01 0DDD EE EEEE X operand C x x x 0 x SR [[SP]]; x x x x x SP [SP] + 2; PC [[SP]]; SP [SP] + 4; CCR [[SP]]; x x x x x SP [SP] + 2; PC [[SP]]; SP [SP] + 4; PC [[SP]]; SP [SP] RRR rrr d [d] [s] [X] x u x u x 1000 RRR rrr Binary-co ded decimal subtraction 0101 CCCC 11EE EEEE Set all 8 bits of d to 1 if cc is true; otherwise, clear them to SR s; x x x x x w ait for in terrupt. Right side of page 5
11 T ABLE C.4 ( Continued) Addressing mo de Mnemonic (Name) Size Addressing mo de Dn An + d d(an,xi) Abs.W Abs.L d(pc) SUB B,W,L s = Dn d = x x x x x x x x (Subtract) d = Dn s = x x x x x x x x x x x x SUBA W d = An s = x x x x x x x x x x x x (Subtract address) L d = An s = x x x x x x x x x x x x SUBI B,W,L s = Immed d = x x x x x x x x (Subtract immed) SUBQ B,W,L s = Immed3 d = x x x x x x x x x (Subtract quic k) SUBX B,W,L s = Dn d = x (Subtract s = d = x extended) SW AP W d = x (Sw ap register halv es) T AS B d = x x x x x x x x (T est and set) d(pc,xi) Immed SR or CCR TRAP (T rap) s = Immed4 TRAPV (T rap on o v erflo w) TST B,W,L d = x x x x x x x x (T est) UNLK (Unlink) x Left side of page 6
12 Condition flags OP code b 15 b 0 Operation performed X N Z V C 1001 DDD1 SSEE EEEE d [d] [s] x x x x x 1001 DDD0 SSee eeee 1001 AAA0 11ee eeee An [An] [s] 1001 AAA1 11ee eeee SSEE EEEE d [d] s x x x x x 0101 QQQ1 SSEE EEEE d [d] QQQ x x x x x 1001 RRR1 SS00 0rrr d [d] [s] [X] x x x x x 1001 RRR1 SS00 1rrr DDD [Dn] [Dn] 15 0 x x EE EEEE T est d and set N and Z flags; x x 0 0 set bit 7 of d to VVVV SP [SP] 4; [SP] [PC]; SP [SP] 2; [SP] [SR]; PC v ector If V = 1, then SP [SP] 4; [SP] [PC]; SP [SP] 2; [SP] [SR]; PC TRAPV vector SSEE EEEE T est d and set N and Z flags. x x AAA SP [An]; An [[SP]]; SP [SP] + 4 Right side of page 6
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