Outline. FlexTrate : High Interconnect Density Fan-Out Wafer Level Processing for Flexible Bio-compatible Electronics

Transcription

1 FlexTrate : High Interconnect Density Fan-Out Wafer Level Processing for Flexible Bio-compatible Electronics T. Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, and S. S. Iyer Center for Heterogeneous Integration and Performance Scaling (CHIPS), Electrical Engineering Department, University of California at Los Angeles (UCLA) Outline 1. UCLA CHIPS A Brief Introduction 2. New Flexible Device Integration Technology 2-1. Introduction of FlexTrate based on FOWLP 2-2. Fine-Pitch Interconnect Formation 2-3. Process Optimization and Evaluation 3. Summary 4. Acknowledgement 1

2 Transistor SLT module 6 transistors, 4 resistors SoCs have been driven by Silicon Scaling nm CMOS Tech IBM POWER 9 Processor Global Foundries 14nm SOI edram technology, 650mm 2 24 cores and 120MB of on-chip Packaging has scaled modestly edram memory 8 billion transistors, 17 wiring levels!! Interconnect density & transistor performance are both important Courtesy IBM CHIPS Framework Tier 1 Equipment Partners ApplicaFons & Architecture Heterogeneous Systems Approximate CompuUng CogniUve CompuUng Fault Tolerance Supply chain Integrity Security Memory Subsystems Processing in Memory DFT Network on Board Design Infrastructure Thermo-Mechanical Electrical Tools ParUUoning DFT AcUve IF Design IntegraFon A processing facility for Interconnect Fabric (IF) & assembly New Tool Concepts Tool Development Scale-Up Tier 1 Foundry Partners Silicon processing Glass Flexible substrates AddiUve manufacturing Thermal compression bonding Wafer thinning Wafer-wafer integrauon Materials Fine Pitch Interconnect Substrate Materials Warpage, Stress Flexible Materials Thermal soluuons Materials for AddiUve Mfg. Reliability Devices/Components Novel switches New memory MEMS Sensors Passives, antennae Medical devices Si, Compound Semis, MEMS, and OSATs 2

3 High Performance Flexible systems will require high performance heterogeneous Chips and high interconnect density Self contained implantable and autonomous electronics has widespread applicaions Depression Parkinson's Epilepsy And many more Markovich et al But they do need Hi performance processors, heterogeneous components and innovauve power delivery and communicauon and Fine pitch interconnects on flexible substrates to conform and insert Fan-out Wafer Level Packaging (FOWLP) a Quick Tutorial Die Die Last Developed by Infineon (now Nanium) PracFced by n some form or the other by TSMC Amkor ASE 3

4 11/6/16 Concept of New Flexible Device IntegraUon FlexTrate : ConfiguraUon of Single Crystalline Dies Embedded in Flexible Substrate (a) Cross-section Flexible substrate An extremely thin large die Flexible substrate High stress (b) An array of thin small dies with sub-functional blocks Flexible substrate Low stress Small dielets embedded in a polymeric film enable bendable and stretchable structure. Thin Si is also flexible, but bending would give serious reliability issues with high stress. Methodology of FlexTrate Based on Fan-Out Wafer-Level Packaging (FOWLP) High-performance heterogeneous devices/components Flextrate Wafer FlexTrate allows for hetero integrauon with high-performance inorganic single crystal semiconductor devices (Si & GaAs etc.) and much Ughter interconnects compared to printed flexible electronics with organic semiconductors in roll-to-roll processing. 4

5 A Fabrication Flow of FlexTrate using Flexible FOWLP Process with a Biocompatible A Fabrication Flow of FlexTrate tm using Flexible FOWLP Process with a Biocompatible Si wafer (1 st handler) 1) Temporary adhesive layer formafon Removable adhesive A Si wafer (2 nd handler) 2) MulFchip flip-chip assembly on 1 st handler Si wafer (1 st handler) 5) Debonding from the 1 st handler 3) PDMS supply Si wafer (2 nd handler) 6) MetallizaFon on Si and Si wafer (2 nd handler) Si wafer (1 st handler) 4) Compression mold Removable adhesive B Si wafer (2 nd handler) 7) Debonding from the 2 nd handler Double Flip Transfer process allows wafer-level processing based on fan-out wafer-level packaging to make fine-pitch interconnects and flexible Si & III-V devices. 5

6 Properties of a Biocompatible PDMS (SILASTIC MDX / Dow) Properties Hardness Tensile strength Elongation at break Dielectric 100kHz Dissipation 100KHz Volume resistivity CTE Young modulus Tg Thermal decomposition temp. Screening test Biocompatible PDMS 30 (Shore A) 5 (MPa) ~500% 3.0 (3.01@100Hz) (0.0009@100Hz) (Ω cm) ~300 (ppm/k) 0.5 (MPa) -120 ( ) 200 ( ) or more Applicable for implantation in the human body for up to 29 days without encapsulation Comparison of Multi-Die Placement: K&S CtW Flip-Chip Bonder and Capillary Self-Assembly with Liquid Droplets (a) Pick-and-Place (b) Tohuku Capillary Self-Assembly KGD Liquid Hydrophobic Driving force: surface tension Hydrophilic K&S alpha bonder 100µm Advantage: Tight Die-Die Die placement with ~1 µm overlay tolerance Die 5mm Die Die Hydrophobic area 1mm Advantage: High thru put Batch assembly is possible with 1-2 µm alignment accuracy. 6

7 A Surface Profile of Multi-Dies Placed on the 1 st Temporary Adhesive on the 1 st Si Handler Si wafer (1 st handler) 100µm Adhesive Adhesive Adhesive Adhesive Adhesive 7mm There is very small die tilt. The maximum height difference among the Si dies is approximately 1.5 µm, similar to the dielet TTV values. Curing Temperature impact on Final Topography Height (µm) (a) *Height difference A: Between Si B: Between Si & PDMS (b) A: 1.5um B: 3-4um 100um mm mm mm Curing at 80 Curing at 40 Curing at 25 The height gap is gradually reduced with the decrease in curing temperature. 500um (c) 1-mm 2 Si dielets Si wafer (2 nd handler) Measured structure A: 0.4um B: 1.5-2um 7

8 *Height difference A: Between Si B: Between Si & PDMS Reducing First Adhesive Thickness and PDMS curing temperature Curing at 40 Curing at 25 (a) 6.0 Height (µm) (b) Height (µm) Adhesive thickness: 50µm 7mm A: 0.4um B: 1.5-2um A: 1.5um B: 3-4um (c) 6.0 Height (µm) (d) Height (µm) Adhesive thickness: 10µm A: 1um B: 1.8um 7mm A: 0.6um B: 0.7um Thinner adhesive layer (10µm) can further reduce the height gap down to 1µm Coplanarity between Si dies (Å) Summary of final dielet co-planarity studies 14,000 12,000 10,000 8,000 6,000 4,000 2, /10um 25 /50um 40 /10um 40 /50um 80 /50um Curing tempetrature / Adhesive thickness 80,000 70,000 60,000 50,000 40,000 30,000 20,000 10,000 The height gap is gradually reduced with the decrease in curing temperature Thinner adhesive layer (10µm) can further reduce the height gap down to <1µm 0 Max. height gap between Si and PDMS (Å) 8

9 Water Contact Angle Shift as a Function of Surface Modification Time with UV/O 3, and their Adhesion Properties Contact angle ( ) Hydrophilic 115 Hydrophobic Low adhesion High adhesion Treatment Fme (min) By using UV/O 3 treatment, the water contact angle is dramatically decreased, and consequently, the surface is rendered highly hydrophilic. Fine wiring formation on Si dielets & PDMS: Line Width Meas. SU8 on Au wirings m 500um Stress buffer layer on Measured width: 18um Design: 20um 100um SU8 on 9

10 An Optical Images of 10-µm-pitch Ti/Au Wirings Formed on Si/PDMS at the Wafer-Level line: 3µm Line/Space: 3µm/7µm (Design: 5µm/5µm) space: 7µm Pitch: 10µm Fine-pitch (pitch: 10µm) wirings are successfully formed on PDMS. An Optical Images of 8-µm-pitch Ti/Au Wirings Formed on Si/PDMS at the Wafer-Level Line/Space: 3.6µm/4.4µm (Design: 2µm/6µm) Pitch: 8µm Fine-pitch (pitch: 8µm) wirings are successfully formed on PDMS. 10

11 Wafer Warpage 625 (25 by 25) Si dielets embedded in Wafer bow 44 mm 44 mm Height profile (µm) 0 0 X direcuon (mm) 40 Typical FOWLP shows serious wafer bow beyond 1mm. This flexible FOWLP technology with PDMS can significantly reduce the thermomechanical stress due to the low glass transition temperature Tg of the PDMS ~50 µm Electrical Property of Fine Wirings on FlexTrate Resistance (Ω) Line width: 3um y = 522x Line width: 5um y = 128x Line width: 7um y = 68.6x Line width: 18um y = 20.8x Wire length (mm) Si wafer (2 nd handler) Measured structure TheoreUcal resistance: mm(l), 100nm(t) (Au: 2.21x10-8 Ω m) 11

12 1.8mm 1.8mm 11/6/16 Electrical Property before/after Removal & Bending TheoreUcal resistance: mm(l), 100nm(t) (Au: 2.21x10-8 Ω m) Before removal & bending Ave. 134 Ω Curvature radius: 2.5mm ~10% increase Metal rod Arer removal & bending Ave. 148 Ω Pictures of a wearable demonstrator of FlexTrate 625 Si dies embedded in The flexible substrate FlexTrate embedding large numbers of small Si dies in the biocompatible PDMS is bendable, wearable and implantable, and can be attached on the curved surfaces such as the human arm or even inserted into the cranium. 12

13 Summary FlexTrate is introduced as a hi-performance wafer-level fanout process on flexible moulded substrates BiocompaUble if needed Heterogeneous integrauon of high performance dielets including MEMS and sensors, passives, coils, antennae, baueries, supercaps.. High density Interconnects Embedded Fluidic interconnects Tight lithographic alignment of dies and wiring Mechanical /electrical tesung in progress Acknowledgements DARPA (N ) Members of the UCLA CHIPS consoruum, GINTI, Tohoku University Dow Corning for the PDMS materials used in this work NITTO for the adhesives MetrospeX LLC and Cyber Technologies for analyuc services chips.ucla.edu 13