Prediction of Encapsulant Performance Toward Fatigue Properties of Flip Chip Ball Grid Array (FC-BGA) using Accelerated Thermal Cycling (ATC)

Transcription

1 Prediction of Encapsulant Performance Toward Fatigue Properties of Flip Chip Ball Grid Array (FC-BGA) using Accelerated Thermal Cycling (ATC) ZAINUDIN KORNAIN 1, AZMAN JALAR 2,3, SHAHRUM ABDULLAH 3, NOWSHAD AMIN 1 1 Department of Electrical, Electronics and System Engineering 2 School of Applied Physic 3 Institute of Microengineering and Nanoelectronics Universiti Kebangsaan Malaysia, Bangi 43650, Selangor MALAYSIA zkornain@gmail.com; azmn@ukm.my; shahrum@eng.ukm.my; Abstract: - The role of encapsulant or underfill is preserving solder joint reliability and protecting fragile low-k chip dielectric layers in Flip Chip Packaging. Traditionally, solder joints required stiff and rigid underfill. The compliant underfill properties such as low coefficient of thermal expansion (CTE), high stiffness (Young's modulus) and high glass transition temperature (Tg), needed for solder bump protection from fatigue failure. The aim of this study is to pre-evaluate the reliability performance of several commercial underfill materials for the protection against solder bumps in Flip Chip Ball Grid Array (FC- BGA) packages. Viscoplastic finite-element simulation methodologies are utilized to predict solder joint reliability under accelerated temperature cycling (ATC) conditions. The results from Finite Element Analysis (FEA) are summarized and discussed to characterize the performance of each underfill material. Key-Words: - FC-BGA; FEA; solder bump fatigue; thermal stress 1 Introduction Flip Chip method becomes popular technology in electronic packaging industry because of small package size and high electrical performance. Flip Chip technology is a face-down attachment of the active side of the silicon die onto the substrate. This technology using solder bump as connector between silicon die and substrate as prominently referred as Controlled Collapse Chip Connection or C4 [1]. The generic configuration of the C4 package is schematically shown in Fig. 1.. Fig.1 Generic Configuration of FC-BGA One of a major concern of fatigue properties of flip-chip technology is the thermal mechanical fatigue life of the C4 solder joints. This thermal mechanical issue mainly arises from the coefficient of thermal expansion (CTE) mismatch between the silicon chip (2.5 ppm/ C) and the substrate (4 10 ppm/ C for ceramics and ppm/ C for organic). As the distance from the neutral point (DNP) increases, the shear stress at the solder joints increases accordingly. So with the increase in the chip size, the thermal mechanical reliability becomes a critical issue [2]. The invention of underfill was one of the most innovative developments to reduce the thermal mechanical stress between silicon die and substrate. Underfill is a liquid encapsulate, usually epoxy resins heavily filled with SiO, that is applied between the chip and the substrate after flip-chip interconnection. Upon curing, the hardened underfill exhibits high modulus, low CTE matching that of the solder joint, low moisture absorption, and good adhesion towards the chip and the substrate. Thermal stresses on the solder joints due to accelerated thermal cycle test (ATC) are redistributed among the chip, underfill, substrate, and all the solder joints, instead of concentrating on the peripheral joints. It has been demonstrated that the application of underfill can reduce the all- ISSN: ISBN:

2 important solder strain level to of the strain in joints, which are not encapsulated [3]. Therefore, underfill can increase the solder joint fatigue life by 10 to 100 times. However, due to uncertain performance of underfill material, it was found in electronic packaging manufacturer the failure occurred in solder bumps of FC-BGA after accelerated thermal cycling (ATC) reliability test. Fig. 2 shows the condition of bump crack after ATC captured by Scanning Electroscopic Electron (SEM). After certain study, the suitability of current underfill material in production was found as one of major factor to the failure. Therefore the needs of new replacement of underfill have to take place in order to overcome the problems. two CTE values before and after the glass transition temperature Tg, CTE 1 for T < Tg and CTE 2 for T > Tg, are usually provided by experimental results for polymer materials, the ANSYS definition of the mean or effective expansion coefficient was used for the implementation [3]: Eff.CTE ( Tg T1 ) CTE1 + ( T2 Tg) CTE2 = T T (1) where T 2 is the stress-free or reference temperature of the component being modeled. As T 1 was a -40 o c and T 2 was the underfill s curing temperature (165 O C), the effective CTE for underfill was calculated and shown below : 2 1 Underfill Substrate Die Solder crack Fig.2 SEM captured on solder bump crack In this paper, a prediction of solder bump fatigue for various commercial underfill by using commercial FEA tool, Ansys is presented to identify favorable encapsulants for 33 x 33 mm 2 Flip Chip Ball Grid Array (FCBGA) packages under ATC conditions. 2 Material Characterization 2.1 Underfill Properties Seven different types of new commercial underfills have been selected based on proposed target properties range as stated in Tab. 1. Due to consistent test method compared with data obtained from suppliers, material analysis using dynamic mechanical analysis (DMA) and thermo-mechanical analysis (TMA) were conducted in-house for obtaining underfill material properties. Tab. 2 shows the themomechanical properties for all underfill whereas underfill H (font bolded) is current encapsulant used in production and regarded as control item for the whole comparison. While Table 1 Underfill thermomechanical properties Underfill CTE E (Gpa) (ppm/c) Tg UF A UF B UF C UF D UF E UF F UF G UF H Table 2 Material properties for components in package Component Young modulus E (GPa) CTE (ppm/ o C) Poisson Ratio Silicon Die Solder Bump (Pb90Sn10) Substrate Underfill Refer to Table 1 ISSN: ISBN:

3 2.2 Package for Simulation The dimensions of the chip under study were 14.5 mm x 11.9 x 0.75mm and fully populated with high lead solder bumps (Pb90Sn10) with standoff 65 µm. The dimension of the ceramic substrate was 33mm x 33mm x 1.2 m and the underfill fillet height is 100%. The material properties of all components in the package were taken from industry and are shown in Tab. 2. Fig. 3 is the model of the global package. 80 um 80 um 60um 9 um 15 um 65 um Fig. 4 Schematic diagram of solder bump \ Outermost Bump Fig.3 3D Quarter symmetry Model of FC-CBGA 3 Finite element analysis 3.1 Solder Ball Fatigue Model Viscoplastic finite-element simulation methodologies were utilized to predict solder ball joint reliability of the same size stacked die chip scale package under accelerated temperature cycling conditions (-40C to +125C, 15min ramps/15min dwells) [4]. T h e s c h e m a t i c o f solder bump is shown Fig. 4. Due to the complex physics that encompass this type of nonlinear transient finite element analysis, only a diagonal slice of the package was modeled in order to facilitate reasonable model run times. The utilization of slice model as shown in Fig. 5 assures that a worst-case situation was simulated where two rows of bumps near die corners were modeled[5]. The bumps (Pb90Sn10) were modeled with nonlinear, viscoplastic, time and temperature dependent material properties based on Darveaux's modified Anand's. The explanations on solder joint fatigue life prediction methodology by Darveaux can be referred elsewhere [6]. Fig. 5 3D slice model of two outermost bump 3.2 Simulation Thermal Loading Fig. 6 shows the cycles of temperature loading of the simulation based on JEDEC JESD22-A104 condition G. The dwell or ramp period was l5 minutes and the temperature load was ramped up and down between the high of 125 O C and the low of -40 O C with an increment of 10 O C for each load sub-step. The thermal load application was assumed to be uniform throughout the FEA model [5][6].. Temperature (C) Simulated Cycle of Thermal Loading (125C to -40C) Time (sec) Fig. 6 Thermal Cycle Loading for simulation ISSN: ISBN:

4 4 Result and Discussion The solder joint viscoplastic strain energy density accumulated per thermal cycle was used to evaluate the fatigue life of bump interconnects and usually referred as the amount of plastic work accumulated per cycle. The Von Mises stress (Sxy) and inelastic strain (W) after second cycle of thermal loading for UF H are exhibited in Fig. 7 and Fig. 8 respectively. It clearly shown that the maximum shear stress and inelastic strain energy density occurs near the outermost edge of the solder bump. All underfills show the same impact to the contour of thermal stress in solder bumps. The lower the inelastic strain energy density accumulated per TC cycle (ΔW), the longer the thermal fatigue life of the solder joint. Fig. 9 shows the contour of solder plastic work density after second cycle of ATC at - 40 C for UF H and again the outermost solder bump has it maximum value. Fig. 7 Solder Von Mises stress in 2nd cycle at -40C for UF H. Fig. 8 Solder Von Mises inelastic stain in 2nd cycle at -40C for UF H. UBM edge Fig.9 Solder plastic work density after 2 nd cycle at -40C for UF H Fig. 9 shows the contour of solder plastic work density after second cycle of ATC at -40 C for UF H and again the outermost solder bump has it maximum value. The comparison among underfill for its effect to solder fatigue life is shown in Fig. 10. From the result, it shows the type-a underfill generates the lowest solder work per cycle which indicates the lowest solder fatigue life among all underfills. The solder bump maximum stress located, it lies at the high-lead solder bump near Under Bump Metallization (UBM) edge. This UBM edge usually caused stress concentration by its geometry shape To compare the material properties, the type-a underfill owns the intermediate value of Young's modulus and highest Tg. It means the stiff material absorbs the most of thermal stress caused by CTE mismatch between silicon chip and substrate. Therefore, type-a underfill most reduces the stress transferred into bump. In type-f underfill, it owns high Young's modulus and lowest Tg so the solder fatigue life of type-c underfill is observably worst. The combination of low Tg and high Young s modulus certainly will not protect the bump from failure. By referring to the control item (UFH) which ranked middle position, the underfill such as UFA, UFB, UFD and UFG are the possible candidates to be substitute material. UFC, UFE and UFF are totally not considered due their worse performance than UFH. Instead of protecting bump from failure, underfill also need to protect fragile low-k layer in silicon die. This need low Young s modulus of material to protect this layer from delamination. Thus, the adequate underfill material selection ISSN: ISBN:

5 becomes very critical to protect both low-k chip and solder bumps at the same time. In this study, UFA is expected affect good reliability to both critical point of failure. Another analysis for effect of underfill upon low-k dielectric layer is needed to verify this prediction. Fig.10 Solder fatigue life versus various of underfill 5 Conclusion The effects of underfill material properties on the solder bump fatigue life of FC-BGA were studied in his this paper. Seven new underfills as optional material to substitute the existing material have been evaluated to find the most promise material to protect the high lead solder bump from cracking. It was found UF A with lowest Tg and moderate Young s modulus ranked as the best candidate to replace the current material. Three other candidate namely UFB, UFD and UFG also has good potential as replacement item. [3] S. Chungpaiboonpatana and F.G. Shi, Advanced HiCTE Ceramic Flip-Chipping of 90nm Cu/low-k device: A Novel Material, Package Structure, and Process Optimization Study, 55 th Electronics Component. and Technology Conference, 2005, pp [4] K.W. Shim and W.Y. Lo, Solder Fatigue Modeling of Flip-Chip Bumps in Molded Packages, 33 th International. Electronics Manufacturing Technology Conference, 2006, pp [5] H.U. Akay, H. Zhang, and N.H. Paydar, Experimental correlations of an energy-based fatigue life prediction method for solder joints, Journal of Advance in Electronics Packaging, vol. 2. No.34, 1997, pp [6] B.A. Zahn, Comprehensive solder fatigue and thermal characterization of a silicon based multi-chip module package utilizing finite element analysis methodologies, 9 th International. ANSYS Conference and Exhibition, 2000, pp [7] R. Darveaux, Effect of Simulation Methodology on Solder Joint Crack Growth Correlations, 50 th IEEE Electronics Component and Technology Conference, 2000, pp References: [1] L. Wang & C.P. Wong, Recent Advances in Underfill Technology for Flip-Chip, Ball Grid Array, and Chip Scale Package Applications, International Symposium on Electronic Materials & Packaging, 2000, pp [2] K. M. Chen, Effects of Underfill Materials on the Reliability of Low-k Flip Chip Packaging, Journal of Microelectronic Reliability, Vol.46, No.3, 2006, pp ISSN: ISBN: