Impact of Uneven Solder Thickness on IGBT Substrate Reliability

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1 Impact of Uneven Solder Thickness on IGBT Substrate Reliability Hua Lu a, Chris Bailey a, Liam Mills b a Department of Mathematical Sciences, University of Greenwich 30 Park Row, London, SE10 9LS, UK b Semelab Limited Coventry Road, Lutterworth, Leicestershire, LE17 4JB, UK H.Lu@gre.ac.uk; Telephone: Abstract Computer simulation method have been used to investigate the effects of uneven thickness of substrate solder interconnect on the reliability of an IGBT power electronics module under cyclic temperature loading conditions. The solder material that has been used in the simulation is Sn3.5Ag and the Garofalo equation has been used to describe the solder s nonlinear mechanical behavior. The equivalent plastic strain per temperature cycle of the solder joint has been used as a damage indicator and its values for a few solder joints with various degrees of solder joint unevenness have been compared. The uneven thickness of a model is created by tilting the substrate about an edge of the substrate while the solder volume is kept constant. The results showed that the impact of the substrate tilt on crack initiation time is very similar to that of the solder joint thickness for solder joints with even thickness. A solder joint thickness control method of using ceramic spacers has also been analyzed in order to evaluate the effects of the spacers on the reliability of substrate solder joint. Introduction A typical IGBT power electronic module (PEM) contains power semiconductor devices, substrates, interconnects, and busbars etc. Fig. 1 shows a CAD drawing of the internal structure of an IGBT PEM. Figure 1. The structure of an IGBT PEM. The module contains 4 IGBTs and 4 diodes on two substrates that are soldered to a baseplate. In PEM manufacturing, soldering technique is often used to attach Direct Bonded Copper (DBC) substrates to baseplates and solder joint failure is one of the most important PEM failure mechanisms [1]. Solder joints function as both the mechanical structural support for substrate and very importantly the heat exchange interfaces between semiconductor devices and the baseplate. The thermal energy that is generated in semiconductor devices flows from the devices through the substrate to the baseplate where it is removed using, for example, liquid a cooling system. The quality of the solder joint can therefore critically affect the heat dissipation of PEMs. The materials in PEMs may have very different Coefficient of Thermal Expansion (CTE) values and temperature changes will result in stress and mechanical fatigue failure in interconnects such as solder joints and wirebonds. The lifetime of a solder joint is dependent on, among other factors, the thickness of the solder joint and thicker solder interconnect have higher fatigue resistance and longer lifetime [2]. Solder joint thickness is determined mainly by solder volume but adequate solder volume alone does not guarantee the quality of the solder joint because manufacturing defects such as voids, delamination and uneven solder thickness may occur. The causes for the uneven solder thickness could be substrate and baseplate warpage (that is caused by the bimetallic effect of the soldered system), and tilting of the substrate relative to the baseplate. To solve the warpage problem, baseplates can be machined before soldering to form a shape that cancels the warpage s effect on solder thickness, and alternatively the baseplate can be made from materials that have similar CTE to that of the substrate [3]. For the substrate tilting problem, however, there is no well recognized solution yet and the effect of it on fatigue failure has not been well documented yet. In this work, the effect of uneven solder thickness distribution caused by substrate tilting on the thermalmechanical fatigue failure of substrate solder joint is investigated using Finite Element Analysis (FEA) method and a possible solution is analyzed. Simulation Methods The basic simplified PEM structure that is used in this work consists of a DBC substrate (which is made of an AlN layer that is covered with copper on both sides), a base plate, and a Sn3.5Ag solder layer that joins them together. Fig. 2 shows the FEA model of the structure and in Table 1 the dimensions are listed /15/$ IEEE Electronic Components & Technology Conference

2 thermal-mechanics fatigue life of the model device. The loading history is shown in Fig. 3. The minimum temperature, the maximum temperature, the ramp times, and the dwell times are -55 C, 125 C, 15 min, and 15 min respectively. Simulations start at the stress free temperature of 125 C and continue for s to include three complete cycles plus a 15 min leading time. Figure 2. FEA model of DBC substrate model on Table 1. The dimensions of the model. L, W, and t are length, width and thickness respectively. The units are mm. DBC Sn3.5Ag Copper material AlN Copper solder Baseplate LxWxt 22x22x1 20x20x0.3 20x20x0.3 30x30x3 The solder alloy in the model is assumed to be Sn3.5Ag. Like many other solder materials, its high homologous temperature (even at room temperature) means that creep is the major deformation mechanism. The constitutive law of Sn3.5Ag can be described by Eq. 1 n Q cr A sinh e exp (1) RT where cr is the creep strain rate, e is von Mises effective stress, R is the universal gas constant, T is temperature in Kelvin, A, η and Q are material constants that are listed in Table 2. Table 2. Visco-plastic model parameters for Sn3.5Ag [4]. A (s -1 ) n η (1/MPa) Q/R(K) 9x Apart from solder, other materials are treated as elastic or elasto-plastic solids and their properties are shown in Table 3. σ y and σ t are the yield stress and plastic tangent modulus. E, ν and α are the Young s modulus, Poisson s ratio and the coefficient of thermal expansion (CTE) respectively. Table 3. Elasto-plastic Material. E(GPa) ν α ppm/k σ y(gpa) σ t (GPa) Cu AlN Sn3.5Ag A cyclic temperature loading is applied to the model in order to investigate the effect of substrate tilt angle on the Figure 3. The temperature loading profile. The models with uneven solder thickness are created by rotating the substrate. The total volume of solder joint is kept a constant for all the models. For simplicity, the rotation axis is parallel to one edge so that the resulting model has a symmetry plane and a ½ model can be used in the simulations. The substrate tilting and the unevenness of solder joint is characterized by the rotation angle, or the tilt angle as it will be referred in this paper. After the substrate rotation, the solder joint thickness is the small at one edge and increasing linearly to reach the maximum at the opposite edge. For a tilt angle of θ, the minimum and maximum solder thicknesses are t0 1 t1 W0 sin (2a) cos 2 and t0 1 t2 W0 sin (2b) cos 2 where t 0 and W 0 are the solder thickness and width when there is not substrate tilt. For fixed t 0 and W 0 the theoretical maximum tilt angle is 1 2t 0 max tan (3) W0 If t 0 and W 0 are 0.3 mm and 20 mm respectively, the maximum tilt angle In this work the maximum max tilt angle is limited to 1.6 to avoid poor quality mesh elements. Fig. 4 shows the cross section of a model with θ=1.6. At this tilt angle, the minimum and maximum solder thickness are about 21 µm and 580 µm respectively. Figure 4. The model with substrate tilt angle of

3 Results and Discussions Model device with tilt angles from 0 to 1.6 degrees in steps of 0.2 have been analyzed using FEA software package ANSYS Release 12. The temperature loading history is shown in Fig. 3. In low cycle fatigue analysis of solder alloys, equivalent plastic strain can be used as a damage indicator. The higher the value the grater the damage that may leads to fatigue failure. Fig. 5 shows the distribution of equivalent plastic strain in the solder joint of the model device without substrate tilt at the end of the simulation time of s. The strain is the highest at the corners of the solder joint and the maximum values are found at the baseplate side corners. In Fig. 6, distributions are shown for the θ=1.4 model. A consequence of the uneven solder thickness is that the maximum strain value is much higher and the strain is concentrated more on the thinner part of the solder joint. In order to compare the reliability of the substrate model assemblies with different tilt angles, the accumulated plastic strain per cycle ( t ) ( t), where t is time and τ is the period of the cyclic loading, can be used because it can be linked to the number of cycles to failure under cyclic loadings. is usually averaged over a small volume on the predicted fatigue path. In order to take into account the contribution of element size, volume weighted average method is used. In Fig. 6, the volume over which the volume weighted average value of are marked. Figure 5. Accumulated equivalent plastic strain at t=11700 s on the substrate side (top) and the baseplate side (bottom) of the solder interconnect for the model with θ=0. Figure 6. Solder joint substrate side (top) and baseplate side (bottom) accumulated equivalent plastic strain at t=11700 s. The tilt angle θ=1.4. The black box marks the volume in which the volume weighted average values are calculated. The number of cycles to failure N f for solder joints under cyclic loadings can be described by the power law (Eq. 4), which is a variation of the Coffin-Manson s law for low cycle fatigue. N C f (4) where C and β are empirical constants. For metals the value of β ranges from 1.43 and 2.0 [5]. The reported value for Sn3.5Ag solder in the literature varies from 1 to 2 [6-9]. This variation is thought to be caused by microstructure of the specimens and the failure criteria used in the tests. Since is evaluated over a small volume, N f can be regarded as the lifetime of that volume and therefore can be regarded as the solder joint crack initiation time for the solder interconnect. For different tilt angles the values of and N f vary and in the following they are treated as functions of the tilt angle θ. In this work, no attempt has been made to predict the lifetime values. Instead, a relative lifetime change parameter D is used for comparing reliability of substrate models with tilt angles and the reliability of the model without tilt. The parameter D is defined in Eq. 5. N ( ) (0) f D (0) ( ) N f (5) 1890

4 Fig. 7 shows 1/ and D as functions of θ. The parameter β is assumed to be 1 in this plot. The results show that the values fall approximately on straight lines. This means that the two parameters are both linearly proportional to θ. Eq. 6 is a curve fit of the 1 / vs. θ data. The R 2 value for the curve fit is which shows the quality of the fit. 1. (6) Eq. 6 describes how tilt angle affects the crack initiation time. and therefore when the tilt angle is small and the (minimum) thickness is greater than 200 µm. At larger tilt angles (smaller t min ), however, the effect of solder thickness is greater than the reduction of t min that is caused by the increase in the tilt angle. Figure 8. Lifetime reduction parameter D as a function of the tilt angle. Figure 7. 1/ and the lifetime reduction parameter D (for β=1) as functions of the tilt angle θ. In Fig. 8, D values for a few β values are shown as functions of θ. Shows. If β deviates from 1 then the nonlinear behavior of D shows up. For θ=1, the reduction of lifetime ranges from 49% to 74% when β changes from 1 to 2. At the maximum tilt angle of 1.6, lifetime reduction can be as high as 97% for β=2. This shows how great the impact of tilt angle could be if substrate tilt angle is close to the maximum value. From the results discussed above, it is clear that substrate tilt can reduce the time to crack initiation in power module substrate solder joints. This is similar to the effect of the reduction of solder overall thickness that is caused by reduction in solder volume or loss of solder in the reflow process. In order to compare tilt angle and nominal solder thickness variation for their effects on the reliability of PEM substrate solder joints, simulations have been carried out to calculate for solder joints with uniform thickness of between 50 to 300 µm in steps of 50 µm and the results are shown in Fig. 9 in which 1/ is plotted against the minimum thickness of models with tilt substrate or against the thickness of the models with even solder joint thickness. The model with substrate tilt has a fixed volume and the minimum thickness t min ranges from 300 to 21 µm as θ changes from 0 to 1.6. The two result set are very similar in trend especially It should be pointed out that crack initiation is not equal to failure. As crack grows, the rate of growth may slow because of the reduced effective size of the solder joint. For the device with non-zero tilt angles, the slow-down may be faster because as cracks grow into thicker part of the solder joint stress and equivalent strain may decrease. This means that if the failure criterion is defined as the cracking of a large proportion of solder joint the effect of tilt angle will not be as serious as the reduction in the solder joints average thickness. Figure 9. 1/ for the devices with a fixed solder volume but different tilt angles, and the devices with uniform thickness solder joint. The substrate tilt also affects the thermal performance of the assembly. To model the temperature distribution in the 1891

5 substrate assembly, a layer of 100 µm thick silicon die is added to the model shown in Fig. 2 and it is bonded to the DBC with a layer of 100 µm Sn3.5Ag solder. A uniform heat flux, which is equivalent to 2000 W power dissipation in the silicon die, is applied to the top of the silicon die. The thermal conductivity of Cu, AlN, SnAg and Si are 390, 285, 78 and 149 W/mK respectively. The bottom of the baseplate is fixed at 20 C while convective heat transfer boundary condition is applied to all other exterior surfaces and the film coefficient and the bulk temperature are 10 W/m 2 K and 20 C respectively. Ansys was used in this thermal analysis and Fig. 10 shows the temperature distribution of an assembly with 1.6 degree tilt and one without tilt. Because of the tilt, temperature increases and the peak moves towards the side of the substrate with higher solder thickness. The peak temperatures in the two models are 110 C and 117 C respectively which give a temperature increase rate of about 4.4 C per degree of substrate tilt angle. If crack starts to propagate at the thinner end of solder joint where more heat passes than at the thicker end, the temperature will start to rise even further and may potentially cause seriously damaging overheat in the silicon die. FEA model of this assembly. This assembly is based on a test PEM that is being studied at Semelab UK and unlike the model for the substrate tilt study; the top copper layer on the DBC substrate has two separate parts. The thicknesses of the layers are the same as in the previous models but the ceramic substrate dimensions are 49.5mm x 58.2mm x 1.0mm. In the FEA model the spacers are included in the analysis because they are difficult to remove in the manufacturing process after solder joints are formed. Any solution like this should increase the reliability of the final product and it should be achievable at acceptable costs to manufacturers. This method is still being tested and at same time computer simulation has been used to analyze the impact of spacers on the assembly that is subject to cyclic temperature loadings. Figure 11. Ceramic spacers for the control of solder thickness. Figure 10. Top view of the temperature distribution in the substrate model without tilt (top) and that with 1.6 of tilt (bottom). Because of the damaging effect of substrate tilt, it is important that it is monitored and controlled in the manufacturing process. One possible method of controlling the solder thickness that has been tested at Semelab is to use spacers at the corners of the substrate during reflow process so that solder joints form with even standoff height. Fig. 11 shows a substrate assembly with spacers and Fig. 12 shows the Figure 12. FEA ½ model of a substrate assembly with ceramic spacers. The spacers are made from AlN which has a much smaller CTE than the solder. When temperature changes this CTE mismatch will result in stress concentration around the spacers. In order to analyze this effect a models with spacers has been analyzed using FEA and the results are compared 1892

6 with these for a model without spacers. In the model with spacers, the spacers are assumed to be bonded with the substrate and the baseplate. The stress free temperature is set at 20 C and the temperature profile is shown in Fig. 13. The profile is different from the one in Fig. 3 so that temperature can be both above and below the stress free temperature. Figure 13. Temperature loading history for the spacer effect analysis. Fig. 14 shows the effect of spacers on the accumulated plastic strain distributions in the two models. When spacers are present, in solder peaked at the corners where spacers are located and the maximum value increased by about 90%. Further analysis has shown that this strain concentration is most serious when the temperature is above the stress free temperature of 20 C. This suggests that if the spacers are not bonded to the substrate and the baseplate the spacer effect would be much weaker. In fact, in another simulation where the stress free temperature is 125 C and the spacers are not bonded to the substrate, the increase in the maximum value is only about 2.5% compared to the case where there are no spacers. Conclusions Our results show that uneven solder thickness that is caused by substrate tilt has very similar effect on crack initiation time to the reduction of solders thickness. The results can be used as a guideline to evaluate the quality of power module solder joint. Further work will be carried out to determine how tilt angle affect the lifetime of solder joint for predetermined failure criteria. Placing spacers at the solder joint corners could improve the evenness of solder but the spacers should not be bonded to both the baseplate and the substrate at the same time. Acknowledgments The authors would like to acknowledge the financial support of the Clean Sky (Grant agreement no: , project title: Sample power electronic module construction for testing, characterization and manufacturability assessment), and EPSRC through the Underpinning Power Electronics 2012: Hub grant (reference: EP/K035304/1). References 1. M. Ciappa, "Selected failure mechanisms of modern power modules," Microelectronics Reliability, vol. 42, 2002, pp H. Lu, T. Tilford, C. Bailey, D. R. Newcombe, "Lifetime Prediction for Power Electronics Module Substrate Mount-down Solder Interconnect", in Proc. International Symposium on High Density Packaging and Microsystem Integration (HDP'07), Shanghai, China, June 26-28, 2007, pp T. Schutze, H. Berg, M. Hierholzer, "Further improvements in the reliability of IGBT modules," in Industry Applications Conference, Thirty-Third IAS Annual Meeting, vol.2, Oct 12-15, 1998, pp J.H. Lau, (editor), Ball Grid Array Technology, McGraw- Hill, 1995, pp G. E. Dieter, Mechanical Metallurgy, Mc Graw Hill Series in Science and Engineering, 1988, pp C. Kanchanomai, Y. Miyashita and Y. Mutoh, Lowcycle fatigue behavior and mechanisms of a lead-free solder 96.5Sn/3.5Ag, J. Electron. Mater., Vol. 31, no. 2, pp , C. Kanchanomai, Y. Miyashita, Y. Mutoh, S.L. Mannan, Influence of frequency on low cycle fatigue behavior of Pb-free solder 96.5Sn-3.5Ag, Materials Science and Engineering: A, Vol. 345, Issues 1-2, pp , 25 March Y. Kariya, M. Otsuka, Mechanical Fatigue Characteristics of Sn-3.5Ag-X (X=Bi, Cu, Zn and In) Solder Alloys, J. Electron. Mater., vol. 27, no. 11, pp , H.D. Solomon, Low Cycle Fatigue of Sn96 Solder With Reference to Eutectic Solder and a High Pb Solder, J. Electron. Packaging, vol. 113, no. 2, pp , 1991 Figure 14. distributions at t=11700 s in the solder joint for the model with bonded spacers (top) and the the model without spacers (bottom). 1893