Mechanical Analysis Challenges in Micro-Electronic Packaging

Transcription

1 Mechanical Analysis Challenges in Micro-Electronic Packaging Luke J. Garner, and Frank Z. Liang Intel Corporation Electrical and thermal performance enhancing features in modern integrated circuits have increased demands on the electronic package. This paper reviews two solder joint failure mechanisms; thermal cycle fatigue under compressive load and solders joint cracking in shock. Two modeling techniques are employed to study these mechanisms, response surface modeling and modal analysis. Response surface modeling is shown to be an effective means of determining the impact of multiple design variables. Modal analysis is used to calibrate a complex system model, prior to simulating shock events. Keywords: Electronic Packaging, Dynamic Modal Analysis, Solder Joint Reliability, Direct Cyclic Analysis, Design of Experiments, Response Surface Modeling and Fatigue. 1. Mechanical Analysis of Electronic Packaging The complex nature of electronic packages results from the many design constraints they must satisfy. These constraints differ significantly from structural components traditionally studied in engineering mechanics. First the package is an electronic component designed to enhance and enable the function of the integrated circuit device it supports. It must provide consistent supply of power and ensure signal integrity as a first priority. Second, the package must provide for the thermal dissipation needs of the integrated circuit. The package must scale the electrical connections of the silicon die large enough to facilitate low cost system boards. Lastly the package must physically protect the chip from environmental and handling damage. The mechanical behavior of the package is primarily considered to assess reliability impact of choices made to enhance some other area of performance. None of these classical responsibilities have prepared the package for the changes in the system environment brought on by rising thermal dissipation requirements. These requirements have caused two potentially damaging problems for the package. First, to improve thermal conductance, thermal interface materials are used between the package and the thermal solution. Some of these materials consist of solid particles embedded in a polymer matrix. To achieve optimal thermal conductance these materials must be compressed to bring the suspended particles into contact and allow solid-solid conduction. These compression loads may have a detrimental effect on the reliability of surface mount packages. Second, the mass of the thermal solution itself has increased to accommodate the rise in power dissipation requirements. These massive thermal solutions pose a risk to components on the system board in shipping and handling due to drop shocks and 2004 ABAQUS Users Conference 21

2 vibration. During these events, the dynamic motion of the thermal solution may induce excessive board flexure, damaging nearby components. Compared to the aerospace and automotive industries, prototypes of electronic packages are relatively inexpensive and small. The size and cost of these test vehicles enables testing a large sample size in multiple accelerated conditions of temperature, humidity, pressure, voltage, and acceleration. These test methods have great value and have given the electronic industry a well deserved reputation for reliability. However, statistical models can not always completely describe the failure mechanisms in increasingly complex packages. Finite element modeling provides a physics based approach to describing the phenomena observed in these accelerated tests and actual use conditions. The use of finite elements is not new to the industry, but many new areas of application are developing. In this paper, examples will be reviewed for two failure mechanisms. These examples are based on the behavior of Flip Chip Ball Grid Array (FCBGA) packages. Figure 1 shows a schematic of this package type, which consists of a silicon die bonded to a glass epoxy substrate. Solder spheres are used for both the mechanical and the electrical connection to the system board. The first mechanism is thermo-mechanical fatigue in the solder joints. In FCBGA packaging, fatigue failure occurs in the solder joints in the region under the die. This is due the local coefficient of thermal expansion (CTE) mismatch created by the silicon being tightly bonded to the substrate, as illustrated in Figure 1. The solder joints at the package corner are not likely to fail as there is little CTE mismatch between the glass-epoxy substrate and the very similar board materials. This is very unlike the behavior observed in ceramic packages where the package-board CTE mismatch leads to failure at the package corners. In FCBGA packages, the failure location shifts when compression load is applied during thermal cycling. Rather than being only in the die shadow area, failures are also noted near the package corners. In some more extreme conditions the package corner failure may occur very early in the thermal cycling. As this behavior cannot be explained by simple CTE-mismatch, the true cause must be identified so that design changes can be made to avoid such early failures. The second failure mechanism is solder joint cracking due to excessive board flexure. This mechanism is being driven by the increase in thermal solution mass. During a drop, the acceleration of the heat sinks mounted on the board will add to the dynamic response and may cause excessive board flexure. As shown in Figure 1, the package resistance to bending will create tensile loads on the solder joints. The tensile loads may initiate and propagate solder joint cracks. Finite element analysis has been applied to study both of these issues. The details of the finite element analyses are reviewed. Each case employs novel modeling techniques to improve the model output and ease of use. The results of the finite element analyses are compared with empirical results. The implications to the reliability of FCBGA packages are discussed. 2. Compression Loading Effects in Thermal Cycling High performance thermal solutions are common in the microelectronic industry. While many of these have been in use for many years for microprocessors, they are now required in new ABAQUS Users Conference

3 applications. These include high performance memory controller hubs and network processors. Unlike many of the microprocessor packages these packages are most likely ball grid arrays (BGA) packages mounted directly on the system board. The effect of substantial compression loading on the reliability of solder joints has not been widely studied. Eyman and Kromann recently noted that that compression loading had detrimental effect on the thermal cycle reliability of plastic ball grid array components [1]. Also, many of the classical reliability assessment methods, both analytical and experimental, have not included these effects. 2.1 Experimental Approach A generic loading fixture has been developed to experimentally evaluate the compression load effects. Figure 1 shows a schematic of this fixture. It consists of a top loading plate with multiple hole patterns so the effect of support span can be studied. The top plate is used to compress a low stiffness spring against a load spreader on top of the package. The load is reacted through the circuit board by four bolts offset from the corners of the FCBGA package. The spring has a low stiffness such that any creep deformation of the board will have a minimal effect on the load. A simple aluminum disk is used to transfer the spring load to the top of the exposed silicon die of the FCBGA package and simulates the heat sink. Thermal grease is used to prevent damage to the die from handling and fretting in thermal cycle. Figure 2 shows the fixture used in these tests. The board is allowed to deflect between the four support points. To minimize the constraint on the board the fixture uses dome washers to support the board from one side only. The precise load is applied to the fixture by means of a hydraulic load frame. The fixture is placed in the frame with a plate supporting the bottom of the fixture and a platen is used to displace the top plate. When the desired load is reached, the load frame cross head is locked. The nuts are then tightened on the bolts until 50% of the load has been removed from the load frame load cell. This action tensions the bolts so that when the cross head is raised the desired load continues to be applied to the component. The 50% load reduction technique was determined through experimentation using a load cell as the component in the fixture. The fixture assembly is then placed into accelerated thermal cycle testing chambers. A standard JEDEC thermal cycle condition was used: TCX (-40 to 85 C). High-end temperature was limited to 100 C to avoid exceeding the board glass transition temperature which would cause excessive damage to the joints and board. At 250 cycle intervals, both electrical test and dye & pry failure analysis were conducted to monitor the performance of BGA solder joint. Test vehicle substrate and test board were designed in a such way that all of the joints in the critical areas (under the die and package corners) can be fully tested electrically. Dye and pry allows accurate measurement of solder joint fatigue crack area. This measurement is made by staining the sample with dye and then separating the board and package to expose the crack face. The stained area of the fractured solder joint indicates the crack area. Solder joints with crack areas greater than a critical value are considered failures. 2.2 Finite Element Analysis To further understand the mechanisms of failure, finite element analysis (FEA) was used. Figure 3 shows a typical mesh of the board and FCBGA package. Reduced integration 2nd order elements 2004 ABAQUS Users Conference 23

4 brick (C3D20R) and wedge (used only in the die fillet) elements were selected. The ABAQUS standard solver was used for all simulations. The symmetry of the load and the package allowed the use of a quarter-symmetric model. As the most critical solder joints were those near the die corner and the package corner, the mesh was refined in these areas to improve accuracy, as shown in Figure 3. For this sensitivity analysis, the details of the solder joint pad design have been excluded. Linear elastic constitutive models were used for all package components except for the solder joints. The solder behavior was simulated by a model from Hong and Burrell [3]. This model includes isotropic hardening plasticity and power law creep. Since the board creeps during these tests, the long-term Young s modulus was used for the board properties. Tests showed that the long-term modulus is about 80% of the instantaneous modulus. The analysis proceeded through the steps depicted in Figure 5. The board surface mount and package assembly induced stresses were included by first cooling the package and board from the solder solidus temperature. Next, the compression load is applied to the top of the die as a distributed load and the board movement is constrained at the desired support points. These support locations are highlighted in Figure 2. For each analysis, all of the nodes in one of the highlighted elements were constrained in the vertical direction only. The model then simulates three thermal cycles to obtain a stable hysteresis in the solder. At all times the model temperature is uniform. 2.3 Response Surface Model To gain further insight into the effect of compression loads in differing system conditions, a designed experiment was conducted using FEA. The input variables selected were the thermal compression load magnitude, the board thickness, and the support span. The experiment design was a full factorial with a center point added, for nine total cases as shown in Table 1. The increment in the inelastic strain energy density (ISED) from the 2nd to the 3rd thermal cycle was used for the fatigue predictions. This value has been showed by Darveaux [3], among others, as a good predictor of fatigue damage in solder joints. These results were extracted at the centroid of each element in the top layer of the corner solder joint. These were then averaged by element volume over layer of elements. These results are then input in a statistical analysis tool to generate the response surface. The fit of the RSM model to the FEA model is shown in Figure 6. This may be improved by increasing the number of cases, but the RSM appears to sufficiently fit the FEA results, R 2 =.98. Using the RSM, predictions for any case in the range of the input variables can be quickly calculated. As part of the thermal cycle evaluation, boards of select thicknesses were thermally cycled through their equivalent life with varied loads. For this study the largest support span was used without the back plate, which allowed for the greatest degree of board flexure. For each experimental case, the ISED increment was calculated using the RSM. Figure 7 shows the fit of the experimentally observed failure rate to the ISED increment. The failure rate shown is for electrical failure at the life equivalent readout for the accelerated thermal cycle test (-40 to 85 C). All the failures in these tests occurred at the package corners. Test legs without any failures were ABAQUS Users Conference

5 assigned an arbitrary failure rate of 0.1 for the purposes of visibility in the figure, but these points were not used to calculate the fit. A power law for the increment in ISED was used as has been suggested by Darveaux [3]. From the figure, it can be seen that the fit is quite good with an R 2 value of Using the above fit, one can now estimate the failure rate prediction for any combination of load, span and board thickness. This information can then be communicated to system designers in the form of design limits to ensure reliable performance of the package throughout life. 3. Dynamic Modeling Analysis for Circuit Board Dynamic modeling analysis has been widely used in machinery, automobile and civil engineering industries, however, application in electronic packaging industry is still unpopular. The more challenging thermal requirements mentioned above are driving package and board design improvement. As a cost effective virtual prototyping tool, FEA has been developed to evaluate and predict the reliability of products in shock and vibration induced by shipping and end user handling of systems. 3.1 FEA Model Description The system in this study is typical of boards used in high performance communications equipment. Figure 8 shows the finite element model used in this analysis. The system consists of a main system board with a smaller mezzanine board. The primary components on the board are three FCBGA Network Processing Units (NPU); two on the main board and one on the mezzanine board. Each processor has a heat sink which is held on by a simple clip. The board is designed to slide into a rack system, with connectors to connect the main board to the rack power supply and internal communication back plane. The rack supports the board with slides on the sides for easy removal. Second order solid hex elements were used for most models except the front panel which used shell elements. A mesh sensitivity study showed that the model is not sensitive to the mesh density in the range investigated. The material properties were obtained from lab tests or handbooks. Acceleration or displacement boundary conditions were applied at the sides of the board, the front panel and the back plane connectors for shock and modal analyses, respectively. For the shock models the measured shock impulse was input directly into the model as an acceleration boundary condition. 3.2 Modal Analysis vs. Direct Time Integration There are many advantages for using modal analysis over direct time integration dynamic modeling techniques; most significant is the 20x improvement in runtime. In addition, experimental data from modal tests is easily obtained for model validation, improving confidence in the model and ensuring the physics of the problem are accurately captured. The primary disadvantage of modal analysis is its inability to handle nonlinearity. Currently FEA software tools can only handle linear modal analysis. In electronic packaging, nonlinear behavior 2004 ABAQUS Users Conference 25

6 is due to nonlinear stiffness and nonlinear damping, however, these are only weakly nonlinear. A linear dynamic model can still find a good approximation to a nonlinear system in a limited range of input. The validated modal model could be extended to the non-linear domain using subspace projection if required. 3.3 Modal Model Validation Natural frequencies, mode shapes and damping are the key parameters for modal model validation. Experimental techniques of modal testing can provide these parameters. The modal test was conducted by applying a random input through an exciter at a loading point on the circuit board. A picture of this setup is shown in Figure 9. A force transducer measured the input force and an array of light weight accelerometers was placed on the board to measure the responses at each point on a grid. In this case a line of 11 accelerometers was used to measure the board one row a time until all the grid locations are covered. The natural frequencies, mode shapes and damping ratios for each mode are extracted from the test data through modal analysis software. Mode shape validation can be done not only by visualization through animation, but also by computing the Modal Assurance Criterion (MAC), a correlation coefficient between the two mode shapes. If the coefficient is equal to 1.0, then the two shapes are perfectly correlated. MAC jk T φmjφak = T T ( φ φ )( φ φ ) ak ak 2 mj mj φ ak - k th eigenvector from analytical model φ mj - j th eigenvector from measurement Handling complex modes and system nonlinearity are two challenges in modal model validation. Measurement noise and the signal syntheses inaccuracy can cause difficulty in ascertaining the authenticity of the complex modes from experiments. If two real modes are close to each other and not analyzed accurately, then both real modes may be interpreted as complex modes. The presence of nonlinear responses may also lead to identification of false complex modes. If the FEA tool does not output complex eigenvectors, then accurately comparing the real modes from FEA to the complex modes from the modal test can be a challenge. If the imaginary values are small relative to the real values, then the imaginary part may be ignored and only the real part eigenvector is used in the comparison with FEA. Fiswell [1] suggested a transformation to convert the complex mode shape matrix to real mode shape matrix before comparing it with the FEA real mode matrix. Φ R = Re( Φ C ) + Im( Φ C )(Re( Φ C ) T Re( Φ C )) 1 Re( Φ Im( Φ The subscripts R and C for the matrices represent real and complex, respectively. Using this technique the MAC was calculated. The results of the model validation are given in Table 2. The results for the first three modes are very good, with MAC values of 0.76 or greater. Figure 10 shows a visualization of the first and second modes for both the FEA modal and the ABAQUS Users Conference C ) T C )

7 modal test data, with excellent agreement. The resonant frequency of each mode is also given in Table 2. While the matching of frequency is quite good, the MAC is poor for the higher modes (4-7). There is room for improvement, but these results are encouraging, as the dynamic response is dominated by the lower order modes. Test results from further random vibration and shock tests of the system board have also confirmed the sufficiency of the modal space. There may be several reasons for the discrepancy between the model and experiment. There is uncertainty in the boundary conditions. Also, the experimental data may introduce some error due to accelerometer mass and limited grid resolution. Grid location mismatch between model and experiment can also lead to discrepancies, since the model points may not exactly align with those used for the modal test. 3.4 Shock Model Validation After modal model validation, we can simulate the effects of shock impulses due to shipping with the validated FEA model. While acceleration is easy to measure in shock tests, it does not provide sufficient accuracy to differentiate between two locations on the same test board. Instead a high speed camera and vision system metrology has been developed to track the displacement of the board during the shock event. With this metrology, the sensitivity in error detection has been greatly improved. Figure 11 shows the comparison of the displacement from the model and the high speed camera system. Further confirmation was gained by comparing the board strains derived from the model with measurements using strain gauges as shown in Figure 12. As can be seen from these figures the model captures the behavior very well. Modal analysis based models can be validated and updated by using the modal test data. When the natural frequencies, mode shapes and damping are confirmed, a dynamic event simulation such as a shock event can be modeled with confidence. The dynamic model can be further validated by using high speed camera measurements and strain gauges. 3.5 Conclusion Analysis techniques were reviewed that discussed two prominent failure mechanisms in FCBGA packages. These mechanisms were analyzed using finite element analysis techniques, response surface modeling and modal analysis. Response surface analysis is a very effective technique for understanding the effects of multiple design variables over wide ranges. Once the RSM has been created, it may be used to interpolate results, eliminating the need for additional finite element analyses. Modal analysis is a very efficient means of simulating the dynamic response of electronic system boards. Results of the modal analysis can be validated readily with test results using the modal assurance criterion. With a validated modal analysis, the system response to shock events can be simulated with confidence ABAQUS Users Conference 27

8 4. References 1. Eyman, M L, Investigation of Heat Sink Attach Methodologies and the Effects on Package Structural Integrity and Interconnect Reliability of the 119-Lead Plastic Ball Grid Array Proc. Elect. Comp. and Tech. Conf. 1997, pp Hong B Z, and Burrell, L G, Modeling Thermally Induced Viscoplastic Dformation and Low Cycle Fatigue of CBGA Solder Joints in a Surface Mount Package, IEEE Trans. on Comp., Packaging, and Manu. Tech. Part A, Vol 20. No 3, 1997, pp Darveaux, R, Effect of Simulation Methodology on Solder Joint Crack Growth Correlation, Proc. Elect. Comp. and Tech. Conf. 1997, pp M. I. Friswell and J. E. Mottershead. Finite Element Model Updating in Structural Dynamics. Kluwer Academic publishers, Tables Table 1. Experimental Design for compression loading in thermal cycle. All variables and results are normalized. Case Load Support Span Board Thickness ISED ABAQUS Users Conference

9 Table 2. Comparison of the resonance frequencies and MAC for experiment and FEA modal analysis. Resonant Frequency (Hz) Mode Experiment FEA Error MAC % % % % % % % ABAQUS Users Conference 29

10 6. Figures FCBGA Package Silicon Die BGA Joint System Board Board Flexure Fracture Possible Crack Paths Possible Crack Paths Thermal Cycle Fatigue System Board Bending Moment Figure 1. Schematic of Flip Chip Ball Grid Array (FCBGA) package and solder joint failure mechanisms ABAQUS Users Conference

11 Figure 2. Compression loading test fixture. Figure 3. Quarter symmetric finite element model of the FCBGA package on a test board 2004 ABAQUS Users Conference 31

12 Figure 4. Detail of solder joint mesh, containing 4 layers of second order elements with 5 elements per layer. Top layer was used for averaging. 183 C Model Temperature 85 C 23 C Initial Temperature Solder Solidus Compressive Load Applied Creep during dwell -40 C Calculation Interval Figure 5. Schematic of FEA modeling steps for compressive loading combined with thermal cycling ABAQUS Users Conference

13 R 2 = RSM ISED (Normalized) FEA ISED (Normalized) Figure 6. Comparison of FEA calculated inelastic strain energy density and RSM fit 2004 ABAQUS Users Conference 33

14 Failure Rate (Normalized) 10 1 y = x R 2 = ISED (Normalized) Figure 7 Fit of FEA to test data for failure rate for all experimental legs Mezzanine board Front plate FCBGA and Heat sink with simplified fins Base board supported on the fixture at two edges End connectors constrained at the backplane Figure 8. Model for dynamic analysis of communication system board ABAQUS Users Conference

15 Exciter The test board Force Transducer An array of accelerometers Figure 9. Test setup for modal testing. Figure 10. Visual comparison of the first (left) and second (right) modes ABAQUS Users Conference 35

16 Displacement (normalized) Experiment FE Model Time (seconds) Figure 11. Comparison of displacement-time history for experimental data and FEA model ABAQUS Users Conference

17 Principal Strain (Normalized) FE Model Experiment Time (sec) Figure 12. Comparison of board strain versus time history for experimental data and FEA model. 7. Acknowledgements The authors would like to recognize the contributions of Yew Lip Tan for gathering the empirical data for compression loading in thermal cycle. Thanks to George Raiser for establishing the RSM methodology at Intel. Also, the authors would like to thank Wade Hezaltine, Micheal Gabriel and Marco Beltman for supporting the modal and shock data collection 2004 ABAQUS Users Conference 37