Low-temperature Ultrasonic Bonding of Cu/Sn Microbumps with Au layer for High Density Interconnection Applications
|
|
- Claud Flynn
- 5 years ago
- Views:
Transcription
1 2017 IEEE 67th Electronic Components and Technology Conference Low-temperature Ultrasonic Bonding of Cu/Sn Microbumps with Au layer for High Density Interconnection Applications Qinghua Zeng, Yong Guan, Jing Chen * Institute of Microelectronics Peking University Beijing, Country j.chen@pku.edu.cn Yufeng Jin Shenzhen Graduate School Peking University Beijing, China yfjin@pku.edu.cn Abstract Flip-chip bonding has become an efficient method to realize fine-pitch interconnection in high density interconnection applications. Thermal-compression bonding of Cu/Sn microbumps can induce extra thermal stress because of high bonding temperature, long bonding time and high bonding force. Temperature, time and force are expected to be decreased to improve the thermal-mechanical reliability of the integration systems. In this work, low-temperature ultrasonic bonding of Cu/Sn microbumps with a thin layer of gold was studied. We also studied bonding of redistribution layers (RDLs) that consisted of electrodeposited copper and a thin layer of gold. The feasibility of the low-temperature ultrasonic bonding was demonstrated through the preliminary experimental results. Cu/Sn microbumps with Au layer were successfully bonded through a quick bonding process and a followed annealing process. However, in the case of bonding of the RDLs, the cross-section of some bonded RDLs showed that cracks existed at the interface of Au/Au layers, which resulted from the uneven surface. The electrodeposition process needs improving to get a flatter surface and the parameters of the bonding process still needs to be optimized. Keywords-ultrasonic bonding; flip-chip; microbump; lowtemperature bonding; thermal-compression bonding I. INTRODUCTION Nowadays, with the development of Internet of Things applications and other smart applications, electronic products are more miniaturized, multi-functional, featuring higher density interconnection as well. Flip-chip microbumps are widely used for high density packaging systems or threedimensional integration systems, as it is capable of fine-pitch interconnection. The alignment accuracy of the flip-chip bonding (FCB) can be improved through not only increasing the resolution of the alignment stage motion and the magnification of the IR image camera but also special designs of the bonding structure. It was reported that repeatable bonding accuracy on the order of less than 100 nm was obtained by using misalignment self-correction elements in the case of Au/Au bonding [1][2]. In terms of bonding methods, thermal-compression bonding (e.g., Au/Au and Cu/Cu) and solid liquid inter diffusion bonding (e.g., Cu/Sn, Cu/Sn/Ag, Au/In and Au/Sn) are widely adopted and studied [3-6]. Direct bonding of Au/Au and Cu/Cu usually requires clean and flat surface, high bonding temperature and high bonding force to ensure that atoms can obtain enough energy to diffuse across the interface [7-10]. Generally speaking, Cu/Sn microbump is a better candidate for three-dimensional integration systems with high interconnection density. Bonding temperature of Cu/Sn microbumps is usually above the melting point of Sn (232 ) to realize transient liquid-phase bonding process, in which the intermetallic compounds (IMCs) are formed through Sn diffusing into the surrounding bulk Cu. The melting point of Cu 3Sn (677 ) is higher than common solder joints and Sn, which makes multichip stacking feasible. Therefore, the reliability of interconnections is highly improved for electronic products operated at elevated temperatures. However, the bonding temperature (above 232 ) is still high and long bonding time is needed for complete reaction between Cu and Sn to form the stable intermetallic compound (IMC) of Cu 3Sn. As a result, extra thermal stress is induced during bonding and the reliability of packaging system is seriously affected. Consequently, temperature, time and force are expected to be decreased to enhance the reliability. Ultrasonic bonding is an efficient method to decrease bonding temperature, time and force with the help of the ultrasonic energy applied during bonding. Friction causes a local steep temperature rise around the bonding interface, which results in a thermal deformation type of bonding [11]. On the other hand, ultrasonic vibration in flip chip FC bonding results in the generation of dislocations, and the atomic diffusion can be activated more easily along the dislocation lines which perform the fast diffusion channels [12-14]. Various work has been reported about ultrasonic FCB [11, 15-20]. Cu/Cu 3Sn/Cu joints were formed through ultrasonic bonding process at ambient temperature for 4 seconds under 0.6 MPa [11]. Cu/Cu bonding was realized at room temperature in 1.5 seconds by applying ultrasonic vibration together with the application of a compression force of 1gf/bump and an ultrasonic frequency of 48.5 khz [18]. Cu microbumps and Au pads were successfully bonded by using thermosonic FCB at room temperature in 0.5 seconds with a bonding force of 7 gf/bump and an ultrasonic frequency of 48.5 khz [19]. In this paper, the low-temperature ultrasonic bonding of Cu/Sn microbumps with a thin layer of gold was studied. X- ray test, cross-sections of the bonding structure and shear test of the bonded samples were carried out to evaluate the feasibility and its reliability. Low-temperature ultrasonic /17 $ IEEE DOI /ECTC
2 bonding of copper redistribution layers (RDLs) with Au layer was also studied. II. DESIGN AND EXPERIMENTS Two kinds of samples with different sizes were designed and fabricated for ultrasonic bonding experiments, namely the chip and the interposer. The chip is 6.5 mm 6.5 mm 0.5 mm and the interposer is 13 mm 13 mm 0.5 mm. The layouts of the chip and the interposer are shown in Fig. 1. The chip is bonded face-to-face with the interposer. The radius of the microbump is 35 μm and the width of the RDL is 80 μm. The pitch of the adjacent microbumps is 380 μm and the number of microbumps is 196 in total. formed by electrodeposition of copper. The second lithography (L2) was followed to develop the pattern of the Cu/Sn/Au microbumps, which were also deposited by electrodeposition. A comparison experiment was also designed, in which the Au layer with a thickness of 500 nm was directly sputtered on the surface of Sn. The copper RDL and the Cu/Sn/Au microbump are shown in Fig. 3. According to Fig. 3, the surface of the microbump is concave and this is because the rate of electrodeposition decreases from the rim of the microbump to the center of the microbump. Figure 2. Process for fabrication of the samples with Cu/Sn/Au microbumps Figure 3. The SEM photo of the electrodeposited Cu RDL and Cu/Sn/Au microbump Figure 1. The layouts of the chip and the interposer The process for fabrication of samples is presented as follows, as shown in Fig. 2. Firstly, 100 nm Ti and 500 nm Cu was deposited on the surface of the silicon wafer by sputtering. Secondly, photoresist was coated through spinning and the first lithography (L1) was carried out to develop the pattern of the RDLs. After L1, RDLs were Another kind of samples with Cu/Au RDLs were also designed and fabricated, as shown in Fig. 4. After electrodeposition of Cu RDLs, Au layer with a thickness of 500 nm was deposited by sputtering. The lift-off of the photoresist was followed in the end. In this case, the interposer and the chip were bonded through Cu/Au RDLs. The SEM photo and the three-dimensional display of the surface of the RDL are shown in Fig. 5. According to Fig. 5, the surface roughness (Ra) was nm, which was 1895
3 tested through an optical profiler. With a flatter surface, the ultrasonic energy was applied more efficiently. highest temperature of the heating plate is 300 C. It was found that the ultrasonic power would not be maintained at the same value if the ultrasonic power were set higher than 15 W in this case, as shown in Fig. 6. With a bonding force of 7 N, ultrasonic power of 15 W and time for applying ultrasonic vibration of 1 s, the samples with Cu/Sn/Au microbumps were bonded under 140 C. The samples with Cu/Au RDLs were bonded with a bonding force of 11.4 N, ultrasonic power of 6 W and time of 3.5 s under 40 C (the lowest temperature of the heating plate). The parameters of ultrasonic bonding are listed in Table. I. After ultrasonic bonding, some samples went through annealing, of which the temperature and time was 250 C and 2 hours, respectively. Figure 4. Fabrication process of ultrasonic bonding samples with Cu/Au RDLs Figure 5. The SEM photo and the three-dimensional display of the surface of the Cu/Au RDL The ultrasonic bonding was carried out through a chip-tochip flip-chip bonder. The ultrasonic power is between 0 W to 20 W and the time for applying ultrasonic vibration is between 0 to 4 seconds. The highest force is 20 N and the Figure 6. The ultrasonic power changes with time during ultrasonic bonding under the condition of 5 W/3 s and 15 W/3 s. Samples Cu/Sn/Au microbumps Cu/Au RDLs TABLE I. PARAMETES OF ULTRASONIC BONDING Ultrasonic power/w Force/N Time/s Temperature/ C
4 III. RESULTS AND DISCUSSION A. Alignment accuracy after bonding The alignment accuracy after bonding is a problem that still needs to be improved to make ultrasonic bonding more available for high density interconnection applications. During ultrasonic bonding, the ultrasonic vibration is transferred from the horn to the chip. As a result, the chip moves horizontally with the horn, which may make alignment accuracy lower than thermal-compression bonding. On the other hand, when we align two chips through IR camera before ultrasonic bonding, only horizontal direction (X-direction) and vertical direction (Y-direction) can be adjusted, which is unavoidable limitation of the bonding machine that we used. On the contrary, in the case of thermal-compression bonding, not only the X-direction and the Y-direction but also the angular direction (θ-direction) can be adjusted. Therefore, we made a comparison between a thermal-compression bonded sample and an ultrasonic bonded sample. The work of the thermal-compression bonded samples is also reported by us [20]. The X-ray photos of bonded samples are shown in Fig. 7 and Fig. 8. It was founded that the alignment accuracy of the samples made by ultrasonic bonding was worse than thermalcompression bonding. Figure 8. X-ray photos of the thermal-compression bonded samples with Cu/Sn/Au microbumps B. Cross-sections of the bonded samples Cross-sections of the ultrasonic bonded samples with Cu/Au RDLs were observed, as shown in Fig. 9. It was found that cracks existed at the bonding interface of some samples. According to Fig. 9, the cracks between Au/Au layers blocks the diffusion of atoms during annealing process. During ultrasonic bonding, the bonding force was not distributed uniformly. As a result, Au/Au layers were not contacted in some areas where the bonding force was smaller. Apart from the unavoidable limitation of the bonding equipment, the electrodeposition process needs to be optimized to decrease the difference of the height of the electrodeposited copper RDLs or microbumps. Figure 7. X-ray photos of the ultrasonic bonded samples with Cu/Sn/Au microbumps and Cu/Au RDLs Cu Au Figure 9. Cross-sections of the ultrasonic bonded samples with Cu/Au RDLs 1897
5 C. Shear test of the bonded samples Shear test was carried out to evaluate the bonding strength of the ultrasonic bonded samples. The shear strength of the samples with Cu/Sn/Au microbumps was 11.1 N (14.4 MPa). It was observed that failures occurred at the interface of Cu RDL/Cu seed layer and the interface of Cu pillar/ Cu RDL, as shown in Fig. 10. It indicated that electrodeposition of copper needed to be optimized to improve the adhesion with the under layer. Figure. 10 Photos of the surface of the samples after shear test IV. CONCLUSIONS In order to decrease the bonding temperature, time and force of the thermal-compression bonding process, a lowtemperature ultrasonic bonding of Cu/Sn Microbumps with Au layer for high density interconnection applications was proposed. The ultrasonic bonding of samples with Cu/Au RDLs was also studied. Preliminary experiments of the ultrasonic bonding were carried out. With a bonding force of 7 N, ultrasonic power of 15 W and time for applying ultrasonic vibration of 1 s, the samples with Cu/Sn/Au microbumps were bonded under 140 C. On the other hand, the samples with Cu/Au RDLs were bonded with a bonding force of 11.4 N, ultrasonic power of 6 W and time of 3.5 s under 40 C (the lowest temperature of the heating plate). The feasibility of the low-temperature ultrasonic bonding was evaluated through the reliability tests, such as X-ray test of the alignment accuracy, cross-sections of the bonding interface and shear test. The X-ray test showed that the alignment accuracy of the ultrasonic bonding was not as good as the thermal-compression bonding. Cross-sections revealed the cracks at the bonding interface of Au/Au layers as result of non-uniform bonding force. Shear strength of the ultrasonic bonded samples with Cu/Sn/Au microbumps was 14.4 MPa. It was concluded that the parameters of the ultrasonic bonding process needed to be optimized further. In our future work, the chemical-mechanical-polishing (CMP) process will be adopted to make the surface of the electrodeposited copper RDLs and copper pillars flatter and more uniform. ACKNOWLEDGMENT This work was supported by the National Natural Science Foundation of China (Grant No. U ). REFERENCES [1] T. T. Bui, L. Ma, M. Suzuki, F. Kato, S. Nemoto and M. Aoyagi, High-precision heterogeneous integration based on flip-chip bonding using misalignment self-correction elements, 2012 International Conference on Optical MEMS and Nanophotonics (OMN 2012), IEEE, 2012, pp , doi: /omems [2] T. T. Bui, M. Suzuki, F. Kato, et al, Modified thermosonic flip-chip bonding based on electroplated Cu microbumps and concave pads for high-precision low-temperature assembly applications, Electronic Components and Technology Conference (ECTC 2013), IEEE, 2013, pp , doi: /ectc [3] R. Agarwal, W. Zhang, P. Limaye, et al, Cu/Sn microbumps interconnect for 3D TSV chip stacking, Electronic Components and Technology Conference (ECTC 2010), IEEE, 2010, pp , doi: /ectc [4] A. Syed, K. Dhandapani, R. Moody, L. Nicholls and M. Kelly, Cu Pillar and -bump electromigration reliability and comparison with high pb, SnPb, and SnAg bumps, Electronic Components and Technology Conference (ECTC 2011), IEEE, 2011, pp , doi: /ectc [5] Y. C. Sohn, Q. Wang, S. J. Ham, et al, Wafer-level low temperature bonding with Au-In system, Electronic Components and Technology Conference (ECTC 2007), IEEE, 2007, pp , doi: /ectc [6] K. E. Aasmundtveit, T. T. Luu, A. S. B. Vard, et al, Hightemperature shear strength of solid-liquid interdiffusion (SLID) bonding: Cu-Sn, Au-Sn and Au-In, Electronics System-Integration Technology Conference (ESTC 2014), IEEE, 2014, pp. 1-6, doi: /estc [7] P. R. Morrow, C. M. Park, S. Ramanathan, M. J. Kobrinsky and M. Harmes, Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-si/low-k CMOS technology, IEEE electron device letters, vol. 27, 2006, pp , doi: /led [8] B. Swinnen, W. Ruythooren, P. De Moor, et al, 3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-si die containing 10 m pitch through-si vias, International Electron Devices Meeting (IEDM 2006), IEEE, 2006, pp. 1-4, doi: /iedm [9] C. Cetintepe, E. S. Topalli, S. Demir, O. A. Civi and T. Akin, A fabrication process based on structural layer formation using Au Au thermocompression bonding for RF MEMS capacitive switches and their performance, International Journal of Microwave and Wireless Technologies, vol. 6, 2014, pp , doi: /s [10] B. K. Kurman and S. G. Mita, Gold-Gold (Au-Au) thermocompression (TC) bonding of very large arrays, Electronic Components and Technology Conference (ECTC 1992), IEEE, 1992, pp , doi: /ectc [11] M. Li, Z. Li, Y. Xiao and C. Wang, Rapid formation of Cu/Cu3Sn/Cu joints using ultrasonic bonding process at ambient temperature, Applied Physics Letters, vol. 102, 2013, pp , doi: / [12] J. Li, L. Han, J. Duan and J. Zhong, Interface mechanism of ultrasonic flip chip bonding, Applied Physics Letters, vol. 90, 2007, pp , doi: / [13] F. Wang, L. Han, J. Zhong, Stress-induced atom diffusion at thermosonic flip chip bonding interface, Sensors and Actuators A: Physical, vol. 149, 2009, pp , doi: /j.sna [14] J. L, R. W, H. He, et al, The law of ultrasonic energy conversion in thermosonic flip chip bonding interfaces, Microelectronic Engineering, vol. 86, 2009, pp , doi: /j.mee [15] P. Xu, F. Hu, J. Shang, A. Hu and M. Li, An ambient temperature ultrasonic bonding technology based on Cu micro-cone arrays for 3D packaging, Materials Letters, vol. 176, 2016, pp , doi: /j.matlet [16] C. L. Chuang, Q. A. Liao, H. T. Li, S. J. Liao and G. S. Huang, Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste, 1898
6 Microelectronic Engineering, vol. 87, 2010, pp , doi: /j.mee [17] H. Ji, Y. Qiao and M. Li, Rapid formation of intermetallic joints through ultrasonic-assisted die bonding with Sn 0.7 Cu solder for high temperature packaging application, Scripta Materialia, vol. 110, 2016, pp , doi: /j.scriptamat [18] L. Qiu, A. Ikeda, K. Noda, S. Nakai and T. Asano, Roomtemperature Cu microjoining with ultrasonic bonding of cone-shaped bump, Japanese Journal of Applied Physics, vol. 52, 2013, pp. 04CB10. [19] T. T. Bui, F. Kato, N. Watanabe, et al, 15-μm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications, Japanese Journal of Applied Physics, vol. 53, 2014, pp. 04EB04. [20] Y. Guan, Q. Zeng, S. Ma, et al, Effect of Metallic Materials Films on the Properties of Copper/Tin Microbump Thermocompression Bonding, Electronic Components and Technology Conference (ECTC 2017), IEEE, 2017 (unpublished). 1899
Effect of Surface Contamination on Solid-State Bondability of Sn-Ag-Cu Bumps in Ambient Air
Materials Transactions, Vol. 49, No. 7 (28) pp. 18 to 112 Special Issue on Lead-Free Soldering in Electronics IV #28 The Japan Institute of Metals Effect of Surface Contamination on Solid-State Bondability
More informationDynamic Strain of Ultrasonic Cu and Au Ball Bonding Measured In-Situ by Using Silicon Piezoresistive Sensor
2017 IEEE 67th Electronic Components and Technology Conference Dynamic Strain of Ultrasonic Cu and Au Ball Bonding Measured In-Situ by Using Silicon Piezoresistive Sensor Keiichiro Iwanabe, Kenichi Nakadozono,
More informationFailure Mechanism for fine pitch micro bump in Cu/Sn/Cu system during Current Stressing
Failure Mechanism for fine pitch micro bump in Cu/Sn/Cu system during Current Stressing Hsiao Hsiang Yao, Alastair David Trigg, and Chai Tai Chong Institute of Microelectronics, A*STAR (Agency for Science,
More informationEspecial Bump Bonding Technique for Silicon Pixel Detectors
Especial Bump Bonding Technique for Silicon Pixel Detectors E. Cabruja, M. Bigas, M. Ullán, G. Pellegrini, M. Lozano Centre Nacional de Microelectrònica Spain Outline Motivation Summary of bump bonding
More information1 INTRODUCTION 2 SAMPLE PREPARATIONS
Chikage NORITAKE This study seeks to analyze the reliability of three-dimensional (3D) chip stacked packages under cyclic thermal loading. The critical areas of 3D chip stacked packages are defined using
More information450 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 3, MARCH 2017
450 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 3, MARCH 2017 Effects of Thermocompression Bonding Parameters on Cu Pillar/Sn-Ag Microbump Solder Joint Morphology
More informationSET Technical Bulletin
SET Technical Bulletin DIE BONDING APPLICATIONS An Innovative Die to Wafer 3D Integration Scheme: Die to Wafer Oxide or Copper Direct Bonding with Planarised Oxide Inter-Die Filling RF MEMS and Flip-Chip
More informationDrop Impact Reliability Test and Failure Analysis for Large Size High Density FOWLP Package on Package
2017 IEEE 67th Electronic Components and Technology Conference Drop Impact Reliability Test and Failure Analysis for Large Size High Density FOWLP Package on Package Zhaohui Chen, Faxing Che, Mian Zhi
More informationReliability assessment for Cu/Low-k structure based on bump shear modeling and simulation method
Reliability assessment for Cu/Low-k structure based on bump shear modeling and simulation method Abstract Bump shear is widely used to characterize interface strength of Cu/low-k structure. In this work,
More informationUltrasonic Anisotropic Conductive Films (ACFs) Bonding of Flexible Substrates on Organic Rigid Boards at Room Temperature
Ultrasonic Anisotropic Conductive Films (ACFs) Bonding of Flexible Substrates on Organic Rigid Boards at Room Temperature Kiwon Lee, Hyoung Joon Kim, Il Kim, and Kyung Wook Paik Nano Packaging and Interconnect
More informationReliability of 3D IC with Via-Middle TSV: Characterization and Modeling
Reliability of 3D IC with Via-Middle TSV: Characterization and Modeling Victor Moroz *, Munkang Choi *, Geert Van der Plas, Paul Marchal, Kristof Croes, and Eric Beyne * Motivation: Build Reliable 3D IC
More informationDeformation of solder joint under current stressing and numerical simulation II
International Journal of Solids and Structures 41 (2004) 4959 4973 www.elsevier.com/locate/ijsolstr Deformation of solder joint under current stressing and numerical simulation II Hua Ye *, Cemal Basaran,
More informationEffect of Direction of Ultrasonic Vibration on Flip-Chip Bonding
Transactions of The Japan Institute of Electronics Packaging Vol. 6, No. 1, 13 [Technical Paper] Effect of Direction of Ultrasonic Vibration on Flip-Chip Bonding Mutsumi Masumoto*, Yoshiyuki Arai*, **,
More informationBudapest, Hungary, September 2007 The Characteristics of Electromigration And Thermomigration in Flip Chip Solder Joints
The Characteristics of Electromigration And Thermomigration in Flip Chip Solder Joints Dan Yang and Y. C. Chan* Department of Electronic Engineering, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon,
More informationTCAD Modeling of Stress Impact on Performance and Reliability
TCAD Modeling of Stress Impact on Performance and Reliability Xiaopeng Xu TCAD R&D, Synopsys March 16, 2010 SEMATECH Workshop on Stress Management for 3D ICs using Through Silicon Vias 1 Outline Introduction
More informationStudy of Electromigration of flip-chip solder joints using Kelvin probes
Study of Electromigration of flip-chip solder joints using Kelvin probes Y. W. Chang and Chih Chen National Chiao Tung University, Department of Material Science & Engineering, Hsin-chu 30010, Taiwan,
More informationTHERMOMECHANICAL ANALYSIS OF ELECTRONIC PACKAGE USING FINITE ELEMENT METHOD
THERMOMECHANICAL ANALYSIS OF ELECTRONIC PACKAGE USING FINITE ELEMENT METHOD N.BhargavaRamudu 1, V. Nithin Kumar Varma 2, P.Ravi kiran 3, T.Venkata Avinash 4, Ch. Mohan Sumanth 5, P.Prasanthi 6 1,2,3,4,5,6
More informationThermal aspects of 3D and 2.5D integration
Thermal aspects of 3D and 2.5D integration Herman Oprins Sr. Researcher Thermal Management - imec Co-authors: Vladimir Cherman, Geert Van der Plas, Eric Beyne European 3D Summit 23-25 January 2017 Grenoble,
More informationLow Temperature Bonding of Pd/Ni Assembly for Hydrogen Purifier
Proceedings of the 2 nd World Congress on Mechanical, Chemical, and Material Engineering (MCM'16) Budapest, Hungary August 22 23, 2016 Paper No. MMME 103 DOI: 10.11159/mmme16.103 Low Temperature Bonding
More informationThermo-structural Model of Stacked Field-programmable Gate Arrays (FPGAs) with Through-silicon Vias (TSVs)
Manuscript for Review Thermo-structural Model of Stacked Field-programmable Gate Arrays (FPGAs) with Through-silicon Vias (TSVs) Journal: Electronics Letters Manuscript ID: draft Manuscript Type: Letter
More informationCharacteristics of Thermosonic Anisotropic Conductive Adhesives (ACFs) Flip-Chip Bonding
Materials Transactions, Vol. 51, No. 10 (2010) pp. 1790 to 1795 Special Issue on Lead-Free and Advanced Interconnection Materials for Electronics #2010 The Japan Institute of Metals Characteristics of
More informationMulti-chip Integration on a PLC Platform for 16X16 Port Optical Switch Using Passive Alignment Technique
Multi-chip Integration on a PLC Platform for 16X16 Port Optical Switch Using Passive Alignment Technique Jung Woon Lim, Hwe Jong Kim, Seon Hoon Kim and Byung Sup Rho Korea Photonics Technology Institute
More informationThin Wafer Handling Challenges and Emerging Solutions
1 Thin Wafer Handling Challenges and Emerging Solutions Dr. Shari Farrens, Mr. Pete Bisson, Mr. Sumant Sood and Mr. James Hermanowski SUSS MicroTec, 228 Suss Drive, Waterbury Center, VT 05655, USA 2 Thin
More informationSelf-Alignment with Copper Pillars Micro-Bumps for Positioning Optical Devices at Submicronic Accuracy
2017 IEEE 67th Electronic Components and Technology Conference Self-Alignment with Copper Pillars Micro-Bumps for Positioning Optical Devices at Submicronic Accuracy Yézouma D. Zonou, Stéphane Bernabé,
More informationEffect of under-bump-metallization structure on electromigration of Sn-Ag solder joints
Advances in Materials Research, Vol. 1, No. 1 (2012) 83-92 83 Effect of under-bump-metallization structure on electromigration of Sn-Ag solder joints Hsiao-Yun Chen, Min-Feng Ku and Chih Chen* Department
More informationPerformance, Packaging, Price: Challenges for Sensor Research I. Eisele Fraunhofer EMFT
Performance, Packaging, Price: Challenges for Sensor Research I. Eisele Fraunhofer EMFT Introduction There are many sensor effects... but only a a very few sensors! Outline CMOS Encapsulated CMOS/MEMS
More informationFEM Analysis on Mechanical Stress of 2.5D Package Interposers
Hisada et al.: FEM Analysis on Mechanical Stress of 2.5D Package Interposers (1/8) [Technical Paper] FEM Analysis on Mechanical Stress of 2.5D Package Interposers Takashi Hisada, Toyohiro Aoki, Junko Asai,
More informationPassionately Innovating With Customers To Create A Connected World
Passionately Innovating With Customers To Create A Connected World Multi Die Integration Can Material Suppliers Meet the Challenge? Nov 14, 2012 Jeff Calvert - R&D Director, Advanced Packaging Technologies
More informationHybrid Wafer Level Bonding for 3D IC
Hybrid Wafer Level Bonding for 3D IC An Equipment Perspective Markus Wimplinger, Corporate Technology Development & IP Director History & Roadmap - BSI CIS Devices???? 2013 2 nd Generation 3D BSI CIS with
More informationTemporary Wafer Bonding - Key Technology for 3D-MEMS Integration
Temporary Wafer Bonding - Key Technology for 3D-MEMS Integration 2016-06-15, Chemnitz Chemnitz University of Technology Basic Research Fraunhofer ENAS System-Packaging (SP) Back-End of Line (BEOL) Applied
More informationAssessment of Current Density Singularity in Electromigration of Solder Bumps
Assessment of Current Density Singularity in Electromigration of Solder Bumps Pridhvi Dandu and Xuejun Fan Department of Mechanical Engineering Lamar University PO Box 10028, Beaumont, TX 77710, USA Tel:
More informationF R A U N H O F E R I N
FRAUNHOFER Institute FoR Electronic NAno systems ENAS System Packaging 1 2 3 4 5 The actual developments of micro and nano technologies are fascinating. Undoubted they are playing a key role in today s
More informationTRENDS IN LEVENSDUURTESTEN VOOR MICRO-ELEKTRONICA PLOT CONFERENTIE
TRENDS IN LEVENSDUURTESTEN VOOR MICRO-ELEKTRONICA PLOT CONFERENTIE JEROEN JALINK 8 JUNI 2016 MICROELECTRONICS RELIABILITY 54 (2014) 1988 1994 Contents Introduction NXP Package form factor Failure mechanism
More informationDevelopment of Lift-off Photoresists with Unique Bottom Profile
Transactions of The Japan Institute of Electronics Packaging Vol. 8, No. 1, 2015 [Technical Paper] Development of Lift-off Photoresists with Unique Bottom Profile Hirokazu Ito, Kouichi Hasegawa, Tomohiro
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2007
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 12: Mechanics
More informationSolder Self-assembly for MEMS
Solder Self-assembly for MEMS Kevin F. Harsh, Ronda S. Irwin and Y. C. Lee NSF Center for Advanced Manufacturing and Packaging of Microwave, Optical and Digital Electronics, Department of Mechanical Engineering
More informationEV Group. Enabling processes for 3D interposer. Dr. Thorsten Matthias EV Group
EV Group Enabling processes for 3D interposer Dr. Thorsten Matthias EV Group EV Group in a Nutshell st Our philosophy Our mission in serving next generation application in semiconductor technology Equipment
More informationIEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 3, MARCH
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 3, MARCH 2016 471 A Self-Aligning Flip-Chip Assembly Method Using Sacrificial Positive Self-Alignment Structures Hyung
More information3D INTEGRATION A THERMAL-ELECTRICAL-MECHANICAL-RELIABILITY STUDY
3D INTEGRATION A THERMAL-ELECTRICAL-MECHANICAL-RELIABILITY STUDY K. Weide-Zaage 1, J. Schlobohm 1, H. Frémont 2, A. Farajzadeh 1, J. Kludt 1 1 Information Technology Laboratory, Leibniz University Hannover
More informationMechanical Simulations for Chip Package Interaction: Failure Mechanisms, Material Characterization, and Failure Data
Mechanical Simulations for Chip Package Interaction: Failure Mechanisms, Material Characterization, and Failure Data Ahmer Syed Amkor Technology Enabling a Microelectronic World Outline Effect of Chip
More informationResearch Challenges and Opportunities. in 3D Integrated Circuits. Jan 30, 2009
Jan 3, 29 Research Challenges and Opportunities in 3D Integrated Circuits Ankur Jain ankur.jain@freescale.com, ankurjain@stanfordalumni.org Freescale Semiconductor, Inc. 28. 1 What is Three-dimensional
More information884 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 5, MAY 2012
884 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO., MAY 212 Ultrasonic Bonding of Anisotropic Conductive Films Containing Ultrafine Solder Balls for High-Power and
More informationOutline. 1 Introduction. 2 Basic IC fabrication processes. 3 Fabrication techniques for MEMS. 4 Applications. 5 Mechanics issues on MEMS MDL NTHU
Outline 1 Introduction 2 Basic IC fabrication processes 3 Fabrication techniques for MEMS 4 Applications 5 Mechanics issues on MEMS 2. Basic IC fabrication processes 2.1 Deposition and growth 2.2 Photolithography
More informationMicro/nano and precision manufacturing technologies and applications
The 4th China-American Frontiers of Engineering Symposium Micro/nano and precision manufacturing technologies and applications Dazhi Wang School of Mechanical Engineering Dalian University of Technology
More informationProcess Modeling and Thermal/Mechanical Behavior of ACA/ACF Type Flip-Chip Packages
Process Modeling and Thermal/Mechanical Behavior of ACA/ACF Type Flip-Chip Packages K. N. Chiang Associate Professor e-mail: knchiang@pme.nthu.edu.tw C. W. Chang Graduate Student C. T. Lin Graduate Student
More informationStress in Flip-Chip Solder Bumps due to Package Warpage -- Matt Pharr
Stress in Flip-Chip Bumps due to Package Warpage -- Matt Pharr Introduction As the size of microelectronic devices continues to decrease, interconnects in the devices are scaling down correspondingly.
More informationSCB10H Series Pressure Elements PRODUCT FAMILY SPEFICIFATION. Doc. No B
PRODUCT FAMILY SPEFICIFATION SCB10H Series Pressure Elements SCB10H Series Pressure Elements Doc. No. 82 1250 00 B Table of Contents 1 General Description... 3 1.1 Introduction... 3 1.2 General Description...
More informationA Study of Friction Behavior in Ultrasonic Welding (Consolidation) of Aluminum
A Study of Friction Behavior in Ultrasonic Welding (Consolidation) of Aluminum Abstract: C.B. Zhang 1, X.J. Zhu 2 and L.J. Li 3 Mechanical & Aerospace Engineering Utah State University In the present study,
More informationEffects of underfill material on solder deformation and damage in 3D packages
University of New Mexico UNM Digital Repository Mechanical Engineering ETDs Engineering ETDs 9-3-2013 Effects of underfill material on solder deformation and damage in 3D packages Geno Flores Follow this
More informationDelamination Modeling for Power Packages and Modules. Rainer Dudek, R. Döring, S. Rzepka Fraunhofer ENAS, Micro Materials Center Chemnitz
Delamination Modeling for Power Packages and Modules Rainer Dudek, R. Döring, S. Rzepka Fraunhofer ENAS, Micro Materials Center Chemnitz The Micro Materials Center @ Virtual Prototyping Finite Element
More informationElectrical Characterization of 3D Through-Silicon-Vias
Electrical Characterization of 3D Through-Silicon-Vias F. Liu, X. u, K. A. Jenkins, E. A. Cartier, Y. Liu, P. Song, and S. J. Koester IBM T. J. Watson Research Center Yorktown Heights, NY 1598, USA Phone:
More informationSupplementary Figure 1 shows overall fabrication process and detailed illustrations are given
Supplementary Figure 1. Pressure sensor fabrication schematics. Supplementary Figure 1 shows overall fabrication process and detailed illustrations are given in Methods section. (a) Firstly, the sacrificial
More informationReliability analysis of different structure parameters of PCBA under drop impact
Journal of Physics: Conference Series PAPER OPEN ACCESS Reliability analysis of different structure parameters of PCBA under drop impact To cite this article: P S Liu et al 2018 J. Phys.: Conf. Ser. 986
More informationCoupling Capacitance in Face-to-Face (F2F) Bonded 3D ICs: Trends and Implications
Coupling Capacitance in Face-to-Face (F2F) Bonded 3D ICs: Trends and Implications Taigon Song *1, Arthur Nieuwoudt *2, Yun Seop Yu *3 and Sung Kyu Lim *1 *1 School of Electrical and Computer Engineering,
More informationEV Group. Engineered Substrates for future compound semiconductor devices
EV Group Engineered Substrates for future compound semiconductor devices Engineered Substrates HB-LED: Engineered growth substrates GaN / GaP layer transfer Mobility enhancement solutions: III-Vs to silicon
More informationTemperature-dependent Thermal Stress Determination for Through-Silicon-Vias (TSVs) by Combining Bending Beam Technique with Finite Element Analysis
Temperature-dependent Thermal Stress Determination for Through-Silicon-Vias (TSVs) by Combining Bending Beam Technique with Finite Element Analysis Kuan H. Lu, Suk-Kyu Ryu*, Qiu Zhao, Klaus Hummler**,
More informationThrough-Wafer Interconnects for High Degree of Freedom MEMS Deformable Mirrors
Through-Wafer Interconnects for High Degree of Freedom MEMS Deformable Mirrors Alioune Diouf 1, Thomas G. Bifano 1, Jason B. Stewart 2, Steven Cornelissen 2, Paul Bierden 2 1 Boston University Photonics
More informationElectromigration Immortality of Purely Intermetallic Micro -bump for 3D Integration
Electromigration Immortality of Purely Intermetallic Micro -bump for 3D Integration Hsiao-Yun Chen,, Chih-Hang Tung, Yi-Li Hsiao, Jyun-lin Wu, Tung-Ching Yeh, Larry Liang-Chen Lin, and Chih Chen 1 Douglas
More informationMultilayer Wiring Technology with Grinding Planarization of Dielectric Layer and Via Posts
Tani et al.: Multilayer Wiring Technology with Grinding Planarization (1/6) [Technical Paper] Multilayer Wiring Technology with Grinding Planarization of Dielectric Layer and Via Posts Motoaki Tani, Kanae
More information3D Stacked Buck Converter with SrTiO 3 (STO) Capacitors on Silicon Interposer
3D Stacked Buck Converter with SrTiO 3 (STO) Capacitors on Silicon Interposer Makoto Takamiya 1, Koichi Ishida 1, Koichi Takemura 2,3, and Takayasu Sakurai 1 1 University of Tokyo, Japan 2 NEC Corporation,
More informationEE143 LAB. Professor N Cheung, U.C. Berkeley
EE143 LAB 1 1 EE143 Equipment in Cory 218 2 Guidelines for Process Integration * A sequence of Additive and Subtractive steps with lateral patterning Processing Steps Si wafer Watch out for materials compatibility
More informationAlternative deposition solution for cost reduction of TSV integration
Alternative deposition solution for cost reduction of TSV integration J. Vitiello, F. Piallat, L. Bonnet KOBUS 611 rue Aristide Bergès, Z.A. de Pré Millet, Montbonnot-Saint-Martin, 38330 France Ph: +33
More informationNext-Generation Packaging Technology for Space FPGAs
Power Matters. Next-Generation Packaging Technology for Space FPGAs Microsemi Space Forum Russia November 2013 Raymond Kuang Director of Packaging Engineering, SoC Products Group Agenda CCGA (ceramic column
More informationNanoscale Issues in Materials & Manufacturing
Nanoscale Issues in Materials & Manufacturing ENGR 213 Principles of Materials Engineering Module 2: Introduction to Nanoscale Issues Top-down and Bottom-up Approaches for Fabrication Winfried Teizer,
More informationRegents of the University of California
Deep Reactive-Ion Etching (DRIE) DRIE Issues: Etch Rate Variance The Bosch process: Inductively-coupled plasma Etch Rate: 1.5-4 μm/min Two main cycles in the etch: Etch cycle (5-15 s): SF 6 (SF x+ ) etches
More informationThree Approaches for Nanopatterning
Three Approaches for Nanopatterning Lithography allows the design of arbitrary pattern geometry but maybe high cost and low throughput Self-Assembly offers high throughput and low cost but limited selections
More informationAn Investigation on NEG Thick Film for Vacuum packaging of MEMS
An Investigation on NEG Thick Film for Vacuum packaging of MEMS Y.F. Jin* 1,3, Z.P. Wang 1, L. Zhao 2, P.C. Lim 1, J. Wei 1 1) Singapore Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore
More informationCyclic Bend Fatigue Reliability Investigation for Sn-Ag-Cu Solder Joints
Cyclic Bend Fatigue Reliability Investigation for Sn-Ag-Cu Solder Joints F.X. Che* 1, H.L.J. Pang 2, W.H. Zhu 1 and Anthony Y. S. Sun 1 1 United Test & Assembly Center Ltd. (UTAC) Packaging Analysis &
More informationPrediction of Encapsulant Performance Toward Fatigue Properties of Flip Chip Ball Grid Array (FC-BGA) using Accelerated Thermal Cycling (ATC)
Prediction of Encapsulant Performance Toward Fatigue Properties of Flip Chip Ball Grid Array (FC-BGA) using Accelerated Thermal Cycling (ATC) ZAINUDIN KORNAIN 1, AZMAN JALAR 2,3, SHAHRUM ABDULLAH 3, NOWSHAD
More informationImpact of Uneven Solder Thickness on IGBT Substrate Reliability
Impact of Uneven Solder Thickness on IGBT Substrate Reliability Hua Lu a, Chris Bailey a, Liam Mills b a Department of Mathematical Sciences, University of Greenwich 30 Park Row, London, SE10 9LS, UK b
More informationModeling and optimization of noise coupling in TSV-based 3D ICs
LETTER IEICE Electronics Express, Vol.11, No.20, 1 7 Modeling and optimization of noise coupling in TSV-based 3D ICs Yingbo Zhao, Yintang Yang, and Gang Dong a) School of Microelectronics, Xidian University,
More informationThermomigration in Eutectic Tin-Lead Flip Chip Solder Joints
Thermomigration in Eutectic Tin-Lead Flip Chip Solder Joints Dan Yang, M. O. Alam, B. Y. Wu and Y. C. Chan* Department of Electronic Engineering, City University of Hong Kong, Tat Chee Avenue, Kowloon
More informationNon-Damage Probing and Analysis of ILD Damage at Scrub Marks
2004 Southwest Test Workshop Non-Damage Probing and Analysis of ILD Damage at Scrub Marks Jun Yorita, T.Haga, Y.Hirata, S.Shimada* (E-mail : yorita-jun@sei.co.jp) Electronics Materials R&D Laboratories
More informationEDS Mapping. Ian Harvey Fall Practical Electron Microscopy
EDS Mapping Ian Harvey Fall 2008 1 From: Energy Dispersive X-ray Microanalysis, An Introduction Kevex Corp. 1988 Characteristic X-ray generation p.2 1 http://www.small-world.net/efs.htm X-ray generation
More informationNonlinear Time and Temperature Dependent Analysis of the Lead-Free Solder Sealing Ring of a Photonic Switch
Nonlinear Time and Temperature Dependent Analysis of the Lead-Free Solder Sealing Ring of a Photonic Switch J. Lau, Z. Mei, S. Pang, C. Amsden, J. Rayner and S. Pan Agilent Technologies, Inc. 5301 Stevens
More informationThe Increasing Importance of the Thermal Management for Modern Electronic Packages B. Psota 1, I. Szendiuch 1
Ročník 2012 Číslo VI The Increasing Importance of the Thermal Management for Modern Electronic Packages B. Psota 1, I. Szendiuch 1 1 Department of Microelectronics, Faculty of Electrical Engineering and
More informationThe Reliability Analysis and Structure Design for the Fine Pitch Flip Chip BGA Packaging
The Reliability Analysis and Structure Design for the Fine Pitch Flip Chip BGA Packaging Chih-Tang Peng 1, Chang-Ming Liu 1, Ji-Cheng Lin 1, Kuo-Ning Chiang E-Mail: Knchiang@pme.nthu.edu.tw Department
More informationEnhanced performance of microbolometer. using coupled feed horn antenna
Enhanced performance of microbolometer using coupled feed horn antenna Kuntae Kim*,a, Jong-Yeon Park*, Ho-Kwan Kang*, Jong-oh Park*, Sung Moon*, Jung-ho Park a * Korea Institute of Science and Technology,
More informationLecture 0: Introduction
Lecture 0: Introduction Introduction q Integrated circuits: many transistors on one chip q Very Large Scale Integration (VLSI): bucketloads! q Complementary Metal Oxide Semiconductor Fast, cheap, low power
More informationUpdate in Material and Process Technologies for 2.5/3D IC Dr. Rainer Knippelmeyer CTO and VP R&D, SÜSS MicroTec AG
Update in Material and Process Technologies for 2.5/3D IC Dr. Rainer Knippelmeyer CTO and VP R&D, SÜSS MicroTec AG TEMPORARY BONDING / DEBONDING AS THIN WAFER HANDLING SOLUTION FOR 3DIC & INTERPOSERS Device
More informationMechanics of wafer bonding: Effect of clamping
JOURNAL OF APPLIED PHYSICS VOLUME 95, NUMBER 1 1 JANUARY 2004 Mechanics of wafer bonding: Effect of clamping K. T. Turner a) Massachusetts Institute of Technology, Cambridge, Massachusetts 0219 M. D. Thouless
More informationESS 5855 Surface Engineering for. MicroElectroMechanicalechanical Systems. Fall 2010
ESS 5855 Surface Engineering for Microelectromechanical Systems Fall 2010 MicroElectroMechanicalechanical Systems Miniaturized systems with integrated electrical and mechanical components for actuation
More informationFabrication Technology, Part I
EEL5225: Principles of MEMS Transducers (Fall 2004) Fabrication Technology, Part I Agenda: Microfabrication Overview Basic semiconductor devices Materials Key processes Oxidation Thin-film Deposition Reading:
More informationLow-Temperature High-Throughput Assembly Technology for Transducer Array in Medical Imaging Applications
2017 IEEE 67th Electronic Components and Technology Conference Low-Temperature High-Throughput Assembly Technology for Transducer Array in Medical Imaging Applications Hoang-Vu Nguyen, Nu Bich Duyen Do
More informationA Temporary Bonding and Debonding Technology for TSV Fabrication
A Temporary Bonding and Debonding Technology for TSV Fabrication Taku Kawauchi, Masatoshi Shiraishi, Satoshi Okawa, Masahiro Yamamoto Tokyo Electron Ltd, Japan Taku Kawauchi, Tokyo Electron Ltd./Slide
More informationADVANCED BOARD LEVEL MODELING FOR WAFER LEVEL PACKAGES
As originally published in the SMTA Proceedings ADVANCED BOARD LEVEL MODELING FOR WAFER LEVEL PACKAGES Tiao Zhou, Ph.D. Southern Methodist University Dallas, TX, USA tiaoz@smu.edu Zhenxue Han, Ph.D. University
More informationWoon-Seong Kwon Myung-Jin Yim Kyung-Wook Paik
Woon-Seong Kwon e-mail: wskwon@kaist.ac.kr Myung-Jin Yim Kyung-Wook Paik Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology Daejon 305-701, Korea Suk-Jin
More informationDesign of Power Electronics Reliability: A New, Interdisciplinary Approach. M.C. Shaw. September 5, 2002
Design of Power Electronics Reliability: A New, Interdisciplinary Approach M.C. Shaw September 5, 2002 Physics Department California Lutheran University 60 W. Olsen Rd, #3750 Thousand Oaks, CA 91360 (805)
More informationComparative Assessment of the Transient Temperature Response during Single-discharge Machining by Micro-EDM and LIP-MM Processes
Comparative Assessment of the Transient Temperature Response during Single-discharge Machining by Micro-EDM and LIP-MM Processes ICOMM 2014 No. 37 Ishan Saxena #1, Xiaochun Li 2, K. F. Ehmann 1 1 Department
More informationSimulation Analysis of Microchannel Deformation during LTCC Warm Water Isostatic Pressing Process Lang Ping, Zhaohua Wu*
International Conference on Information Sciences, Machinery, Materials and Energy (ICISMME 2015) Simulation Analysis of Microchannel Deformation during LTCC Warm Water Isostatic Pressing Process Lang Ping,
More informationRatcheting deformation in thin film structures
Ratcheting deformation in thin film structures Z. SUO Princeton University Work with MIN HUANG, Rui Huang, Jim Liang, Jean Prevost Princeton University Q. MA, H. Fujimoto, J. He Intel Corporation Interconnect
More informationModal and Harmonic Response Analysis of PBGA and S-N Curve Creation of Solder Joints
Sensors & Transducers 2013 by IFSA http://www.sensorsportal.com Modal and Harmonic Response Analysis of PBGA and S-N Curve Creation of Solder Joints 1 Yu Guo, 1 Kailin Pan, 1, 2 Xin Wang, 1, 2 Tao Lu and
More informationLATEST INSIGHTS IN MATERIAL AND PROCESS TECHNOLOGIES FOR INTERPOSER AND 3D STACKING
LATEST INSIGHTS IN MATERIAL AND PROCESS TECHNOLOGIES FOR INTERPOSER AND 3D STACKING European 3D TSV Summit, January 22-23, 2013, Grenoble Dr. Rainer Knippelmeyer, CTO and VP of R&D, GM Product Line Bonder
More informationFriction and Elongation of Al Electrodes due to Micro-Sliding between the Inner Mo Electrode and the Al Electrodes in High-Power Devices
Materials Transactions, Vol. 43, No. 9 (2002) pp. 2326 to 2330 c 2002 The Japan Institute of Metals EXPRESS REGULAR ARTICLE Friction and Elongation of Al Electrodes due to Micro-Sliding between the Inner
More information1
Process methodologies for temporary thin wafer handling solutions By Justin Furse, Technology Strategist, Brewer Science, Inc. Use of temporary bonding/debonding as part of thin wafer handling processes
More informationLarge-Area and Uniform Surface-Enhanced Raman. Saturation
Supporting Information Large-Area and Uniform Surface-Enhanced Raman Spectroscopy Substrate Optimized by Enhancement Saturation Daejong Yang 1, Hyunjun Cho 2, Sukmo Koo 1, Sagar R. Vaidyanathan 2, Kelly
More informationElectrical Conductive Adhesives with Nanotechnologies
Yi Li Daniel Lu C.P. Wong Electrical Conductive Adhesives with Nanotechnologies Springer 1 Introduction 1 1.1 Electronics Packaging and Interconnect 1 1.2 Interconnection Materials 11 1.2.1 Lead-Free Interconnect
More informationOptimization of Anisotropic Conductive Film Bonding for Improving the Quality of the Image in Vision Inspection
International Journal of Applied Engineering Research ISSN 973-462 Volume 12, Number 24 (217) pp. 199-163 Optimization of Anisotropic Conductive Film Bonding for Improving the Quality of the Image in Vision
More informationAssessment of Soft Errors due to Alpha Emissions from Presolder on Flip Chip Devices Rick Wong, Shi-Jie Wen, Peng Su, Li Li 10/30/09
Assessment of Soft Errors due to Alpha Emissions from Presolder on Flip Chip Devices Rick Wong, Shi-Jie Wen, Peng Su, Li Li 10/30/09 1 Introduction Cause of Soft errors a. Ion creates electron hole pairs
More informationVertically-Integrated Array-Type Miniature Interferometer as a Core Optical Component of a Coherence Tomography System for Tissue Inspection
Vertically-Integrated Array-Type Miniature Interferometer as a Core Optical Component of a Coherence Tomography System for Tissue Inspection Wei-Shan Wang a, Maik Wiemer *a, Joerg Froemel a, Tom Enderlein
More information