450 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 3, MARCH 2017

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1 450 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 3, MARCH 2017 Effects of Thermocompression Bonding Parameters on Cu Pillar/Sn-Ag Microbump Solder Joint Morphology Using Nonconductive Films Hyeong Gi Lee, Ji-Won Shin, Yong-Won Choi, and Kyung-Wook Paik Abstract In this paper, wafer-level preapplied nonconductive films (NCFs) were used to interconnect the Cu pillar/sn-ag microbumps for 3-D through silicon via vertical interconnection. Thermocompression bonding is a common method to interconnect chips to substrates using NCFs, and thermocompression bonding time should be reduced to increase the bonding productivity. Therefore, isothermal bonding method without heating and cooling process in bonding profile was introduced to reduce the bonding time. Solder joints bonded by an isothermal bonding method were compared to those joints bonded by a conventional ramp-up bonding method that was consist of heating, bonding, and cooling process. Final joint gap was decreased using an isothermal bonding method due to higher heating rate, and solder joint morphology was also changed according to the final solder joint gap. Furthermore, solder joint should have enough contact area to substrate metal pads without solder wetting on the Cu pillar sidewall to avoid reliability problems by Sn consumption at the solder joint. Effects of isothermal bonding parameters were investigated in terms of the bonding pressure, temperature, and time to optimize the isothermal bonding parameters for good solder joint. As bonding pressure and bonding temperature increased, solder joint gap decreased because final joint gap was determined by bonding pressures and dynamic viscosity of NCFs. Isothermal bonding times can be reduced to 10 s, because the degree-of-cure of NCFs could be over 90% after 2.2 s. As a summary, solder joint bonded with NCFs using optimized isothermal bonding parameters showed excellent bump joint resistances and solder wetting on substrate metal pads. Index Terms Polymer films, soldering, through-silicon vias. I. INTRODUCTION CONVENTIONAL 2-D electronic packaging technologies have been evolved into the 3-D packaging technology to achieve higher performance and increased package density [1] [3]. Wire bonding interconnection method used in current 3-D package-on-package structure is facing the limitation, as the pitch of chips continuously decreased. Through silicon via (TSV) that forms the vertical path through the chips is one of a solution for various 3-D integration methods. By use of the TSV, electronic package can be further miniaturized, high performing, and multifunctional [4], [5]. As electronic Manuscript received June 20, 2016; revised October 15, 2016; accepted December 13, Date of publication January 17, 2017; date of current version March 14, Recommended for publication by Associate Editor M. Bakir upon evaluation of reviewers comments. The authors are with the Nano Packaging and Interconnect Laboratories, Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon , South Korea ( kwpaik@kaist.ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCPMT Fig. 1. Bonding profiles of the conventional ramp-up and the isothermal bonding method. packaging technology advances, 3-D integration of chips in vertical direction became essential technology and TSV technologies have been studied in many applications such as 3-D NAND, high bandwidth memory, and application processors [6] [11]. Solder interconnection method using Cu pillar/sn bumps has been extensively used as an interconnection method for TSV chip-stacking. Cu pillar/sn bumps formed on a chip are interconnected onto substrate metal pads by a thermocompression bonding method. However, as the pitches of the bumps become finer below 40 μm, many problems occur such as remaining flux residue, void entrapment in underfilll materials due to limitation of capillary flow of underfill materials, and underfill overflow contamination. These problems interrupt the multichip stacking. As a solution for these problems, nonconductive films (NCFs) for TSV chipstacking applications become an effective solution. NCFs are preapplied B-stage-type films that act as void-less underfill, wafer-level applicable adhesive film. Furthermore, NCFs have flux ability [12], [13]. To interconnect a chip on a substrate using preapplied NCFs, conventional ramp-up thermocompression bonding is the most common method. However, conventional ramp-up bonding process takes significant bonding times, in this experiment about 300 s, due to slow heating rate of bonding tool and cooling process shown in Fig. 1. Conventional ramp-up bonding process consists of chip aligning, heating, bonding, IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 LEE et al.: EFFECTS OF THERMOCOMPRESSION BONDING PARAMETERS 451 Fig. 2. (a) Conventional ramp-up bonding. (b) Isothermal thermocompression bonding. (c) Isothermal thermocompression gang bonding with a large bonding tool. and cooling using flip chip bonder as shown in Fig. 1. However, isothermal bonding method using a hot bonding tool is an alternative bonding method for mass-production of preapplied NCF interconnection as shown in Fig. 2. Chip aligning process is normally conducted using a flip chip bonder in both conventional ramp-up and isothermal bonding, but bonding process is performed using a thermocompression bonder with a hot bonding tool. Thermocompression bonders require less precision and cheaper equipment than flip chip bonders. Furthermore, thermocompression bonders can be used as a gang bonder, which interconnect several aligned chips at once using larger bonding tool as shown in Fig. 2(c). By using the thermocompression gang bonder, bonding time and equipment cost are reduced significantly compared to a conventional ramp-up bonding method. To use isothermal bonding method for mass-production, effect of bonding method on solder interconnection should be investigated because heating rate of isothermal bonding method is much higher than conventional ramp-up bonding method. In previous studies, it was reported that the minimum viscosity of NCFs and the time to reach the minimum viscosity decreased as heating rate increased. As a result, final joint gap decreased as heating rate increased, and this relationship is described by 1 h(t) = 4F t 3π R 4 0 (t) t + 1 (1) h 2 0 where h(t) is final joint gap, h 0 is initial joint gap, F is bonding force, R is test vehicle constant, and η(t) is dynamic viscosity [14], [15]. Effects of the isothermal bonding method on solder joint morphology were investigated using the relationship between heating rate and final joint gap because isothermal bonding Fig. 3. (a) Curing and (b) viscous behaviors of NCFs used in this paper. method has higher heating rate than the conventional rampup bonding method. In order to use the isothermal bonding process, solder joints bonded by an isothermal bonding method should be well defined without any Cu pillar sidewall-wetting of solder. Insufficient solder contact area to Cu pad may cause the risk of early solder joint failure during thermal cycling test and Cu pillar sidewall-wetting accelerates Sn consumption at solder resulting in more intermetallic compound (IMC) and Kirkendall voids formation [16], [17]. Therefore, the effects of isothermal bonding parameters on the solder joint morphology should be investigated. II. EXPERIMENTS A. Materials Preparation NCFs were fabricated using epoxy resins, curing agents, and some additives. Flux additive was included in NCFs to remove the native solder oxides during the bonding process. The solution was ball-milled for two days to make a homogeneous resin. The resin was coated on a releasing film as 20-μm-thick film format using a comma roll coater. Fig. 3 shows the curing and viscous behavior of NCFs used in this paper. B. Test Vehicles The test vehicles were designed to measure the Cu pillar/sn-ag microbump joint contact resistance and

3 452 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 3, MARCH 2017 TABLE I ISOTHERMAL BONDING PARAMETERS Fig. 4. Photographs of (a) Cu pillar/sn-ag microbump and (b) Si substrate with Cu/Au pads. electrical stability. 10-μm-height Cu pillar and 10-μmthick Sn-Ag microbumps were electroplated on I/O pads of a wafer. Cu and Au metal pads were also electrodeposited on another Si wafer substrate having the test pattern to measure the contact and daisy chain resistances after bonding of a test chip on a substrate. The top chip with dimensions of 6 6 mm 2 and the substrate Si chip with dimension of mm 2 were used as shown in Fig. 4. The top chip with 80-μm-pitch Cu pillar/sn-ag microbump was used to investigate the effects of bonding method, and the top chip with 60-μm-pitch microbump was also used to optimize the bonding parameters. Daisy chains and single-joint contact resistances were formed in the test vehicle for the electrical evaluation. C. Degree-of-Cure Measurement To measure the degree-of-cure of NCFs, Fourier transform infrared (IR) spectroscopy was used. IR-absorbance peaks were obtained on the surface of the NCFs after bonding. The peak intensity of uncured resins and that of full-cured resin were used to calculate the degree-of-cure of partially cured resins. D. Bonding Profile The chips with preapplied NCFs were bonded using the conventional ramp-up bonding method with the heating rate of 5 C/s and the isothermal bonding method with heating rate of 31 C/s as shown in Fig. 1. In order to investigate the effects of bonding parameters on the solder joint morphology, various bonding pressure, temperature, and time were used. Table I shows the bonding parameters of this paper. Various bonding pressures of 30, 50, and 70 N were used at the target bonding temperature of 250 C for 15 s. Three bonding temperatures of 220 C, 250 C, and 280 C were also used at the fixed Fig. 5. Bonding temperature profiles as a function of (a) bonding temperatures and (b) bonding times. bonding pressure of 50 N to investigate the effect of bonding temperatures on the solder joint morphology. To investigate the effect of bonding times on the solder joint morphology, 10- and 15-s bonding were compared. Fig. 5 shows the actual isothermal bonding profile. III. RESULTS AND DISCUSSION The mechanism of solder joint formation by conventional ramp-up and isothermal bonding processes using NCFs was investigated with cross-sectional images of various temperatures. Fig. 6 shows cross-sectional views of solder joints using NCFs at 40 C, 140 C, 210 C, 230 C, and 250 C during the conventional ramp-up and isothermal bonding processes. At 40 C, solder bump was not contacted to the pad of substrate, and physical contact of solder bumps was observed at 140 C. Fig. 7 shows solder joint gap during the rampup and isothermal bonding processes. Solder joint gap was fixed before solder melting temperature and maintained until the end of the bonding process. In case of conventional rampup bonding method, 38 s were needed to reach the solder melting temperature. However, it takes 6.2 s to melt the solder in isothermal bonding method. The final joint gap of the isothermal bonding method was lower than that of the conventional ramp-up bonding method because final joint gap decreased as the heating rate increased. Fig. 8 shows degreeof-cure of NCF during the bonding processes. Solder joint gap was not further decreased over solder melting temperature, because the degree-of-cure of NCFs reached to almost 90% at the solder melting temperature. By isothermal bonding method using NCFs, stable solder joint was formed with shorter bonding time than conventional ramp-up bonding method. Fig. 9 shows the cross-sectional images of solder joints bonded with NCFs at the bonding pressure of 30, 50, and 70 N.

4 LEE et al.: EFFECTS OF THERMOCOMPRESSION BONDING PARAMETERS 453 Fig. 8. Degree-of-cure of NCFs during the conventional ramp-up bonding and isothermal bonding methods. Fig. 9. Cross-sectional views of solder joint bonded using the isothermal bonding method at 250 C for 15 s at the bonding pressures of (a) 30, (b) 50, and (c) 70 N. Fig. 6. Cross-sectional views of solder joints using a conventional rampup bonding method at (a) 40 C, (b) 140 C, (d) 210 C, (f) 230 C, and (h) 250 C after bonding and isothermal bonding method at (c) 140 C, (e) 210 C, (g) 230 C, and (i) 250 C after bonding. Fig. 10. Joint resistances and joint gaps of solder joint bonded using the isothermal bonding method at 250 C for 15 s at the bonding pressure of 30, 50,and70N. Fig. 7. Solder joint gap during the conventional ramp-up bonding and isothermal bonding methods. The isothermal bonding with a bonding temperature of 250 C was performed for 15 s. At the bonding pressure of 30 N, solder joint showed unstable contact to pad. However, the solder joints bonded at the bonding pressure of 50 and 70 N showed good wetting on pads. Fig. 10 shows the joint contact resistance and joint gap of solder joints using NCFs bonded at the bonding pressure of 30, 50, and 70 N by isothermal bonding method. Solder joints bonded at the bonding pressures of 50 and 70 N showed stable joint contact resistance of 4 m. The joint gap decreased as bonding pressures increased as Fig. 11. Cross-sectional views of solder joint bonded with NCFs at the bonding temperatures of (a) 220 C, (b) 250 C, and (c) 280 C. shown in (1) [14]. In terms of bonding pressure, solder joint bonded with NCFs at the bonding pressure of 50 N showed excellent electrical resistance and the well-defined solder wetting area. Fig. 11 shows the cross-sectional images of solder joints bonded with NCFs at the bonding temperatures of 220 C, 250 C, and 280 C. The joint contact resistances and joint gaps of solder joints using NCFs bonded at the bonding

5 454 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 3, MARCH 2017 Fig. 12. Joint contact resistances and joint gaps of solder joint bonded with NCFs at the bonding temperatures of 220 C, 250 C, and 280 C. Fig. 14. Joint resistances and joint gaps of solder joint bonded with NCFs at the bonding time of 10 and 15 s. time of 10 and 15 s showed stable joint contact resistance of 4 m and the same joint gap. Solder joints were almost same regardless of the isothermal bonding time because the degree-of-cure of NCFs exceeded 90% using an isothermal bonding method within 2.2 s. Fig. 13. Cross-sectional views of solder joint bonded with NCFs at the bonding times of (a) 10 and (b) 15 s. TABLE II HEATING RATE OF BONDING PROFILES OF 220 C, 250 C, AND 280 C temperatures of 220 C, 250 C, and 280 C by the isothermal bonding method were shown in Fig. 12. The solder joint bonded at the bonding temperature of 220 C formed small contact area to substrate pad and showed higher joint contact resistance than other bonding temperatures. The joint gap decreased as the bonding temperature increased because heating rate from the room temperature to the solder melting temperature increased as target bonding temperatures increased. The heating rates of isothermal bonding profiles of 220 C, 250 C, and 280 C are shown in Table II. In previous research, after the solder joint formation is completed, the thickness of the IMCs is highly dependent on the target bonding temperatures at the same bonding time [18]. As a result, the bonding temperature was optimized as the lower temperature of 250 C in terms of electrical bump contact resistance and solder joint morphology. Fig. 13 shows the cross-sectional images of solder joint bonded with NCFs at the isothermal bonding time of 10 and 15 s. In the case of joint resistances as shown in Fig. 14, solder joints bonded at the isothermal bonding IV. CONCLUSION In this paper, effects of bonding parameters on the Cu pillar/sn-ag microbumps solder joint morphology were investigated. Reducing the thermocompression bonding time is needed because the bonding time is closely related to bonding productivity. Conventional ramp-up bonding and isothermal bonding methods were compared in terms of bonding times and solder joint morphologies. Solder joint gaps of NCFs were maintained after physical contact of solder due to high degreeof-cure of NCFs at the solder melting temperature. Using an isothermal bonding method, good solder joint morphology can be obtained with reduced thermocompression bonding time. The effects of the isothermal bonding parameters were also investigated in terms of the bonding pressure, bonding temperature, and bonding time. As bonding pressures and temperatures increased, joint gaps decreased. The solder contact area to pad increased because the final joint gap was directly related to bonding pressures and dynamic viscosities. Bonding time using NCFs can be reduced to 10 s because the degreeof-cure of NCF exceeded 90% using an isothermal bonding method within 2.2 s. As a result, the solder joint bonded with NCFs using an isothermal bonding method at the bonding temperature of 250 C and bonding pressure of 50 N for 10 s showed good electrical property and solder wetting on substrate pads. REFERENCES [1] D. Choudhury, 3D integration technologies for emerging microsystems, in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp [2] P. Garrou, C. Bower, and P. Ramm, Handbook of 3D Integration Technology and Applications of 3D Integrated Circuits, vol. 1, [3] H. J. Lau, Overview and outlook of through-silicon via (TSV) and 3D integrations, Microelectron. Int., vol. 28, no. 2, pp. 8 22, 2001.

6 LEE et al.: EFFECTS OF THERMOCOMPRESSION BONDING PARAMETERS 455 [4] S. W. Yoon, D. W. Yang, J. H. Koo, M. Padmanathan, and F. Carson, 3D TSV processes and its assembly/packaging technology, in Proc. IEEE Int. Conf. 3D Syst. Integr. (3DIC), San Francisco, CA, USA, Sep. 2009, pp [5] M. Sadaka, I. Radu, and L. D. Cioccio, 3D integration: Advantages, enabling technologies & applications, in Proc. IEEE Int. Conf. Integr. Circuit Design Technol., Grenoble, France, Jun. 2010, pp [6] C.-Y. Lu, Future prospects of NAND flash memory technology The evolution from floating gate to charge trapping to 3D stacking, J. Nanosci. Nanotechnol., vol. 12, no. 10, pp , [7] K. Parat and C. Dennison, A floating gate based 3D NAND technology with CMOS under array, in Proc. IEEE Int. Electron Devices Meeting (IEDM), Washington, DC, USA, Dec. 2015, pp [8] K.-T. Park et al., Three-dimensional 128 Gb MLC vertical nand flash memory with 24-WL stacked layers and 50 MB/s highspeed programming, IEEE J. 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Paik, Wafer-level packages using B-stage nonconductive films for Cu pillar/sn Ag microbump interconnection, IEEE Trans. Compon., Packag., Manuf. Technol., vol. 5, no. 11, pp , Nov [14] J.-W. Shin, Y. S. Kim, H. G. Lee, U. B. Kang, S. K. Seo, and K.- W. Paik, Effects of thermo-compression bonding parameters on joint formation of micro-bumps in non-conductive film (NCF), in Proc. 65th IEEE Electron. Compon. Technol. Conf., May 2015, pp [15] A. Taluy et al., Wafer level underfill entrapment in solder joint during thermocompression: Simulation and experimental validation, in Proc. 63rd IEEE Electron. Compon. Technol. Conf., May 2013, pp [16] Z. Mei, M. Ahmad, M. Hu, and G. Ramakrishna, Kirkendall voids at Cu/solder interface and their effects on solder joint reliability, in Proc. 55th Electron. Conf. Technol. Conf., Jun. 2005, pp [17] K. Zeng, R. Stierman, T.-C. Chiu, D. Edwards, K. Ano, and K. N. Tu, Kirkendall void formation in eutectic SnPb solder joints on bare Cu and its effect on joint reliability, J. Appl. Phys., vol. 97, no. 2, pp , [18] S.-T. Lu, J.-Y. Juang, H.-C. Cheng, Y.-M. Tsai, T.-H. Chen, and W.-H. Chen, Effects of bonding parameters on the reliability of finepitch Cu/Ni/SnAg micro-bump chip-to-chip interconnection for threedimensional chip stacking, IEEE Trans. Device Mater. Rel., vol. 12, no. 2, pp , Jun Hyeong Gi Lee received the B.Sc. and M.Sc. degrees in materials science and engineering from the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2009 and 2011, respectively, where he is currently pursuing the Ph.D. degree in materials science and engineering. His current research interests include nonconductive films for bump interconnection. Ji-Won Shin received the B.Sc., M.Sc., and Ph.D. degrees from the Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2008, 2010, and 2015, respectively. His current research interests include study on nonconductive film for fine-pitch Cu-pillar/Sn-Ag bump interconnection. Yong-Won Choi received the B.Sc., M.Sc., and Ph.D. degrees from the Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2007, 2009, and 2014, respectively. His research topics were developing hybrid interconnection for 3-D-through silicon via using nonconductive adhesives and Cu/Sn double bump. His current research interests include developing advanced packaging technologies. Kyung-Wook Paik received the B.Sc. degree in metallurgical engineering from Seoul National University, Seoul, South Korea, in 1979, the M.Sc. degree from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1981, and the Ph.D. degree in materials science and engineering from Cornell University, Ithaca, NY, USA, in He was a Research Scientist at KAIST from 1982 to 1985, and was involved in the development of gold bonding wires. He was a Senior Technical Staff Member of the Interconnect Multichip Module Technology and Power IC Packaging, General Electric Corporate Research and Development, Brookline, MA, USA, from 1989 to He rejoined the Department of Materials Science and Engineering, KAIST, as a Professor in 1995, where he is currently with the Nanopackaging and Interconnect Laboratory, and is involved in flip-chip bumping and assembly, adhesive flip-chips, embedded capacitors, and display packaging technologies. He was a Visiting Professor with the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA, from 1999 to 2000, where he was involved in packaging education and integrated passives research programs. He joined Portland State University, Portland, OR, USA, in 2005, and was involved in flip-chip polymer materials evaluation. He has authored or coauthored over 80 technical papers, and holds 16 U.S. patents and four U.S. patents pending. Dr. Paik has been the Chairman of the Korean IEEE Components, Packaging and Manufacturing Technology Chapter since 1995 and is a member of the International Microelectronics and Packaging Society, SEMI, and MRS.