Multi-chip Integration on a PLC Platform for 16X16 Port Optical Switch Using Passive Alignment Technique

Transcription

1 Multi-chip Integration on a PLC Platform for 16X16 Port Optical Switch Using Passive Alignment Technique Jung Woon Lim, Hwe Jong Kim, Seon Hoon Kim and Byung Sup Rho Korea Photonics Technology Institute , Wolchul-dong, Buk-gu, Gwangju, Korea jungwoon@kopti.re.kr, Tel: , Fax: Abstract We propose simple assembly techniques capable of performing high density multi-chip integration on a PLC platform with eutectic AuSn solder bumps, for 16x16 port SOA gate switch composed 2x2 optical switch SOA array chips using passive alignment technique. Conventional methods have used chip-by-chip bonding method. These methods are found it is difficult to obtain high bonding strength because the solder interconnections remelt during repeated bonding steps. To overcome this problem, we investigated the single re-flow processes and optimized the bonding condition for non re-flow process on minimum AuSn solder bump spreading. Also, die shear tests were conducted to evaluate mechanical reliability between the solder bump and the chip pads. Introduction Optical switches have been a major area of interest since the advent of optical communication systems. There are several different types of optical switches. Among them, semiconductor optical amplifiers (SOA) used as optical gate switches are of great interest due to their fast switching, high extinction ratio over a wide wavelength range and the ability to compensate optical losses. There were many reports on optical switches using SOA chips flip-chip-bonded on PLC platforms. The focuses of these reports were on integration fabrication, module performance, and system demonstration. [1-5] In order to produce large quantities of SOA gate switch modules at low cost, planar lightwave circuit (PLC) platforms were extensively studied. These efforts have been made to increase the number of channels or chips and reduce the platform size. The integration of multi-channel or multi-chips on a PLC platform makes optical components highly functional and cost-effective. The integration technique of optical active devices on PLC has been developed recently because it leads a compact module size, thereby achieving cost reduction. Passive alignment techniques such as flip-chip bonding have many advantages for integration using PLC platform, compared to active alignment techniques as faster assembly time and the smaller assembled module size. Furthermore, it is impractical to integrate all the optical multi-chips on PLC platform using active alignment techniques. Therefore flip-chip bonding techniques have been used in multi-chip gate switch packaging due to high bonding accuracy, shortest electrodes and superior thermal conductivity. In order to use SOA chips as optical gate switches, numerous assembly techniques were developed, enabling a large number of SOA chips to be bonded on a single PLC platform. However, the PLC were repeatedly heated and the solder surfaces were oxidized during the remelting, degrading the final bonding strength. A solution was suggested that a single re-flow process should be carried out after aligning multiple chips on a PLC platform. However, there was a possibility of misalignment during the reflow. Therefore several remedies were suggested such as optimizing solder composition or the size of the solder patterns. We used two assembly methods capable of performing high density multi-chip integration on a PLC platform for 16x16 port SOA gate switch composed eight sets of 2x2 optical switch array chips using a flip-chip bonding as the passive alignment technique. A total of 32 SOA chips are required to develop 16x16 port SOA gate switch module and the effective multi-chip bonding techniques, which allow to bond eight sets of four channel SOA array chips, are dependent upon the important factors such as bond temperature, bond time, and bond force. In order to overcome these problems, we studied the bond temperature, bond time, and bond force to find the optimum bonding condition. Using these conditions, we integrated the eight SOA array chips on a platform, and then investigated the degree of solder reaction and the bonding strength. Structure of SOA optical switch and PLC platform The structure for the 2x2 SOA optical switch is shown in Fig.1. Four channel SOA array chips were bonded on a quartz-based planar lightwave circuit (PLC) platform using passive alignment flip-chip bonding. A 4-channel SOA array chip is traversed for any branch of the switch. Thus, this single SOA array chip is used for gating as well as amplifying the signal to compensate the losses within the switch module. Fig. 1. Schematic top view of 2x2 SOA optical switch Fig. 2 shows the configuration of 16x16 port optical switch on a PLC platform composed eight sets of 2x2 optical switch array chips. The platform is an integrated optical and electrical circuit board which includes embedded type optical waveguides, electrical signal paths, and electrical wiring /06/$ IEEE Electronic Components and Technology Conference

2 Fig. 2. Configuration of multi-chip integration on a PLC platform of 6µmx6µm were formed using PECVD and a wet etching is carried out to make the electrodes and SOA bonding areas. After a surface cleaning process, Au electrodes and Ti/Ni/Au under bump metallurgy (UBM) layers were patterned on the substrate. A negative photoresist was used for the metal line patterning while a positive photoresist was used for solder bumps. The UBM of Ti/Ni/Au was fabricated using evaporation and lift-off. On the metal lines, solder bumps were patterned using a positive photoresist and the stripe-type AuSn solder bumps were formed by evaporating alternating layers Au and Sn. Using these procedures, the PLC platform with electrode and AuSn solder bump was fabricated as shown in Fig. 4. Fig. 3 shows the cross section of the PLC platform and the 4-channel SOA array chips. On the PLC platform, Au electrodes and stripe type AuSn (Au 80 wt.%, Sn 20 wt.%) solder bump of 2.4µm thick were made. A 4-channel SOA array chip was aligned on each channel and heat is applied to complete the bonding. The AuSn solder bump height and the Au electrode height were determined to optimize the optical align accuracy between the SOA active core and the optical waveguide. Also the PLC platform was designed considering the thickness tolerance of the wafers. Fig. 4. PLC platform with electrode (metal line) and AuSn solder bump Fig. 3. Cross section of PLC platform and SOA chip AuSn solder bump and electrode on platform PLC platform for vertical alignment. A simulation was carried out on optical coupling loss with respect to the bonding accuracy of the SOA chips on the PLC platform. The index contrast of channel waveguide of 0.75% was used. And the core and clad index values at 1550nm was and respectably. The core size and waveguide channel spacing were 6µmx6µm and 250µm respectively. It was confirmed that the bonding accuracy greatly affects the coupling loss. In order to keep the coupling loss within 1dB, the bonding accuracy should be less than ±1µm. Fabrication of planar lightwave circuit (PLC) platform A 4-inch quartz substrate is used to fabricate the PLC platform for multi-chip bonding. Waveguides with a core size Methodology of multi-chip passive alignment assembly To perform the multi-chip integration on a quartz based PLC platform with AuSn stripe-type solder bumps formed by under bump metallurgy (UBM), we adopted two flip-chip assembly techniques: a two-step assembly method and a onestep assembly method. The first half of the two-step flip-chip assembly method is a chip-by-chip alignment step. The second half is a simultaneous solder re-flowing step.[7-8] On the other hand, the one-step assembly method has only a single thermal compression step without the re-flow. In the thermal compression step, the SOA chips are heated up to the solder melting temperature with necessary pressure, and then all the chips are bonded during chip-by-chip bonding step. The bonding temperature affects the bonding quality greatly. Therefore, the reaction of AuSn solder bumps was studied with respect to bonding temperature. The solder did not react at 270 ; it started to melt at 280. At 300, the solder spreading occurred. In order to protect adjacent solder, the pre-bonding temperature should not exceed 280. The dummy glass chips of the same size as the actual SOA array chip were used in the test to search the optimum flipchip bonding condition and measure the bonding accuracy and the bonding quality. The align mark matching between the dummy glass chip and the substrates was easily measured using an optical microscope. The AuSn solder spreading could be studied at the same time. The dummy specimens were also used in the die shear test to measure the bonding strength Electronic Components and Technology Conference

3 The main disadvantage of the two-step assembly method is the lateral shift during re-flow step, thereby degrading the bonding accuracy. It is also difficult to control the bonding accuracy due to the self align tendency of the solder. To circumvent these problems, we propose a one-step assembly method using thermal compression. Individual chips are placed on their designated positions and temperature and an external force are applied simultaneously. The resulting bonded area is larger, giving rise to a superior bonding strength. And this method remarkably reduces the tack-time because they are bonded without the re-flow process. Fig. 5 explains the multi-chip integrated procedure using the two methods. The two-step assembly method consists of a pre-bonding step and a simultaneous re-flow step. In the pre-bonding step, the PLC platform is set on a heater block and heated up to alignment temperature (T1) with pressure, which is below the solder melting temperature (T3). And then in the re-flow step, the PLC platform is heated up to the solder re-flow temperature (T2) without pressure, and the eight SOA array chips are bonded at the same time. The one-step assembly method has only a thermal compression step without the solder re-flow step. In the bonding step, the SOA chip is heated up to the solder melting temperature (T3) with a necessary pressure, but the PLC platform is heated below the melting temperature (T3), and then all the chips are bonded during chip-by-chip bonding step. compression step should not affect the near AuSn stripe-type solder bump. It was possible to optimize the one-step assembly bonding condition using a design of experiment (DOE) taking bonding temperature, bond pressure and bond time into account. Using the optimum condition, 16x16 port optical switch composed 2x2 SOA Switch arrays were fabricated as shown in Fig. 6. Fig x16 port optical switch composed eight sets of 2x2 SOA switch array chips The bonding uniformity of the two-step assembly was studied in Fig. 7 and Fig. 8. The eight sets of SOA array chip were flip-chip-bonded on a single PLC using the two-step method and the bonding interfaces were observed using SEM. Since this technique uses no external force during re-flow step, the SOA chips were pushed out further from the PLC surface. It was found that the chip height increased about 2~4µm after the re-flow step. The lateral shift during re-flow was prevented by using thin solder bumps of 2~3µm. Fig. 5. Multi-chip integrated procedure multi-chip bonding procedure using one-step assembly method. using two-step assembly method. Results of multi-chip passive alignment assembly The most important aspect when developing 16x16 SOA switch array was that the 8 bonded SOA arrays on the PLC should have the uniform bonding properties. For excellent uniformity during the one-step assembly method, the thermal Fig. 7. SEM plan view before and after re-flow before re-flow step after re-flow step Electronic Components and Technology Conference

4 The bonding uniformity is the most important when eight SOA chips are flip-chip-bonded to a single PLC platform. To measure this, die shear tests were performed as shown in Fig. 10. The shear force was applied along the solder stripe direction. Fig. 10. Configuration of die shear test Fig. 8. SEM cross-sections before and after re-flow before re-flow step after re-flow step The Fig. 9 is the cross-sectional SEM micrograph of a SOA chip bonded on a PLC using the one-step assembly. This method carries out the pre-bonding step and the re-flow step simultaneously. The solder melting time is constant and a constant force is applied to the individual SOA chips. Therefore the SOA chips were bonded closer to the PLC surface. And due to the applied force, a lateral solder spreading was observed. But the size of solder spreading is minimized using optimum bonding condition. As can be seen in Fig. 11, the average bonding strength of the one-step assembly method was about 60gf higher than that of the two-step assembly. However, the standard deviation was greater, indicating lower die shear uniformity. Fig. 9. After one-step assembly cross-sectional planar Fig. 11. Results of bonding strength histogram of one-step assembly histogram of two-step assembly. Conclusions We propose two assembly techniques using passive alignment to perform high density multi-chip integration on a PLC platform. 16x16 port SOA gate switches composed eight sets of 2x2 optical switch SOA array chips were realized. First, two-step assembly method consists of a chip-by-chip pre-bonding step and a simultaneous single re-flow step. The align marks between the chip and the PLC platform surface are matched and the assembly were pre-bonded below the melting temperature of the AuSn solder. The subsequent reflow step brings the bonding temperature above the melting temperature applying no external pressure. Second, one-step assembly method employs only thermal compression bonding Electronic Components and Technology Conference

5 between the AuSn solder bump on a PLC platform and multichips without the re-flow step. The one-step assembly has the advantage of higher bonding strength. In addition, the bonding height can be set at will. But the bonding uniformity is inferior. However, the thermal compression effectively eliminated the possibility of the misalignment occurring during the re-flow of the two-step assembly. Therefore, it is more suitable technique for high accurate bonding of optical components on PLC platforms. Acknowledgments This work was supported by the national program as on of the Regional Specialization Technology Development Business funded by Korea Ministry of Commerce, Industry and Energy(MOCIE). References [1] R. S. Fan and R. B. Hooker, Hybrid optical switch using passive polymer waveguides and semiconductor optical amplifiers, J. Lightwave Technol., vol. 18, no. 4, (2000), pp [2] R. Sato, T. Ito, K. Magari, T. Inoue, R. Kashara, M. Okamoto, Y. Tohmori, and Y. Suzuki, 10-Gb/s lowinput-power SOA-PLC hybrid integrated wavelength converter and its 8-slot unit, J. Lightwave Technol., vol. 22, no. 5, (2004), pp [3] I. Armstrong, I. Andonovic, A. E. Kelly, S. Bonthron, J. Bebbington, C. Mchie, C. Tmobling, S. Fasham, and W. Johnstone, Hybridization platform assembly and demonstration of all-optical wavelength conversion at 10 Gb/s, J. Lightwave Technol., vol. 23, no. 5 (2005) pp [4] Y. Yamada, H. Terui, Y. Ohmori, M. Yamada, A. Himero, and M. Kobayashi, Hybrid-integrated 4 4 optical gate matrix switch using silica-based waveguide and LD array chips, J. Lightwave Technol.,, vol. 10, no. 3, (1992) pp [5] I. Ito, I. Ogawa, N. Yoshimoto, F. Ebisawa, K. Magari, K. Shuto, Y. Kawaguchi, M. Yanagisawa, O. Mitomi, F. Hanawa, Y. Tohmori, Y. Yamada, Y. Yoshikuni, and Y, Hasumi, Ultra-wide-band high-speed wavelength selector using a hybrid integrated gate module: a 4-channel SS- SOA gate array on PLC platform, ECOC 97, (1997) pp [6] T. Hashimoto, Y. Nakasuga, Y. Yamada, H. Terui, M. Yanagisawa, Y. Akahori, Y. Tohmori, K. Kato, and Y. Suzuki, Multichip optical hybrid integration technique with planar lightwave circuit platform, J. Lightwave Technol., vol. 17, no. 7, (1998), pp [7] Y. Nakasuga, T. Hashimoto, Y. Yamada, H. Terui, M. Yanagisawa, K. Moriwaki, Y. Akahori, Y. Tohmori, K. Kato, S. Sekine, and M. Horiguchi., Multi-chip hybrid integration on PLC platform using passive alignment technique, Electronic Components and Technology Conference 1996, (1996) pp [8] J. Sasaki, M. Itoh, T. Tamanuki, H. Hatakeyama, S. Kitamura, T. Shimode, and T. Kato, Multiple-chip precise self-aligned assembly for hybrid integrated optical modules using Au-Sn solder bumps, IEEE Transaction on advanced packaging, vol. 24, no. 4 (2001) pp Electronic Components and Technology Conference