MP112D GHz GaAs MMIC Attenuator. Datasheet
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1 MP112D GHz GaAs MMIC Attenuator Datasheet
2 MP112D GHz GaAs MMIC Attenuator MAIN FEATURES Operating range 0.1 to 15 GHz Insertion loss 4.5 db at 10 GHz Attenuation range 31.5 db (6 bit, 64 states, 0.5 db step) Parallel Data Input 100% On-Wafer DC and RF Tested 100% Visual Inspection to MIL-STD-883 Method 2010 Chip size 2500x1250 µm², thickness 100 µm ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage for Digital Control Control Voltages RF Input Power Operating Temperature Storage Temperature Value -6 V to -9 V 0 to +5.5 V TBD -40 to +85 C -55 to +125 C GENERAL DESCRIPTION The MP112D is a high performance GaAs MMIC 6-bit digital attenuator which covers the frequency range 0.1 to 15 GHz and can be used in Telecommunication, Instrumentation and Radar applications. The on-chip digital control logic allows for parallel data input. This chip is manufactured using 0.18 μm gate length phemt process. The MMIC uses gold bond pads and backside metallization and is fully protected with Silicon Nitride passivation to obtain the highest level of reliability. ELECTRICAL CHARACTERISTICS (AMBIENT TEMPERATURE T = 25 C) Symbol Parameter Min. Typ. Max. Unit ΔF Frequency Range GHz IL Insertion Loss 6.5 db S11 Input Return Loss 10 db S22 Output Return Loss 9 db P1dB Input Power at 1 db Compression Point 16 dbm Δ_ATT Attenuator Range (6 bit, 64 states, 0.5 db step) 31.5 Deg RMS_ATT RMS Amplitude Error 0.2 db RMS_PhS RMS Phase Error 2.5 Deg VSS Supply Voltage for Digital Control Logic -7.5 VDC VLH Control Voltage High (V A1,2,3,4,5,6 ) VDC VLL Control Voltage Low (V A1,2,3,4,5,6 ) VDC I_VSS DC Current for Digital Control (VSS=-7.5V) 10 ma 02 MP112D Revision Specifications subject to change without notice.
3 ON-WAFER MEASUREMENTS AT T = 25 C (TYPICAL) 03 MP112D Revision Specifications subject to change without notice.
4 ON-WAFER MEASUREMENTS AT T = 85 C (TYPICAL) Input power level for characterization is -5 dbm. 04 MP112D Revision Specifications subject to change without notice.
5 ATTENUATOR FUNCTIONAL DIAGRAM MECHANICAL DATA Chip size = 2500x1250 µm² (before wafer dicing), thickness = 100 µm; Bond pad dimensions are shown to a centre of a bond pad. Bond pad / Backside metallization: Gold; RF, DC and control pads (1, 2 and 4 to 12) are 100x100 µm²; A GND pad (3) is 100x150 µm². BOND PAD DESIGNATIONS Pad number Pad ID DC Voltage (V) Description 1 RF port #1 2 RF port #2 3 GND Decoupling ground 4 A6 0 / +3.3 Control of 16.0 db attenuator bit 5 A5 0 / +3.3 Control of 8.0 db attenuator bit 6 A4 0 / +3.3 Control of 4.0 db attenuator bit 7 VSS -7.5 Supply of digital control logic 8 A3 0 / +3.3 Control of 2.0 db attenuator bit 9 A2 0 / +3.3 Control of 1.0 db attenuator bit 10 A1 0 / +3.3 Control of 0.5 db attenuator bit 11 BIAS Reference voltage for bias generator of digital control logic (1,2) 12 REF Reference voltage for digital control logic (1,2) 13 VQ Monitor of the output voltage of the control logic (1) (1) This pad is NOT used in typical conditions; (2) It s possible to use an external voltage divider in addition to integrated circuit. 05 MP112D Revision Specifications subject to change without notice.
6 ATTENUATOR CONTROL TABLE State number Attenuation Voltage to apply on the control pads (db) A6 A5 A4 A3 A2 A1 0 (REF) «0» is control voltage low and «1» is control voltage high. 06 MP112D Revision Specifications subject to change without notice.
7 ATTENUATOR CONTROL TABLE State number Attenuation Voltage to apply on the control pads (db) A6 A5 A4 A3 A2 A «0» is control voltage low and «1» is control voltage high. ORDERING INFORMATION Part Number Package Type Version Description MP112D Bare Die GHz Attenuator APPLICATION NOTES Wire Bonding A recommendation for RF pads (1 and 2) is one wire: diameter 25 µm, length 450 µm. A recommendation for DC and control pads (3 to 10) is one wire: diameter 25 µm, length µm. Bias Arrangement The pad #7 (VSS) needs to have DC bypass capacitance of 100 pf as close to the device as possible. Attenuator Control Bias Digital control logic is integrated in the device to supply the necessary internal switching voltages for the attenuator s cells. The reference state is enabled with logic low (0V) on control pads of the attenuator (4 to 6 and 8 to 10). The binary weighted attenuation states are switched by applying logic high on the respective control pad. A control table for the attenuator is presented below. Recommended ESD Management This device is susceptible to electrostatic and mechanical damage. Dice are supplied in antistatic containers, which should be opened in cleanroom conditions at an appropriately grounded antistatic workstation. Devices need careful handling using correctly designed collets, vacuum pickups or, with care, sharp tweezers. 07 MP112D Revision Specifications subject to change without notice.
8 Micran, Research & Production Company 51d Kirova Avenue, Tomsk, Russia, phone: fax: This information is subject to change without notice. Published in Russia, April 5, 2016 MICRAN JSC
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