Self-Alignment with Copper Pillars Micro-Bumps for Positioning Optical Devices at Submicronic Accuracy

Transcription

1 2017 IEEE 67th Electronic Components and Technology Conference Self-Alignment with Copper Pillars Micro-Bumps for Positioning Optical Devices at Submicronic Accuracy Yézouma D. Zonou, Stéphane Bernabé, Daivid Fowler, Mireille Francou, Olivier Castany Université Grenoble Alpes, CEA, LETI, MINATEC campus, CEA-Grenoble, 17 rue des martyrs, F Grenoble, France yezouma-dieudonne.zonou@cea.frauthors Philippe Arguel CNRS, LAAS, 7 avenue du colonel Roche, F Toulouse, France Université de Toulouse, UPS, LAAS, F Toulouse, France Abstract This paper studies the self-alignment properties between two chips that are stacked on top of each other with copper pillars micro-bumps. The chips feature alignment marks used for measuring the resulting offset after assembly. The accuracy of the alignment is found to be better than 0.5 μm in x and y directions, depending on the process. The chips also feature waveguides and vertical grating couplers (VGC) fabricated in the front-end-of-line (FEOL) and organized in order to realize an optical interconnection between the chips. The coupling of light between the chips is measured and compared to numerical simulation. This high accuracy selfalignment was obtained after studying the impact of flux and fluxless treatments on the wetting of the pads and the successful assembly yield. The composition of the bump surface was analyzed with Time-of-Flight Secondary Ions Mass Spectroscopy (ToF-SIMS) in order to understand the impact of each treatment. This study confirms that copper pillars microbumps can be used to self-align photonic integrated circuits (PIC) with another die (for example a microlens array) in order to achieve high throughput alignment of optical fiber to the PIC. Keywords- Self alignment, Copper pillars, Micro-bumps, Selfpositioning, Optical coupling, Silicon Photonics I. INTRODUCTION Packaging of optoelectronic devices is a major contribution to the module cost (up to 80%) [1]. This is mainly due to the active alignment process between single-mode devices, which requires high alignment precision in the micrometer range and is a unitary and time consuming process. Different methods of passive alignment were studied in order to reduce manufacturing cost, while enabling the assembly of complex optical devices. In this context, a promising solution is the approach based on the self-alignment effect of solder bumps during the melting stage. This solution has the advantage to allow batch assembly process and is compatible with existing manufacturing equipment, which reduces the cost of the packaging. In the past years, several works studied the accuracy of self-alignment with In, PbSn, AuSn, or Sn solder balls and exhibited a good positioning accuracy (< 1 μm) [1][2][3]. In the meantime, the need for increased interconnections density, thinner profile, and improved electrical and thermal performances led to the industrial adoption of copper pillar bumps with Sn solder for flip-chip stacking. It is therefore an important work to develop a self-alignment process with copper pillars bumps and to study the achievable accuracy. One key aspect of chip assembly with eutectic solder is the good wettability of the bump solder on the under bump metallization (UBM) pads. Conventional process uses liquid flux, which is not perfectly suitable for optical applications because residues are left by the flux and can alter optical transmission. To prevent this problem, fluxless approaches were developed. The first approach uses a reducing gas atmosphere in order to remove the tin oxide layer. Formic acid vapor (HCOOH) is commonly used for that purpose, but the process is known to be delicate with tin solder [4] and requires process optimization or additional treatment like vacuum ultra violet [5]. Other gas can be used but are less common, like Ar/H2 plasma [6]. The second approach is to cap the tin bumps with a non-oxidizing material like chromium in order to protect tin from oxygen [7]. In this work, we will study three types of processes: reflow with liquid flux, reflow with formic acid vapor, and a pre-treatment with liquid flux before reflow. The influence of the treatment on the surface of the bumps will be analyzed with ToF-SIMS. The assembly of chips with solder bumps can provide selfalignment effect due to the capillary forces of the solder during the melting phase. We investigate the precision of the self-alignment depending on the surface treatment, the Sn bump height, and the initial offset before reflow, by reading a Vernier scale on the assembled chips. In section VI, we present some experiments done on assembled chips, both featuring embedded optical waveguides and coupling structures that realize an optical interconnection between them. This configuration, is useful for Optical Proximity Communications [2], which is a /17 $ IEEE DOI /ECTC

2 preliminary assessment for further experiments involving self-assembly of micro-optics on the top of a Silicon Photonics Chip, as described in [8]. II. TEST VEHICLE We designed and processed silicon photonic chips including buried silicon waveguides and grating couplers in the front-end-of-line (FEOL). We used 200-mm-diameter SOI wafers with 2- m-thick buried oxide and 300-nm-thick silicon layer. The waveguide geometry is a rib with 400-nm-wide ridge and 150-nm-thick slab. We designed two types of structures corresponding to top and bottom chips intended to be flip-chipped the one on top of the other (Figure 1). These two structures are processed on the same wafers, followed by back-end-of-line (BEOL) processing with either copper pillar micro-bumps or UBM. The top chips are diced from the wafers with copper pillars and the bottom chips are diced from the wafers with UBM pads. Dimensions of top and bottom chips are 3.8 x 2.0 mm and 3.8 x 10.0 mm respectively. For light coupling evaluation, the top chips is designed to act as a bridge for light transmission (see Figure 6). The optical interconnect between the top and bottom chip is made with vertical grating couplers (VGC). registration accuracy better than 0.1 μm. Particular attention was payed to ensure that the overlay between the fabricated levels was indeed bounded by this tolerance value. Since our aim is to measure the alignment precision between the two chips after stacking, it is necessary to see through the silicon chips, which requires the backside of the wafers to be polished. Inspection is done with a microscope and a CMOS image sensor camera that makes it possible to observe wavelength up to 1.1 μm. Due to the reduced resolution of infrared imaging, our precision when reading the misalignment is limited to 0.5 μm. The measurement pattern presented in Figure 2(a) includes a Vernier scale that allows reading with 0.5 μm precision. Figure 2(b) is a close-up on the horizontal Vernier scale that is used for measuring the misalignment in the x direction. Figure 1: Test vehicles GDS and 3d view of assembly Copper pillar micro-bumps with Cu/Ni/SnAg structure were fabricated by electro-chemical deposition (ECD), with 25 μm diameter and 50 μm square pitch. The SnAg thickness of the bumps was 4, 6 and 8 μm. The corresponding UBM pads are made by physical vapor deposition (PVD) of Ti/Ni/Au with a thickness of 200/700/100 nm respectively. The precision of the self-alignment is measured with alignment marks with Vernier scale (Figure 2). All the photolithography steps were done on steppers with a Figure 2: design view of alignment marks (a) gobal view of all the alignment marks (b) zoom on the Vernier scale 558

3 III. SELF-ALIGNMENT ASSEMBLY CONDITIONS Flip-chip stacking was performed on FC150 and FC300 equipment from SET, followed by a mass reflow at 250 C [9]. Figure 3 explains the motion during assembly at the bump level. For testing the self-alignment capability, we purposely induced a controlled initial offset in both x and y direction. This experiment was performed with the FC300 equipment, which makes it possible to place chips reliably with 1 μm precision. to zero. Pre-treatment with liquid flux also reduces the oxygen and the carbon efficiently. This result is consistent with the fact that assembling chips with HCOOH 8% treatment, or with liquid flux pre-treatment, yields a 100% successful assembly ratio (meaning that all the UBM pads are wetted after assembly) [9]. Figure 3: Principle of self-alignment with copper micro bumps IV. SURFACE TREATMENT EFFECT ON SnAg MICRO- BUMPS Proper wetting of the solder is a necessary requirement for self-alignment to occur as expected, which requires the application of an adequate surface treatment. For understanding the actions of the surface treatment on SnAg micro-bump, we performed ToF-SIMS analysis of the oxygen and carbon remaining on the surface of the bumps after each treatment. This gives information on the ability of the treatment to remove the oxide layer and the organic contamination remaining on the bumps. Samples are treated according to TABLE I and immediately stored in vacuum atmosphere in order to prevent re-oxidization. TABLE I DIFFERENT SURFACES TREATMENTS USED AND THEIR CONDITIONS HCOOH 1.7% HCOOH 8% Pre-treatment with liquid flux 205 C C Action at room temperature in ultrasonic bath (3 min) + IPA cleaning The ToF-SIMS results is shown on Figure 4. The reference sample exhibits the highest intensity pic for oxygen and carbon (Figure 4 (a) and (b) respectively), which is a measure of the thickness of oxide layer and organic residues on the bump surface. The sample treated with HCOOH 1.7% has less oxygen and carbon than the reference but HCOOH 8% treatment is more efficient and shows oxygen intensity close Figure 4. Surface treatment impact on bumps surfaces (a) impact on oxygen (b) impact on carbon V. SELF-ALIGNMENT WITH FLUX AND FLUXLESS TREATMENT For self-alignment evaluation, samples are treated with liquid flux, formic acid 8%, or pre-treated with liquid flux. The alignment marks and the Vernier are observed in the infrared with a microscope, as previously explained, in order to measure the alignment accuracy (Figure 5). The result is reported in TABLE II as a function on the initial offset that was set purposely. All the assemblies reached a self-alignment precision better than 0.5 μm. In the case of the liquid flux (Figure 5 c) we observe some residues between copper bumps, which are absent with the 559

4 two other techniques. Since we do not want to alter the optical transmission with flux residues, we gave our preference to these two techniques for the next set of experiment, namely HCOOH 8% treatment and pre-treatment with liquid flux. TABLE II : ALIGNMENT ACCURACY DEPENDING ON THE SURFACE TREATMENT TABLE III SELF-ALIGNMENT ACCURACY DEPENDING ON THE SnAg HEIGHT SnAg height x x <0.5 < <0.5 < <0.5 <0.5 TREATMENT NUMBER OF SAMPLES x x liquid flux <0.5 <0.5 pre-treatment with liquid flux <0.5 <0.5 HCOOH 8% <0.5 <0.5 Figure 5: Infrared microscope observation of the measurement pattern after chip assembly and self-alignment. (a) ideal alignment according to the design (b) self-alignment with formic acid, (c) liquid flux, (d) pre-treatment with liquid flux 560

5 Assemblies were made with different SnAg micro-bumps height and the result is presented in TABLE III. Changing the SnAg height from 8 to 4μm did not alter the self-alignment accuracy, which was still below 0.5μm. Note that the choice of the SnAg height is limited by copper pillar diameter, because in general the height must be lower than radius of the pillar to avoid spilling on the side of the copper pillar during the reflow step. TABLE IV : ACCURACY DEPENDING ON THE INITIAL OFFSET TREATM ENT pretreatment with liquid flux pretreatment with liquid flux HCOOH 8% NUMBER OF SAMPLES x x <0.5 < <0.5 <0.5 Figure 6 Optical paths from fibers to waveguides In a second step we increased the initial offset to study the limit of the restoring motion for bumps with 8μm of SnAg. The result is shown on TABLE IV. The accuracy is still below 0.5μm when the offset is smaller than 6μm (5 and 3μm in laterals directions). But when the offset was increased to 7μm, self-alignment did not occur correctly and the final offset remained the same as the initial one. Fortunately, pickand-place equipment are available that offer a positioning precision better than 5 μm with high throughput (> 1000 Unit Per Hour [10]). Figure 7: Experimental setup showing the assembled chip with horizontal light channels. The optical fibers are aligned with the last optical channel. VI. OPTICAL COUPLING In addition to the self-alignment measurement presented in the previous sections, we performed optical coupling experiments between the two chips, using embedded optical waveguides and vertical grating couplers (VGC). The bottom chip features a reference channel (Figure 6, Path 1) and several bridge channels (Path 2), where the offset between the grating couplers varies for the different channels. The insertion loss for all channels is measured using an automated probe station (Cascade Elite 300) with input and output optical fibers at 8 incidence angle from the vertical (Figure 7). Figure 8 : Offset definition between the grating couplers. In the top view, the two couplers are drawn side by side for clarity, while there are on top of each other in reality. The reference is the first silicon trench of the grating coupler. 561

6 The offset between the VGC is explained in more details on Figure 8. The reference point for defining the offset is the position of the first silicon trench of the grating couplers. Offset values from 2 to 16μm in the horizontal direction were implemented on the test vehicle. The gap = 20μm between the stacked VGCs is fixed by the height of the copper pillars/snag bumps/ubm and the passivation layers. Chips were assembled with the process explained in the previous section. Self-alignment reached a precision below 0.5 μm, as evidenced by reading the Vernier scale. The measured insertion loss for the different channels is presented on Figure 9 after averaging the interferences. Figure 9 : Measured insertion loss for the different channels (after smoothing of the interferences) From this graph, we deduce the loss corresponding to the transition of light between two stacked VGC, as shown on Figure 8 (this is done by subtracting the reference and dividing by two). On Figure 10, the loss at 1300 nm wavelength is plotted as a function of the VGC offset. This experimental result is compared with an FDTD simulation of the system obtained using RSoft software. Figure 10 : Loss of the VGC to VGC transition as a function of the horizontal offset ( ). Experimental measurement shows minimum loss for an offset close to = 8μm, while FDTD simulation performed with a gap = 20μm gives an optimal coupling for = 8.5μm. There is a good agreement between the experiment and the simulation for the position of the optimal coupling, which demonstrates at the same time a good control of the selfalignment and of the optical design. VII. CONCLUSION In this paper we demonstrated submicronic position accuracy after self-alignment between SOI photonic chips using copper pillars micro-bumps. This result was obtained by using suitable surface treatments for the SnAg micro-bumps. We demonstrated that self-alignment with copper microbumps can reach an accuracy lower than 0.5μm with different SnAg bump height (8, 6 and 4μm). We studied the selfalignment according to the initial offset, and found out that for 25μm bumps the self-alignment is efficient (<0.5μm) when the initial offset is smaller than 6 μm. This allows efficient optical coupling from VGC to VGC coupling, paving the way for self-aligned optical architectures involving microlenses positioned on the top of a Photonic Chip. These new architectures will enable low cost, high throughput assemblies of single mode fiber connectors on Photonic Integrated Circuits. ACKNOWLEDGMENTS This work was funded thanks to the French national program Programme d Investissements d Avenir, IRT Nanoelec ANR-10-AIRT-05. The authors would also like to thank the Leti/DOPT/LCPC laboratory, especially Philippe Grosse for helping with optical characterisation on the prober station. REFERENCES [1] R. A. Boudreau and S. M. Boudreau, Eds., Passive micro-optical alignment methods. Boca Raton: Taylor & Francis, [2] S. Bernabé, C. Kopp, M. Volpert, J. Harduin, J.-M. Fédéli, and H. Ribot, Chip-to-chip optical interconnections between stacked selfaligned SOI photonic chips, Opt. Express, vol. 20, no. 7, pp , [3] T. Hayashi, An innovative bonding technique for optical chips using solder bumps that eliminate chip positioning adjustments, IEEE Trans. Compon. Hybrids Manuf. Technol., vol. 15, no. 2, pp , Apr [4] W. Lin and Y. C. Lee, Study of fluxless soldering using formic acid vapor, Adv. Packag. IEEE Trans. On, vol. 22, no. 4, pp , [5] K. Sakuma, A. Shigetou, S. Shoji, and J. Mizuno, Investigations of fluxless flip-chip bonding using vacuum ultraviolet and formic acid vapor surface treatment, in 2011 International Symposium on Advanced Packaging Materials (APM), 2011, pp [6] S.-M. Hong, C.-S. Kang, and J.-P. Jung, Plasma reflow bumping of Sn3.5 Ag solder for flux-free flip chip package application, IEEE Trans. Adv. Packag., vol. 27, no. 1, pp , [7] C. C. Lee and J. Kim, Fundamentals of fluxless soldering technology, in International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, Proceedings, 2005, pp [8] S. Bernabe et al., On-Board Silicon Photonics-Based Transceivers With 1-Tb/s Capacity, IEEE Trans. Compon. Packag. Manuf. Technol., vol. PP, no. 99, pp. 1 8, [9] Y. D. Zonou, O. Castany, S. Bernabe, and P. Arguel, Towards self-alignment with copper pillars, in th Electronic System- Integration Technology Conference (ESTC), 2016, pp [10] Panasonic, Panasonic FCB3 Microelectronics Bonder, Panasonic. 562