Thermal experimental & simulation investigations on new lead frame based LED packages.
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1 Thermal experimental & simulation investigations on new lead frame based LED packages. B. Pardo, A. Piveteau, J. Routin, S, A. Gasse, T. van Weelden* CEA-Leti, MINATEC Campus, 17 rue des Martyrs, GRENOBLE Cedex 9, FRANCE * Boschman Technologies, Stenograaf 3, NL EX Duiven
2 Outline Context Thermal issues in LED Packaging ENIAC Project : Consumerizing Solid State Lighting Thermal resistance determination Implementation of Technological Test Vehicles (LED chips, Lead frame based LED Packages and boards) Thermal resistance set up and measurement procedure Numerical simulations using Finite Element Method Thermal resistance results Comparison of measurements and numerical modeling Discussion Conclusions & Perspectives Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
3 Context - Thermal issue in LED Packaging Incandescent light Heat dissipated by radiation Small exchange areas (1 mm²) + low temperature (100 C) LED light Convection and radiation can be neglected Heat dissipated by conduction at component level Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
4 Context - Thermal issue in LED Packaging Efficiency Color Shift Source: Seoul SC Source: Seoul SC Reliability Source: LumiLeds Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
5 Context - Thermal issue in LED Packaging * Objective of the work R j s * R s b <<0 Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
6 Context - ENIAC Project : Consumerizing Solid State Lighting Partners: Philips, NXP, TNO, ST, CTU, Plessey, Leti... Objectives : Develop a retrofit LED lamp format A60, E27 base Performances of 60W incandescent bulb (800 lm, 2700 K,...) Low cost component process Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
7 Context - ENIAC Project : Consumerizing Solid State Lighting WP4 Description: LED Light Engine WP4 Task 4-1 : Simulation : Thermal Mnt - Mechanical Loading Optical Performance Task 4-2: Packaging of light Engine Component Task 4-3: SIP Approach Task 4-4: LED Light Engine Performance, Reliability and Safety This presentation focuses on some of our work on Tasks 4-1 & 4-2 for thermal management Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
8 Outline Context Thermal issues in LED Packaging ENIAC Project : Consumerizing Solid State Lighting Thermal resistance determination Implementation of Technological Test Vehicles (LED chips, Leadframe based LED Packages and boards) Thermal resistance set up and measurement procedure Numerical simulations using Finite Element Method Thermal resistance results Comparison of measurements and numerical modeling Discussion Conclusions & Perspectives Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
9 Thermal resistance determination Implementation of Technological Test vehicles LED blue chip CREE EZBright 1000 Lead frame based LED Packages Copper layer overmoulded by reflective polymer Boschman Technologies LED component example Interface materials Silver Epoxy die-attach adhesive (Epoteck H20E-HC) SAC Solder joint Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
10 Thermal resistance determination Samples with 2 boards/component pad configurations Boards No Electrical Insulation Electrical Insulation LED component Rebel footprint compatible CREE XP footprint compatible Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
11 Thermal resistance determination Thermal resistance set up and procedure Optical Measurements (SphereOptics) The objective is to measure the Wall-Plug-Efficiency to determine the thermal load and make a correct calculation of the thermal resistance measurement. P Heat = P Elec P Opt The WPE measures only the optical power efficiency for 350 ma at 20 C (and not the dependence of the optical power Vs current or temperature). Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
12 Forward voltage (V) Thermal resistance determination Thermal measurement 1st step: Calibration - K factor measurement 3,25 3,2 3,15 3,1 3,05 3 2,95 2,9 2,85 Calibration curve - step 1 - If = 350 ma y = -0,0038x + 3,2876 R 2 = 0, Temperature ( C) K factor = V f / T Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
13 Thermal resistance determination 2nd step: Thermal transient measurement Working condition example : Drive current 350 ma HeatSink 20 C Calibration C Sense current 1 ma Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
14 Thermal resistance determination Thermal Simulation using Ansys software µm 5 µm 3 µm n QW p Au/Sn GaN Silicone Glue Reflective Polymer 100 µm + Si doped Reflective Polymer 10 µm + Die-Attach (Ag Glue) or Solder 200 µm + - Component Lead Frame Component Lead Frame 10 µm Solder Joint SAC Air Solder Joint SAC Die : GaN / Si (Plessey SC) Die-attach: Silver Epoxy Adhesive Reflective material: White polymer Component Leadfame: Copper layer Solder Joint: Sn/Ag/Cu (SAC305) Encapsulation: Silicone Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
15 Thermal resistance determination Thermal Simulation using Ansys software LED components on Star PCBs (electrically Isolated / Not Isolated) LED Component (Cree XP footprint compatible) on Star PCB LED Component (Rebel footprint compatible) on Star PCB Hypothesis : 3D Steady State Thermal simulation Isotropic material & linear behaviour Wire-bounding not modelized Radiation not taken into account but negligible Boundary Conditions : Initial Temperature: 20 C Heat Flux input 0.8 W/mm² (Die top surface) Fixed Temperature 20 C (PCB bottom surface) Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
16 Outline Context Thermal issues in LED Packaging ENIAC Project : Consumerizing Solid State Lighting Thermal resistance determination Implementation of Technological Test Vehicles (LED chips, Lead frame based LED Packages and boards) Thermal resistance set up and measurement procedure Numerical simulations using Finite Element Method Thermal resistance results Comparison of measurements and numerical modeling Discussion Conclusions & Perspectives Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
17 Thermal resistance results Post-processing example : T3ster Ansys Meshing example Differential structure function calculated calculated from cooling curve measured and evaluated by T3ster 3D steady state simulation results: Temperature distribution example Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
18 Thermal resistance results Thermal Resistance Measurement / Simulation Footprint Configuration Electrical insulation Die Die- Attach Leadframe contribution + SAC Thermal Rsistance (K/W) Leadframe Component (without PCB) Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2, PCB Total (Component + PCB) Simulation Cree XP No 0,86 2,05 1,44 4,35 0,56 4,9 Measurement Cree XP No 2,65 2,26 0,6 5,51 1,96 7,47 Simulation Cree XP Yes 0,85 2,71 1,27 4,82 1,27 6,1 Measurement Cree XP Yes 3,16 2,84 1,6 7,6 5,6 13,2 Simulation Rebel Yes 0,85 1,95 2,3 5,11 3,78 8,8 Measurement Rebel Yes 2,16 3,43 1,16 6,78 5,02 11,8 Simulation Rebel No 0,85 2,4 1,21 4,46 0,14 4,6 Measurement Rebel No 2,4 2,96 2,19 7,55 6,65 14,2 The simulation underestimates the thermal resistance of the die. Concerning the Die-attach, we have a good correlation T3ster Vs Ansys. The solder-joint geometry variability could explain the differences between Rth_simulated & Rth_measured on leadframe component. The thermal conductivity of PCB is always understimated The thermal resistance is underestimated or a delamination on solder joint could increase the measured Rth (only observed on this particular sample)
19 Conclusions & Perspectives Conclusions Single Chip Lead frame LED Components have been produced Thermal resistances has been determined thanks to electrical and optical measurements using the T3Ster equipment Numerical simulations and comparison with thermal measurements have been carried out. A relative good agreement between simulations & measurements Input data for the conductivity of materials need to be modified versus input data from the datasheet of the PCB Low thermal resistances as low as 5.5 K/W components have been obtained Perspectives Optimization of die-attach process (reproducibility) Multi-chip and multi-component Led modules investigated Reliability studies to start Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
20 Acknowledgement CSSL is partly funded by the European Commission and the participating Public Authorities in the ENIAC Joint Undertaking. ENIAC=European Nanoelectronics Initiative Advisory Council Thank you for your attention
21 Thermal experimental & simulation investigations on new lead frame based LED packages. Benjamin PARDO February 1&2,
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