IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 8, AUGUST

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1 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 8, AUGUST Impact of Copper Through-Package Vias on Thermal Performance of Glass Interposers Sangbeom Cho, Venky Sundaram, Rao R. Tummala, Fellow, IEEE, and Yogendra K. Joshi, Fellow, IEEE Abstract In this paper, the thermal performance of glass interposer substrate with copper through-package vias (TPVs) is investigated both experimentally and numerically. Copper via arrays with different via pitches and diameters were fabricated in mm mm 100 µm glass panels using low-cost laser drilling, electroless plating, and electroplating for copper deposition. The thermal performance of such a structure was quantified by measuring an effective thermal conductivity which combines the effect of copper and glass. The effective thermal conductivity of fabricated samples was determined with infrared microscopy and compared with finite-element analysis on unit TPV cell. Using the effective thermal conductivity, further numerical analyses were performed on a 2.5-D interposer, which has two chips mounted side by side with a total heat generation of 3 W. Interconnects and TPV layers in the interposer were modeled as homogeneous layers with an effective thermal conductivity. Using the developed model, the effect of copper TPVs on the thermal performance of silicon and glass interposers was compared. To further characterize the thermal performance of the 2.5-D glass interposer structure, the effects of pitch of interconnects and TPVs and the TPV diameter are presented. Index Terms 2.5-D interposer, thermal performance, through-package via (TPV). I. INTRODUCTION SILICON and glass interposers have been proposed and are being developed as next-generation substrates to overcome the limitations of organic substrates due to many advantages, including high I/O density. However, a silicon interposer is limited to 300-mm wafer sizes, leading to high fabrication cost of each interposer and high electrical loss limiting its electrical performance. To address these issues, the 3-D Systems Packaging Research Center at Georgia Tech has been developing glass interposers since 2010 [1]. Glass has the merits of panel-based processing, which results in low costs. Combined with the advantages of ultrahigh electrical resistivity, low electrical losses make glass an excellent interposer candidate over organic and silicon [2]. However, glass has a 100-times lower thermal conductivity than silicon, which can result in poor thermal transmission. Manuscript received December 24, 2014; revised May 3, 2015; accepted June 15, Date of publication July 23, 2015; date of current version August 12, This work was supported by the Silicon and Glass Interposers Consortium through the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA. Recommended for publication by Associate Editor A. Jain upon evaluation of reviewers comments. S. Cho and Y. K. Joshi are with the G. W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA USA ( scho84@gatech.edu; yogendra.joshi@me.gatech.edu). V. Sundaram and R. R. Tummala are with the 3D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, GA USA ( vs24@mail.gatech.edu; rao.tummala@ece.gatech.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCPMT This paper addresses this problem by experimentally and numerically investigating the effect of copper through-package vias (TPVs), which serve as a major thermal path within the interposer. The idea of using metal vias for thermal management was first adopted in the design of interconnects between the chip and printed circuit boards (PCBs). Lee et al. [3] developed analytical closed form expressions for the thermal resistance network of vias between multichip modules, which showed good agreement with experimental data. Li [4] studied the relationship between the thermal resistance and the via design parameters. This paper shows that adding metal vias can improve the thermal performance across the PCB by over 10 times. A number of studies have explored the advantages of 2.5-D and 3-D package integration technologies (Fig. 1) over 2-D integration. The main advantage of 3-D technology is to enhance interconnect density using through-silicon vias (TSVs) in logic and memory chips, which provides an improved bandwidth due to reduced interconnect length [5]. However, the power densities in these stacked 3-D integrated circuits (ICs) dramatically increase as the number of stacked chips increases, while the area of the chips decreases. This may result in thermomechanical reliability failures, in addition to lower electrical performance due to high junction temperature. Incorporating thermal vias in ICs can be a promising way to solve this problem. However, it poses area penalty for routing space and reduces the number of electrical I/Os, resulting in a tradeoff between thermal and electrical performances. Recent studies with thermal vias were focused on the development of algorithms for an efficient placement of thermal vias in 3-D ICs, minimizing the perturbations on routing [6], [7]. Goplen and Sapatnekar [6] developed an algorithm to determine the optimized number of thermal vias in 3-D ICs for various thermal objectives, including minimizing maximum temperature and thermal gradients. Lee and Lim [7] presented a cooptimization study for interconnects in 3-D ICs, considering signal, power, and thermal aspects. Numerical simulations have also been carried out to study the temperature distribution within 3-D ICs with TSVs. Ma et al. [8] proposed a simplified thermal model for TSVs in interposer using effective thermal properties. The accuracy and the application limits of the model were presented along with the volume ratio of copper and silicon. Lau and Yue [9] studied the thermal performance of 3-D IC integration system-in-package with TSVs through modeling. The study presented the effect of various parameters, including TSV filler material, diameter, pitch, and aspect ratios, on the thermal IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 1076 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 8, AUGUST 2015 Fig. 1. Schematic of (a) 2.5-D interposer packaging with logic and memory and (b) 3-D IC integration technology with TSVs. resistance of the interposers. The thermal performance of TSVs in 3-D chip stack was also evaluated experimentally. Zhang et al. [10] examined the thermal characteristics of TSV arrays by measuring the electrical resistance, which has a linear relationship with temperature. Matsumoto et al. [11] measured the temperature distribution of 3-D stacked test chips and calculated the equivalent thermal conductivity of the interconnection. Oprins et al. [12] presented a methodology for the detailed thermal analysis of stacked die packages, including the complete back-end-of-line structures. In the study, a two-die stacked structure in a ball grid array package configuration was studied and the results were experimentally validated. Kim et al. [13] and Zhang et al. [14] have studied the application of advanced cooling schemes in 3-D ICs. Kim et al. [13] investigated single-phase and phase-change convection, and discussed the effect of different refrigerants on thermal performance of 3-D ICs. Zhang et al. [14] presented 2.5-D and 3-D integration approaches with an embedded microfluidic cooling, which utilized fluidic microbumps and fluidic vias. While a number of works have been reported on the thermal characterization of silicon-based 2.5-D and 3-D integration technologies, thermal studies of glass-based integration technologies are currently lacking both experimental and numerical characterizations [15], [16]. This paper is organized into three sections. Section II describes the fabrication process of glass interposer test samples. Fabricated samples with via structures and test setup designed for the thermal performance measurements are also presented. Section III compares the test results with finiteelement (FE) analysis. Section IV provides simulation results to study the effect of TPVs on the thermal performance of 2.5-D glass interposers. The results from parametric studies of the effect of via pitch and diameter are also presented. II. THERMAL CONDUCTIVITY MEASUREMENT OF GLASS INTERPOSER WITH COPPER VIAS To measure the effect of copper TPVs on the thermal performance of glass interposer, TPV via arrays were fabricated on a 114 mm 114 mm 100 μm borosilicate glass panel. Prior to via drilling, both surfaces of the panel were cleaned with acetone and isopropyl alcohol. Then both sides were laminated with 22.5-μm-thick dielectric polymer layers. A hot press machine was used during the lamination process with optimized temperature and time settings. The laminated polymer layer serves as a buildup layer Fig. 2. Process flow for glass interposer fabrication. for wiring and also as a buffer layer which reduces the impact of laser on glass during the ablation process [2]. The laminated glass sample was then subjected to UV laser ablation for via formation. The UV laser drilling resulted in tapered via profiles. Fig. 2 summarizes the process flow used for the test sample fabrication. It also shows the optical images of glass samples via entrance and exit formed by UV laser ablation. To achieve good metal adhesion to the glass panel, the surface of polymer was roughened through microetch processes. A 1-μm copper seed layer was formed on the roughened surface through electroless copper deposition, followed by electrolytic copper plating processes which resulted in a final copper layer thickness of 10 μm. After having the via side walls plated, via pads were patterned using photolithography. Via pad diameter was designed to be 40 μm larger than each via diameter. Table I summarizes the via dimensions of fabricated via arrays including entrance and exit via diameters, pitches, plating thickness, pad size, and the number of vias. After patterning the via pads, the panel was diced into 10 pieces of 2.54 mm 2.54 mm-size glass samples with TPV arrays having different via parameters. A. Test Setup for Effective Thermal Conductivity Measurement To measure thermal conductivity of via samples, a heater assembly was fabricated, which consisted of a heater

3 CHO et al.: IMPACT OF COPPER TPVs ON THERMAL PERFORMANCE OF GLASS INTERPOSERS 1077 TABLE I TPV GEOMETRY AND DIMENSIONS Fig. 3. Schematic of test setup to measure effective thermal conductivity of glass samples with copper vias. and a PCB. The size of the heater was 2.54 mm 2.54 mm, which corresponded to the sample size with a 100-μm thickness. The heater was comprised of two resistors, each able to dissipate a maximum power of 6 W and was wire bonded to the PCB for power supply connection. Two diodes placed at the center and the edge of the heater were utilized for surface temperature measurements. The heat-generating surface of the heater was exposed to ambient, and its other sides were surrounded by epoxy with wire bonds. The epoxy protected the heater and wirebonds from mechanical and electrical impact and also minimized heat loss from the surfaces of heater. After the epoxy was cured, the heater diodes were calibrated by putting the assembly in a large oven. A via-patterned glass sample of the size of 2.54 mm 2.54 mm was attached to the heater using a thermal adhesive pad. After the sample was attached to the heater, the assembly was covered with an insulation material to reduce heat losses through convection and radiation to the ambient. Fig. 3 shows the schematic of the test setup used to measure the effective thermal conductivity of glass samples with copper TPVs. A Quantum Focus Instruments Infrared (IR) microscope, with a spatial resolution of 2.8 μm and a pixel size of 1.6 μm, was used to measure the surface temperature of the sample. The heater assembly was mounted and tightly fixed on the thermal stage of IR microscope using Teflon blocks. Two source meters were connected to the heater assembly to supply power to the heater and to provide constant current source (1 ma) to diodes. Six additional thermocouples were attached to the PCB and the epoxy area to estimate the amount of heat dissipated through conduction. Prior to the measurements, the surface of the sample was coated with a black carbon spray to reduce the uncertainty in the measurement. The IR microscope measures radiance at a defined reference temperature. This allows the acquisition of the reference emissivity at each pixel area of the sample. This calibrated emissivity map of the sample was used in subsequent measurements to accurately measure temperature. The reference temperature was selected such that it was in proximity to the temperature of the area of interest during the tests. Heat loss through epoxy was estimated using thermal resistance analysis, including spreading resistance, and calculated to be 14% of total power input of the heater. Heat loss through convection Q c was estimated using (1) and its heat transfer coefficient h c was calculated using (2) for small devices in a natural convection condition [17] Q c = h c A T (1) h c = 0.83 f ( T/L ch ) n (2) where T is temperature difference between the surface and the ambient, L ch is the characteristic length, f = 1 and n = 0.33 for horizontal plate facing upward. Heat loss through radiation Q R was estimated using the expression for a small surface in large surroundings Q R = εσ A ( Tsurf 4 T sur 4 ) (3) where T surf is the sample s surface temperature ( 343 K) at targeted heater power level, T sur is the temperature of the surroundings, ε ( 0.8) is emissivity measured by the IR microscope system, and σ is the Stefan Boltzman constant ( W/m 2 K 4 ). Total heat losses through convection and radiation were found to be 5% of the total heater power. Fig. 4 shows the thermal resistance network of the via sample stack-up on heater. Heater resistance R h and thermal pad resistance R p were measured separately prior to each stack-up to determine T 3. The average surface temperature of the sample T 4 was measured by the IR microscope. Finally, the effective thermal conductivity of the glass sample was calculated using y k = Q (4) T

4 1078 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 8, AUGUST 2015 Fig. 4. Thermal resistance network of sample stack-up on heater. where Q is the heat flux calculated using the power input of the heater minus the estimated heat losses, y the sample thickness, and T the temperature difference between T 4andT3. B. Effective Thermal Conductivity Calculation Due to the large number of via interconnects, the development of the thermal model of interposer is computationally intensive. To resolve this problem, an equivalent model with effective thermal conductivity has been used [9], [18]. Since interconnect vias are populated in the interposer with repeated geometric patterns, they can be simplified by converting a single cell of interconnect/tpv pattern into a block with a representative thermal conductivity. Both in-plane and out-of-plane thermal conductivity should be calculated because the thermal path offered by the copper structure is dependent on the direction of heat flow. To determine in-plane and out-of-plane effective thermal conductivity of a interconnect/ TPV cell, the inward heat flux boundary condition was applied to the left/top surface, the outward heat flux condition was applied to the right/bottom surface, and the adiabatic condition was applied to the other side walls of the model. Effective thermal conductivity was calculated with (4) using the average temperature of left/top and right/bottom surfaces. Models for three different samples listed in Table I were developed and the effective thermal conductivities were calculated. C. Test and Simulation Results Fig. 5 shows steady-state IR images of the glass samples with different via patterns heated from the back. In each image, copper pads show the highest temperature due to high thermal conductivity compared with polymer-laminated glass around them. However, the temperature profile along the copper pad was not symmetric, a trend observed for all samples. From the cross-sectional and top view images shown in Fig. 6, it was observed that copper was not evenly plated at the heater side of each TPV, which caused poor thermal contact between the heater and the sample. A likely cause was the misalignment of the TPV mask with glass panel during photolithography. This additional interfacial thermal resistance between the sample and the heater is thought to be the major reason for the nonuniform temperature profile along the edge of the TPV in IR images. Fig. 5. Surface temperature profile of (a) Sample 1, (b) Sample 2, (c) Sample 3, and (d) Sample 4 measured with IR microscopy. D: diameters of vias. P: pitches of vias. N: numbers of vias. Fig. 6. Cross-sectional view (top) and top view (bottom) of Sample 3. The resolution uncertainty of the test system was calculated using equation ( ) G 2 ( ) G 2 ( ) G 2 u G = u 1 + u u n (5) x 1 x 2 x n where u G is the uncertainty of variable G and u 1 u n are the uncertainties of variable x 1 x n. The uncertainties of the test results were calculated after performing five sets of measurements for each sample,

5 CHO et al.: IMPACT OF COPPER TPVs ON THERMAL PERFORMANCE OF GLASS INTERPOSERS 1079 TABLE II COMPARISON OF THE MEASURED OUT-OF-PLANE EFFECTIVE THERMAL CONDUCTIVITIES OF THE GLASS SAMPLES WITH SIMULATION TABLE III PERCENTAGE ERROR BETWEEN CALCULATED EFFECTIVE OUT-OF-PLANE THERMAL CONDUCTIVITY FROM MODELS AND MEASUREMENTS FOR SAMPLES 2 AND 3 Fig. 7. models. Copper plating condition of vias in (a) original and (b) corrected and expressed as u k = B ± σ (6) where u k is the uncertainty of the measured effective out-of-plane thermal conductivity, B is the average value, and σ is the standard deviation of five measurements. Before taking each measurement, the sample was cooled down to ambient temperature, and heated up again to reference temperature for new emissivity mapping. Table II compares the effective out-of-plane thermal conductivity of four samples. Results for Samples 2 4 are compared with the simulation results from single via analysis introduced in the previous section, while Sample 1 simulation is compared with the measurement in [15]. Samples 2 and 3 show large differences ( 36% and 39%), while Sample 4 shows the least ( 5%). Several factors, including additional heat loss, quality of thermal contact between each layer in the samples, and copper plating quality, can contribute to the discrepancy. From the test and simulation results, shown in Table II, the implementation of 144 copper vias with a diameter of 100 μm at a pitch of 200 μm in a 2.54 mm 2.54 mm area increases the out-of-plane thermal conductivity of the glass substrate by 20 times compared with its original property (1 W/m K). One of the sources of the discrepancy between the test and simulation for Samples 2 and 3 was copper plating quality. Based on the copper plating quality condition acquired from the cross-sectional top and bottom images of the samples, new via models were developed. Fig. 7 shows two different via models with different copper plating conditions of vias in the original model and the corrected model. Another source of error can be the contact resistance between the thermal adhesive and the sample, which was neglected in the model. To evaluate the effect of the contact resistance on the discrepancy between modeling and test results, the contact resistance of the same adhesive material (room temperature vulcanization silicone) from [19] was used, assuming that the contact conditions between the sample and the adhesive are similar. Table III shows the error (in %) calculated after comparing the effective out-of-plane thermal conductivity from the original copper plating condition corrected and the contact resistance-applied model with test results. The errors (in %) for Samples 2 and 3 decrease as the models get corrected, which shows that these two factors can be the major causes of the discrepancy. To get more accurate test results, the contact resistance of each sample needs to be measured. III. SIMULATION WITH 2.5-D INTERPOSER APPLICATION Prior studies have shown that the thermal conductivity of the substrate does not significantly affect the thermal performance of the interposer as most of the heat generated from chips is dissipated through the back of the chip to the lid or heat sink [16]. Interposer structures without heat sink were considered for low-power application (3 W) to show the effect of interposer components on thermal performance. Using an equivalent interposer model with effective thermal conductivities for copper TPVs, a 2.5-D glass interposer was developed. The interposer model consisted of five major components: chips, microbumps, interposer, bumps, and PCB. Several assumptions were made in the modeling of each component as geometric details and arrangements of TPVs are dependent on the floorplanning of the dies and signal assignment. General assumptions made for current simulation studies are as follows. 1) Both chips on the interposer have identical size (10 mm 10 mm) and heat generation. 2) Chips are modeled as two blocks which have uniform volumetric heat generations and the distance between the two chips is fixed at 100 μm. 3) Microbumps under the periphery area of the chips have smaller pitch than those in the center area and are assigned for signal delivery between dies.

6 1080 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 8, AUGUST 2015 Fig. 8. Schematic of 2.5-D interposer and geometric dimensions of microbumps, TPVs, and bumps used for modeling. 4) Microbumps under the center area of the chips (9 mm 9 mm area) are directly connected to copper TPVs. TPVs are also connected to bumps directly for ground connection to PCB. 5) 20% of TPVs are assigned as ground TPVs. The ground TPVs are connected to copper vias in PCB, which are directly connected to a ground plane. 6) One ground plane is embedded in PCB. It has the same size as PCB (50 mm 50 mm) and a thickness of 0.5 oz ( 18 μm). A power layer in PCB is not considered in the model. 7) As the number of interconnects increases or decreases, the number of TPVs also increases or decreases for increased-decreased signal delivery. To control interconnects and TPVs together, four microbumps are assumed to be connected with one TPV, and two TPVs are connected with one bump. For ground via connection, each bump is mapped one-to-one to copper vias in PCB. Ground TPVs are assumed to be placed under the center of the chip area. 8) All heat generated from chip (3 W) is assumed to be conducted through components and dissipated at the bottom of PCB, which has its bottom plane temperature fixed at 300 K. Based on the above assumptions, a parametric design study of silicon and glass interposers was performed to characterize the effect of copper TPVs and copper ground plane. A. Effect of Copper TPVs and Ground Plane on Glass and Silicon Interposers The purpose of the first simulation was to compare the effect of copper TPVs on the thermal performance of silicon TABLE IV GEOMETRIC DIMENSIONS OF INTERPOSER COMPONENTS and glass interposers. The model did not include the effect of copper traces within re-distribution layer in the interposer or PCB and focused only on the effect of copper vias and single copper ground plane on the thermal performance of the interposer. The geometric details are summarized in Fig. 8. The dimensions of chips, interposer, and PCB, and the number of interconnects/vias are tabulated in Table IV. Table V summarizes material thermal conductivities. As a baseline, silicon and glass interposer structures without copper TPVs and ground plane were considered and the maximum temperature of each structure was compared with each interposer structure having vias and ground plane implemented. TPV shape, diameter, and total substrate thickness were kept the same for silicon and glass interposers as shown in Figs. 8 and 9. The thickness of the polymer layers in the glass interposer was 22.5 μm, which corresponded to the thickness of the polymer laminated on the sample. The SiO 2 layer thickness in the Si interposer was modeled as 1 μm, which corresponded to the typical dielectric layer thickness on a silicon interposer.

7 CHO et al.: IMPACT OF COPPER TPVs ON THERMAL PERFORMANCE OF GLASS INTERPOSERS 1081 TABLE V MATERIAL PROPERTIES AND CALCULATED EFFECTIVE THERMAL CONDUCTIVITIES OF INTERCONNECTS AND TPVs Fig. 10. Surface temperature profile of (a) and (b) glass interposer and (c) and (d) silicon interposer with different via and layer condition. Fig. 9. Geometric dimension of TPV in silicon interposer. Fig. 10 compares the surface temperature profile and the maximum temperature of the two interposers for two different cases, when each chip generates 1.5 W. Due to symmetry, only a quarter of the geometry was considered and is shown in Fig. 10. Without copper TPVs and ground layers, the glass interposer showed a 32% higher maximum temperature than the silicon interposer. The glass substrate showed a similar temperature with PCB, as glass impedes the heat being conducted through the substrate. The silicon interposer, however, decreased the chip temperature, resulting in a substrate temperature higher than that of the glass interposer. The difference in maximum temperature between glass and silicon interposers decreased after TPVs and ground layer were implemented in both interposers as shown in Fig. 10(b) and (d). The glass interposer showed a 17% higher maximum temperature than the silicon interposer. The results indicate that the copper TPVs in the glass interposer perform more effectively than those in the silicon interposer. Fig. 11 compares junction-to-board thermal resistance jb improvement of glass and silicon interposers, where jb = T j T b (7) Q where T j is the junction temperature, T b is the board bottom temperature, and Q is the total heat generated from the chips. The addition of TPVs and ground layer decreased the thermal resistance of both interposers, but the resistance of glass Fig. 11. Normalized junction-to-board thermal resistances of glass and silicon interposers with different via and ground layer conditions. interposer showed higher comparative decrease than silicon, and confirmed the better thermal effectiveness of copper TPVs in the glass interposer than those in silicon. B. Effect of TPV Pitch on Thermal Performance of Glass Interposer To characterize the effect of interconnects and TPVs on the glass interposer, further analyses of the effect of pitch were performed based on Assumption 7. Three cases with different numbers of interconnects and TPVs were considered for the glass interposer structure. Table VI lists the numbers and the pitches used for three different cases. Other geometric features and dimensions remained the same as shown in Fig. 8. During the simulation, only the pitch of microbumps in the

8 1082 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 8, AUGUST 2015 TABLE VI PITCH/COUNT AND NORMALIZED jb OF MICROBUMPS,TPVs,AND BUMPS FOR THREE CASES.EACH THERMAL RESISTANCE IS NORMALIZED BY THE RESISTANCE VALUE FROM CASE 1 Fig. 13. Junction-to-board thermal resistances of glass interposer with different D1 (laser entrance diameter) and D2 (laser exit diameter). Fig. 12. Normalized junction-to-board thermal resistance with different effective out-of-plane thermal conductivities of three components (microbumps, TPVs, and bumps). Each component s resistance is normalized by its maximum value. center area was varied, and the outside of it was kept constant as 80 μm. The total number of microbumps in the periphery area was Table VI compares the jb in three cases by normalizing them by maximum value from Case 1. As the number of interconnects and TPVs increased, the thermal performance of the glass interposer also increased, but its effect was not significant. Case 3 showed a 9% better thermal performance than Case 1 by having a 3.5 times higher number of interconnects and TPVs. Fig. 12 shows the thermal performance improvement of the glass interposer by changing the effective out-of-plane thermal conductivity of the microbumps, TPVs, and bumps. Interconnect and TPV counts in Case 1 of Table VI were considered for the fixed components. The variation of thermal conductivity ranged from that of glass (1 W/m K) to copper (400 W/m K). The effect of interconnect/tpv on in-plane thermal conductivities was not considered because negligible variation in it was observed compared with out-of-plane thermal conductivity. A consistent dependence trend for all the three components was demonstrated with a relatively large drop between 1 and 50 W/m K. Increasing the thermal conductivity of interconnect/tpv layers beyond 100 W/m K did not enhance the performance much. The thermal conductivity change in bump layer affected the thermal performance of the interposer the most, while the microbump affected the least. For interconnects, an effective thermal conductivity in the range W/m K is hard to achieve, as the solder has a lower thermal conductivity ( 50 W/m K) than copper. However, TPV only consists of copper and thus can have a wider range of effective thermal conductivity values, depending on the amount of copper used for filling vias. Fig. 13 shows the change in jb for different TPV diameters at fixed pitch (300 μm) and height of the interposer (145 μm). As the diameters (D1 andd2) increase, the effective out-of-plane thermal conductivity of the TPV layer also increases due to the increased copper volume fraction. This result indicates that increasing out-of-plane thermal conductivity to that of copper gave insignificant enhancement, compared with the implementation of TPVs with diameters of 160 and 130 μm. This implies that the thermal resistance of other components becomes more dominant than that of the interposer substrate after TPV implementation. The change in effective in-plane thermal conductivity of TPV was negligible ( 1 3 W/m K) compared with the change in effective out-of-plane thermal conductivity ( W/m K) during the analysis. IV. CONCLUSION This paper investigates the effect of copper TPVs in glass interposers through FE modeling and measurements. Copper TPVs were fabricated in a glass interposer and their effective thermal conductivity was measured by IR microscopy. The measured values were compared with the results from the FE model which used an equivalent TPV layer with effective thermal conductivity. Using the equivalent modeling technique, a 2.5-D interposer model was developed for parametric design study. Detailed interconnects and TPV geometry dimensions were incorporated in the modeling to develop a more realistic model. Major results from the parametric design study are as follows. 1) The implementation of copper TPVs in glass interposers and copper ground layers in PCBs enhanced the thermal performance of interposers. Interconnects and TPVs perform as thermal as well as electrical paths.

9 CHO et al.: IMPACT OF COPPER TPVs ON THERMAL PERFORMANCE OF GLASS INTERPOSERS ) The TPVs in glass interposer performed more effectively than in the silicon interposer. Glass isolated heat within the chip due to its low thermal conductivity. The silicon interposer substrate, however, played a role as a heat spreader which efficiently lowered the chip temperature. 3) Increasing the number of interconnects and TPVs by decreasing their pitch improved the thermal performance of the glass interposers due to the increased effective out-of-plane thermal conductivity of interconnect and TPV layers. It was shown that the glass interposer s out-of-plane thermal resistance became no longer significant for effective thermal conductivities higher than 100 W/m K. ACKNOWLEDGMENT The authors would like to thank the member companies of the low-cost glass interposers and packages consortium at the Georgia Institute of Technology 3-D Systems Packaging Research Center for supporting this study. REFERENCES [1] V. Sukumaran et al., Through-package-via formation and metallization of glass interposers, in Proc. IEEE 60th Electron. Compon. Technol. Conf. (ECTC), Jun. 2010, pp [2] V. Sukumaran, T. Bandyopadhyay, V. Sundaram, and R. Tummala, Low-cost thin glass interposers as a superior alternative to silicon and organic interposers for packaging of 3-D ICs, IEEE Compon., Packag., Manuf. Technol., vol. 2, no. 9, pp , Sep [3] S. Lee, T. F. Lemczyk, and M. M. Yovanovich, Analysis of thermal vias in high density interconnect technology, in Proc. 8th IEEE Annu. Semicond. Thermal Meas. Manage. Symp. (SEMI-THERM), Feb. 1992, pp [4] R. S. Li, Optimization of thermal via design parameters based on an analytical thermal resistance model, in Proc. Thermal Thermomech. Phenomena Electron. Syst., May 1998, pp [5] W. R. Davis et al., Demystifying 3D ICs: The pros and cons of going vertical, IEEE Des. Test Comput., vol. 22, no. 6, pp , Nov./Dec [6] B. Goplen and S. S. Sapatnekar, Placement of thermal vias in 3-D ICs using various thermal objectives, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 4, pp , Apr [7] Y. Lee and S. K. Lim, Co-optimization and analysis of signal, power, and thermal interconnects in 3-D ICs, IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 30, no. 11, pp , Nov [8] H. Ma, D. Yu, and J. Wang, The development of effective model for thermal conduction analysis for 2.5D packaging using TSV interposer, Microelectron. Rel., vol. 54, no. 2, pp , Feb [9] J. H. Lau and T. G. Yue, Effects of TSVs (through-silicon vias) on thermal performances of 3D IC integration system-inpackage (SiP), Microelectron. Rel., vol. 52, no. 11, pp , Nov [10] L. Zhang, H. Y. Li, G. Q. Lo, and C. S. Tan, Thermal characterization of TSV array as heat removal element in 3D IC stacking, in Proc. IEEE 14th Electron. Packag. Technol. Conf. (EPTC), Dec. 2012, pp [11] K. Matsumoto, S. Ibaraki, K. Sakuma, and F. Yamada, Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack, in Proc. IEEE Int. Conf. 3D Syst. Integr., Sep. 2009, pp [12] H. Oprins et al., Fine grain thermal modeling and experimental validation of 3D-ICs, Microelectron. J., vol. 42, no. 4, pp , Apr [13] Y. J. Kim, Y. K. Joshi, A. G. Fedorov, Y.-J. Lee, and S.-K. Lim, Thermal characterization of interlayer microfluidic cooling of three-dimensional integrated circuits with nonuniform heat flux, J. Heat Transf., vol. 132, no. 4, 2010, Art. ID [14] Y. Zhang, A. Dembla, Y. Joshi, and M. S. Bakir, 3D stacked microfluidic cooling for high-performance 3D ICs, in Proc. IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [15] S. Cho, Y. Joshi, V. Sundaram, Y. Sato, and R. Tummala, Comparison of thermal performance between glass and silicon interposers, in Proc. IEEE 63rd Electron. Compon. Technol. Conf. (ECTC), May 2013, pp [16] T. Hisada and Y. Yamada, Effect of thermal properties of interposer material on thermal performance of 2.5D package, in Proc. Int. Conf. Electron. Packag. (ICEP), Apr. 2014, pp [17] W.-H. Chen, H.-C. Cheng, and H.-A. Shen, An effective methodology for thermal characterization of electronic packaging, IEEE Trans. Compon. Packag. Technol., vol. 26, no. 1, pp , Mar [18] H.-C. Chien et al., Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications, in Proc. IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [19] P. Teertstra, Thermal conductivity and contact resistance measurements for adhesives, in Proc. ASME InterPACK, Jul. 2007, pp microelectronics. Sangbeom Cho received the B.S. degree from Hanyang University, Seoul, Korea, and the M.S. degree in mechanical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Korea. He is currently pursuing the Ph.D. degree in mechanical engineering with the Georgia Institute of Technology, Atlanta, GA, USA. He is with the 3-D Systems Packaging Research Center, Georgia Institute of Technology. His current research interests include thermal management of Venky Sundaram received the B.S. degree from IIT Mumbai, Mumbai, India, and the M.S. and Ph.D. degrees in materials science and engineering from the Georgia Institute of Technology, Atlanta, GA, USA. He is currently the Director of Research and Industry Relations with the 3-D Systems Packaging Research Center, Georgia Institute of Technology. He is the Program Director of the Low-Cost Glass Interposer and Packages Industry Consortium with more than 25 active global industry members. He is a globally recognized expert in packaging technology and a Co-Founder of Jacket Micro Devices, Livonia, MI, USA and an RF/wireless startup acquired by AVX Corporation, Fountain Inn, SC, USA. He has authored over 15 patents and 100 publications. His current research interests include system-on-package technology, 3-D packaging and integration, ultrahighdensity interposers, embedded components, and systems integration research. Dr. Sundaram has received several best paper awards. He is the Co-Chairman of the IEEE CPMT Technical Committee on High-Density Substrates and the Director of Education Programs with the Executive Council of the International Microelectronics and Packaging Society.

10 1084 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 8, AUGUST 2015 Rao R. Tummala (F 93) received the B.S. degree from the Indian Institute of Science (IIS), Bangalore, India, and the Ph.D. degree from the University of Illinois at Urbana Champaign, Champaign, IL, USA. He was an IBM Fellow, pioneering the first plasma display and multichip electronics for mainframes and servers. He is currently a Distinguished and Endowed Chair Professor and the Founding Director of the National Science Foundation s Engineering Research Center with the Georgia Institute of Technology, Atlanta, GA, USA, pioneering Moore s Law for system integration. He has authored over 500 technical papers, holds 74 patents and inventions, and has authored the first modern book entitled Microelectronics Packaging Handbook, the first undergrad textbook entitled Fundamentals of Microsystems Packaging, and the first book introducing the system-on-package technology. Prof. Tummala is a member of the National Academy of Engineering. He has received many industry, academic, and professional society awards, including the Industry Week s Award for improving the U.S. competitiveness, the IEEE David Sarnoff Award, the International Microelectronics and Packaging Society Dan Hughes Award, the Engineering Materials Award from ASM, and the Total Excellence in Manufacturing from SME. He received the Distinguished Alumni Awards from the University of Illinois at Urbana Champaign, IIS, and the Georgia Institute of Technology. He was a recipient of the Technovisionary Award from the Indian Semiconductor Association and the IEEE Field Award for his contributions to electronics systems integration and cross-disciplinary education in He was the President of the IEEE Components, Packaging, and Manufacturing Technology Society and the IEEE International Microelectronics and Packaging Society. Yogendra K. Joshi (F 12) received the B.Tech. degree in mechanical engineering from IIT Kanpur, Kanpur, India, in 1979, the M.Sc. degree in mechanical engineering from the State University of New York, Buffalo, NY, USA, in 1981, and the D.Phil. degree in mechanical engineering and applied mechanics from the University of Pennsylvania, Philadelphia, PA, USA, in He is currently a Professor and John M. McKenney and Warren D. Shiver Distinguished Chair with the G. W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA, USA. He has authored or co-authored over 260 archival journal and conference publications. His current research interests include multiscale thermal management. Prof. Joshi is a fellow of the American Society of Mechanical Engineers (ASME) and the American Association for the Advancement of Science. He was a co-recipient of the ASME Curriculum Innovation Award in 1999, the Inventor Recognition Award from the Semiconductor Research Corporation in 2001, the ASME Electronic and Photonic Packaging Division Outstanding Contribution Award in Thermal Management in 2006, the ASME Journal of Electronics Packaging Best Paper of the Year Award in 2008, the IBM Faculty Award in 2008, the IEEE Semitherm Significant Contributor Award in 2009, the IIT Kanpur Distinguished Alumnus Award in 2011, the ASME InterPack Achievement Award in 2011, the ITherm Achievement Award in 2012, and the ASME Heat Transfer Memorial Award in 2013.