Perspectives on giga-bit scaled DRAM technology generation

Transcription

1 Microelectronics Reliability 40 (2000) 191±206 Introductory invited paper Perspectives on giga-bit scaled DRAM technology generation Kinam Kim Technology Development, Memory Device Business, Samsung Electronics Co., San #24, Nongseo-Lee, Kiheung-Eup, Yongin-Gun, Kyungki-Do, South Korea Received 30 August Abstract As the density of DRAM approaches giga-bit scaled DRAM, many critical challenges emerge from its small cell size. The most critical obstacles are insu cient cell capacitance and large leakage current at storage junction. Besides, variation of threshold voltage of memory cell transistor and the increased delay of word line and bit line come up to limit performance of device. In this paper, the critical issues in giga-bit technology are reviewed and appropriate approaches to overcome these issues are discussed based on the technology generation. The discussions are mainly focused on the key technologies: memory cell capacitor technology, memory cell transistor technology, word line and bit line technology, memory cell connection technology and metallization technology. Down to the 0.10 mm technology generation, we can speci cally de ne the challenges for each technology generation and can nd the ways to overcome these obstacles with proper technology migrations based on the current Capaciton-Over-bit line cell structure. The technology migration will move toward Ta 2 O 5 capacitor, modi ed memory cell transistor, W- gate, W-bit line and self-aligned landing pad technology in cost-e ective ways. Beyond the 0.10 mm technology generation, breakthrough technology seems to be indispensable. The breakthrough technology should happen in memory cell concept, memory cell structure and integration technology. # 2000 Elsevier Science Ltd. All rights reserved. 1. Introduction Since the dynamic random access memory (DRAM) with one transistor and one capacitor (1T1C) cell architecture appeared in late seventies, it has played a key role as the technology driver for ultra large scale integration (ULSI) silicon technology. During the last 20 years, the density of DRAM has been quadrupled every three years, presently reaching full production of 64 Mb DRAM and early stage of mass production of address: kkn0414@samsung.co.kr (K. Kim). 256 Mb DRAM. As the density increases, the minimum feature size has been scaled down from 10 mm for 16 Kb DRAM to 0.25 mm for 256 Mb DRAM at a factor of 0.84 per year, which is equivalent to the cell size reduction rate of 0.7 every year. With this scaling trend, a quadrupled density in a chip whose size is only 1.5 times bigger than previous generation has been realized. At the same time, the chip speed has been improved in spite of the increased chip size. In the mean while, the unit process as well as the integration process and the circuit design have undergone evolutions and revolutions. Among them, lithography technology, half-vcc bit line scheme, /00/$ - see front matter # 2000 Elsevier Science Ltd. All rights reserved. PII: S (99)

2 192 K. Kim / Microelectronics Reliability 40 (2000) 191±206 folded bit line cell architecture, three-dimensional capacitor structure, low leakage current of thin dielectric material, low resistance metal silicide technologies for word lines and bit lines are believed to be the key technologies in DRAM. Although great successes have been achieved, the current DRAM technology cannot be extended to the giga-bit era and beyond because of many challenges. The critical challenges mainly come from the extremely small cell size since the number of cells over 10 9 are integrated in a single chip of few centimeter squared die size. In such a small cell size, one transistor and one capacitor should be formed with satisfying the stringent requirements such as su cient cell charge, small leakage current, and fast charge transferring from and into memory cell capacitor. The stringent requirements impose a very tight control on maintaining process. The narrow process windows have already been the issues on the recent DRAM technology with higher performance such as Rambus DRAM and merged DRAM with logic (MDL). Unless the issues are overcome, giga-bit scaled DRAMs cannot be massively produced, although fully working 1 Gb DRAM has been demonstrated [1]. Lately many innovative technologies and approaches to resolve these issues have been demonstrated and proposed [2± 5]. In this paper, key issues and solutions will be discussed based on giga-bit scaled DRAM technology generation. 2. Challenges from small cell size The structure of 1T1C memory cell is the most important gure in characterizing DRAM in terms of die size, performance, yield, and even fabrication cost. The primary objective is to achieve the smaller cell size together with faster operation, wider process margin, and simpler fabrication methodology. It has been the major driving force in the development of DRAMs. The unit cell can be laid out in two di erent ways depending on the bit line arrangement as shown in Fig. 1. One is the open bit line cell architecture in which bit line pairs (bit line and bit line bar) are physically placed at both sides of the sense ampli er (see Fig. 1(a)). The other is the folded bit line cell architecture in which adjacent bit line pairs on the same side are connected to the sense ampli er (see Fig. 1(b)). Fig. 1. The cell con gurations and cell layouts of open bit line and folded bit line architectures. (a) Shows the cell con guration of open bit line architecture. The cell (one transistor and one capacitor) represented by lled circle is placed at the every intersection of the word line and bit line. (b) Indicates the cell con guration of folded bit line architecture. (c) Represents the cell layout for open bit line architecture. The unit cell size is 6F 2, and capacitor area is 2F 2. (d) Shows the cell layout of folded bit line architecture. The unit cell size is 8F 2 and capacitor area is 3F 2.

3 K. Kim / Microelectronics Reliability 40 (2000) 191± The smallest unit cell sizes are 6F 2 and 8F 2 in the open and folded bit line architectures, respectively, as shown in Fig. 1(c) and (d) where F denotes the half pitch of the bit line and is normally determined by lithography. The folded bit line cell architecture has been the standard layout due to its superior noise immunity in spite of bigger unit cell size. The common mode noise is easily eliminated because two adjacent bit lines are inputs of di erential sense ampli er in the folded bit line cell architecture. In contrast, the common mode noise cannot be canceled out in the open bit line architecture because of separated bit line and bit line bar con guration. The folded bit line cell architecture has been evolved from two-dimensional to three-dimensional cell structures such as trench cell [6] and stack cell [7] in order to increase the capacitor area. Since the trench and stack cells were invented, further evolutions on these cells have been achieved in terms of stability, process margin, and process complexity. Now both trench and stack cells are used in commercial DRAM products with their own advantages. The pronounced advantages of trench cell are higher transistor performance and better topology. High transistor performance is demanded for Rambus and Merged DRAM with logic [8]. Since trench cell capacitors are formed at the early stage of the processing sequence, it can give low thermal budget for transistors, thereby resulting in bene ts of improved transistor performance. Trench cell DRAM has inherently better topology because the memory cell capacitor is formed beneath the silicon surface. In spite of these advantages, trench cell DRAM has di culty in achieving su cient memory cell capacitance. The di culty comes from the extremely deep trench etching and the lack of capability of fabricating high dielectric capacitor such as tantalum penta-oxide (Ta 2 O 5 ) and bismuth strontium titanate (BST). On the other hand, stack cell has an advantage in implementing a high dielectric capacitor, which is one of the most critical obstacles in giga-bit scaled DRAM technology. Stack capacitor has been changed from the capacitor-under-bit line (CUB) to capacitor-over-bit line (COB) structure to satisfy the requirement of cell ca- Fig. 2. The schematic representation of typical COB (capacitor-over-bit line) stack cell. The numbers indicate the most critical area in giga-bit scaled DRAMs. (1) Denotes the memory cell capacitor in which su cient memory cell capacitance is the rst priority. (2) Illustrates the storage node junction where small junction leakage is the primary target to achieve. (3) Indicates the memory cell transistor where the small sub-threshold leakage current and small variation of the threshold voltage are the most important. (4) Illustrates the word line and bit line in which small RC delay is the rst objective to realize. (5) Indicates the memory cell connection technology in which the small process window is issue to be resolved in gaia-bit scaled DRAMs. (6) Shows the metallization technology where global topology and the number metal layers are primary concerns.

4 194 K. Kim / Microelectronics Reliability 40 (2000) 191±206 pacitance. The COB stack cell can provide more area for cell capacitor compared to CUB stacked cell. The maximum capacitor areas obtained in CUB and COB stack cell are 2F 2 and 3F 2, respectively. Therefore, COB stack cell will be a better candidate for giga-bit scaled DRAMs. A typical example of COB cell is illustrated in Fig. 2. Even though COB stack cell has a great possibility in the giga-bit scaled DRAM technology, there are still many challenges due to its extremely small cell size. The most challenging obstacles are insu cient cell capacitance and large leakage current at the storage junction. Besides, the variation of threshold voltage of memory cell transistors, increased delay of long wires such as word and bit lines, increased parasitic resistance between the cell capacitor and the bit line are other barriers in achieving a high yield. All of these issues come up to limit the process margin to a narrow window. Unless the aforementioned issues are solved, mass production of giga-bit scaled DRAMs cannot be easily achieved. In following sections, the challenges and directions to overcome the challenges are discussed based on the DRAM technology generations. 3. Memory cell capacitor technology Memory cell capacitance is the key parameter that determines the sensing signal margin, sensing speed, data retention time and endurance against the soft error event. It is generally accepted that the minimum cell capacitance should be 25fF/cell regardless of minimum feature size, density, and chip size. The requirement of memory cell capacitance over 25fF/cell is a practical design guideline rather than a theoretical limit. The junction leakage current from the storage junction of a memory cell, subthreshold leakage current of the memory cell transistor, capacitor dielectric leakage, charge loss due to a-particle and cosmic ray irradiation, noise coupling, and mismatch in the sense ampli er undesirably reduce sensing signal margin as shown in the following equation. 1 v S ˆ 2 C s C B C 1 sv cc Ij I sub C s C B I d tref C B v N Q c where v s denotes the sensing signal voltage. C s is memory cell capacitance and C B is the parasitic bit line capacitance. I j, I sub, and I d are junction leakage current of a storage node, subthreshold leakage current of a memory cell transistor and dielectric leakage current of a memory cell capacitor, respectively. t ref is the refresh time to represent data retention time. v N is the noise voltage due to noise coupling and mismatches of 1 threshold voltage and conductance of sense ampli er. Q c is the charge loss due to a-particle and cosmic ray irradiation. These undesirable components are very dif- cult to be attenuated and become dominant as dimension shrinks. Therefore, the requirement of memory cell capacitance should be over 25fF/cell so that the stable memory cell operation can be guaranteed in spite of the charge loss components mentioned previously. Capacitance of DRAM cell can be described as shown in the following equation for parallel plate capacitor, which is determined by the area of memory cell capacitor (A ), the dielectric constant of capacitor dielectric e), and the thickness of capacitor dielectric (d ). C s ˆ A e d The requirement of minimum capacitance of 25fF/cell imposes a great challenge on giga-bit scaled DRAMs because capacitor area is scaled down with the square of the minimum feature size. Up to now, most of the strategies to satisfy the minimum capacitance have been focused on increase of the memory cell capacitor area, as well as decrease of the dielectric thickness rather than using high dielectric material. For instance, the current stack cell in 0.25 mm DRAM technology requires cylindrically shaped capacitor with around 1 mm height within mm 2 of cell area, while the current trench cell with the same technology generation requires around 7±8 mm depth of trench. Both cells use NO (nitride oxide) dielectric whose thickness is around 4.5±5.0 nm in oxide-equivalent thickness. However, when technology advances from the 0.25 mm technology for 256 Mb DRAM to the 0.18 mm technology for 1 Gb DRAM, the capacitor area of 0.18 mm technology is reduced to a half of that in the 0.25 mm technology generation. Therefore, unless the capacitor dielectric thickness is reduced to a half of previous generation or the dielectric constant is doubled, the total surface area of the capacitor should be doubled. Since the ultimate thickness limit of NO dielectric is considered to be around 3.5±4 nm in oxide-equivalent thickness, the thickness of NO dielectric lm can not be scaled down below 4 nm oxide-equivalent thickness because of the abrupt increase of dielectric leakage current. The only possible way to satisfy the required memory cell capacitance is to increase the surface area of the storage node, which can be obtained either by increasing the stack height of the capacitor or by increasing the surface area of storage node with hemispherical grain (HSG) of polysilicon. The increased height of the capacitor gives a rise to other undesirable issues such as high global topology di erence and di culties in contact hole etching and storage node separ- 2

5 K. Kim / Microelectronics Reliability 40 (2000) 191± ation. It is generally accepted that the stack height of capacitor is limited to around 1.0±1.2 mm without appreciable yield loss. The increase of capacitor area with HSG is determined by the grain size of HSG. As a feature size shrinks, smaller grain size is required, resulting in less contribution to area improvement. Therefore, there is not much room for implementation of high capacitance by scaling down the dielectric thickness or expanding the capacitor area for the gigabit scaled DRAMs. As a result, it leads to the need for utilizing high dielectric materials. The strategy to select the appropriate capacitor structure and capacitor dielectric material is projected with DRAM technology generations in Fig. 3. The candidates for capacitor dielectric are NO, Ta 2 O 5, Al 2 O 3 and BST. NO dielectric is commonly used in all commercial DRAM products. The only issue in NO dielectric is that the thickness of NO is very close to its practical limit, and therefore, further scaling of the lm thickness seems to be impossible. NO dielectric can be extended to the 0.18 mm technology by using cylindrical storage structure whose inner surface area is enlarged by HSG. A good candidate to replace the NO dielectric beyond 0.18 mm technology generation seems to be Ta 2 O 5 which has a dielectric constant of 20±25. Currently, reliability of Ta 2 O 5 dielectric is being veri ed, and it will be ready for usage in commercial DRAM products in the near future. The capacitor using Ta 2 O 5 dielectric is based on MIS structure. M denotes the metal electrode for the plate node, I indicates dielectric, and S represents the heavily doped poly-silicon Fig. 3. A strategy for memory cell capacitor technology vs. DRAM technology generation. for the storage node. The plate electrode in Ta 2 O 5 capacitor is a stack of highly doped poly-silicon/titanium nitride (TiN), or heavily doped poly-silicon/tungsten nitride (WN). The reason to use TiN or WN is that TiN or WN layer prevents escaping of oxygen from Ta 2 O 5 and reaction of Ta 2 O 5 with poly-silicon during the poly-silicon deposition. The doped poly-silicon on top of the TiN or WN layer protects the metal electrodes from oxidizing during the inter-layer oxide deposition after capacitor formation. The thermal budget after formation of capacitor has been found to be crucial in scaling the thickness of Ta 2 O 5 dielectric. Lower thermal budget allows a thinner Ta 2 O 5 dielectric. How far the Ta 2 O 5 thin layer can be scaled is not clear, but the limit is believed to be around 2±3 nm in oxide equivalent thickness. Unless the thickness of Ta 2 O 5 can be scaled down, MIS Ta 2 O 5 capacitor can only be applied down to the 0.13 mm technology generation. Metal storage node instead of poly-silicon storage node has been proposed in order to scale down Ta 2 O 5 by eliminating the native oxide on storage poly-silicon because the native oxide on the surface of storage poly-silicon hinders scaling of dielectric lm thickness. But the MIM Ta 2 O 5 capacitor on metal electrode is challenged by a large dielectric leakage. Recently, thin aluminum oxide (Al 2 O 3 ) lm [9] appeared to be a promising candidate for dielectric material for 0.18±0.13 mm DRAM technology generation or probably for the 0.11 mm DRAM technology generation because Al 2 O 3 has high dielectric constant of 10 and has smaller leakage current than Ta 2 O 5. Smaller leakage current gives a better possibility for Al 2 O 3 thickness to be scaled down compared to Ta 2 O 5. Since Al 2 O 3 can be deposited by atomic layer deposition technique at lower temperatures below 4508C than NO and Ta 2 O 5 [9], Al 2 O 3 capacitor has great possibility in embedded DRAM application because of the low thermal budget. The issue of Al 2 O 3 is relatively low dielectric constant compared to Ta 2 O 5 and BST. The best candidate for dielectric material beyond 0.13 mm technology generation is probably BST due to its extremely high dielectric constant around 200±400. High dielectric BST capacitor should be formed in MIM structure because BST can only be crystallized on the metal electrode. The high dielectric BST capacitor, however, is still under development. The development is slowly progressing due to the di culty of etching metal electrode, unstable BST lm, a lack of barrier layers to strongly resist against oxidation, contamination originated from metal electrodes and BST lm, and many other integration related issues including hydrogen damage [10]. The key parameters for MIM BST capacitor are barrier height between metal electrodes and BST dielectric, dielectric constant, crystallization temperature for BST lm and the barrier

6 196 K. Kim / Microelectronics Reliability 40 (2000) 191±206 layers between storage electrode and poly-silicon plug. In addition, BST integration with current ULSI CMOS technology is very limited because BST integration requires dedicated facilities. The conduction current of BST capacitor is governed by Schottky emission current. Since the Schottky conduction current is strongly dependent on the barrier height between metal electrode and BST, the metal electrode should have a high work function. So far, Pt electrode is found to have superior leakage current characteristics as well as the highest capacitance. It is very important to control surface property of metal electrode and interface property between metal electrode and BST in order to maintain good barrier property. The dielectric constant of BST is known to be dependent on the thickness of the BST lm. As the BST lm thickness decreases, the dielectric constant decreases due to the lower dielectric constant region at the interface between metal and BST dielectric. The deposited BST dielectric requires high temperature annealing around 600±7508C in O 2 ambient for crystalline structure. Crystalline structure of BST lm is found to have higher dielectric constant and lower dielectric leakage current. During high temperature annealing in O 2 ambient, a considerable amount of oxygen penetrates Pt storage electrode, resulting in poly-silicon oxidation at the interface between the poly-silicon plug and the storage electrode. Therefore, the barrier layer to block the oxygen penetration should exist between Pt electrode and poly-silicon plug and have strong resistance to oxygen penetration at high annealing temperature. Unfortunately, TiN/titanium (Ti) barrier commonly used in current metallization scheme is not proper because of loss of barrier property at around 5008C. Although various barrier layers such as titanium silicon nitride (TiSiN) [11] and titanium aluminum nitride (TiAlN) [12] have been proposed, these barriers alone can not completely resolve the oxidation problem during BST crystallization at high temperature in O 2 ambient. Therefore, recent studies to prevent the oxidation problem are shifted from barrier materials to structure modi cations such as oxide spacer technology [13], recessed barrier [14] and Pt encapsulation with recessed barrier [15]. These approaches are intended to increase the oxygen penetration length, thereby suppressing the oxidation of poly-silicon at the interface. Another di cult issue which BST capacitor faces is the electrode formation. With the more vertical pro le of storage node, the larger capacitor area can be achieved. Pt is very di cult to etch vertically. Ru or RuO 2 electrodes are found to be easy in obtaining vertical etching pro le [16]. However, BST capacitor based on ruthenium (Ru) or ruthenium oxide (RuO 2 ) su ers the leakage current and low dielectric constant. Recently, many new approaches to form the storage node without relying on the metal electrode etching have been proposed. Among them, two approaches are promising. One approach is as follows: after barrier layer is formed, thick oxide is deposited and storage node is printed with hole shape pattern. After that, oxide etching is proceeded. Then metal electrode is deposited by chemical vapor deposition (CVD) and storage node is separated by metal chemical±mechanical polishing (CMP). The other one is that after contact hole etching as described in previous approach, the metal electrode is lled by electro-plating techniques like copper (Cu)-electroplating [17]. 4. Memory cell transistor technology The transistors used in DRAMs can be divided into two di erent classes. One is the n-metal-oxide semiconductor (MOS) memory cell transistor in the memory cell array, and the other one is complementary metal oxide semiconductor (CMOS) transistor in the periphery circuit. The requirements and approaches for transistors in DRAMs are quite di erent for each class of transistors. The constraints on the memory cell transistor come from non-scaleable high threshold voltage around 1 V regardless of technology generations in order to suppress the sub-threshold leakage current. The threshold voltage requirement of memory cell transistor makes the channel doping density to increase as the feature size shrinks. When the substrate doping density is higher than cm 3 in order to keep the threshold voltage around 1 V, leakage current due to the electric eld assisted tunneling [18] rapidly increases, resulting in increased junction leakage current. The gate length of memory cell transistor and its substrate doping concentration are projected as a function of technology generation in Fig. 4. The substrate doping concentration of memory cell transistor of 1 Gb DRAM based on the 0.18 mm technology reaches approximately cm 3. In order to reduce the substrate doping density, the self-aligned channel implantation scheme has been proposed [19], where high doping is localized only in the channel region and the doping beneath the source and drain regions is prohibited. Reduced doping density underneath source and drain regions is bene cial due to the reduction of junction capacitance. Although this process greatly reduces the substrate doping density, thereby suppressing abnormally high junction leakage current, it requires complicated process steps. When device dimension shrinks, the merit of this process diminishes because the distance between channel and heavily doped source/drain region decreases. Recently, a new cell transistor scheme by employing metal shield inside the

7 K. Kim / Microelectronics Reliability 40 (2000) 191± Fig. 4. The gate length and substrate doping concentration of memory cell transistor vs. DRAM technology generation. shallow trench isolation has been proposed in order to eliminate the increase of the substrate doping concentration [20]. In this innovative cell transistor, the channel stop implantation necessary for device isolation can be eliminated, thereby reducing substrate doping concentration as shown in Fig. 4. It is known that the channel stop implantation is one of the major sources in increasing source/drain substrate doping concentration [21]. Furthermore, this novel cell transistor can eliminate the disturbance from neighboring storage nodes due to electric eld penetration e ect [20]. This e ect becomes serious when the cell pitch is below 0.20 mm whose feature size corresponds to the 0.10 mm technology generation. Since the memory cell transistor has the minimum channel length and width, it is very susceptible to both the short channel and inverse narrow width e ects. Both e ects decrease the threshold voltage of memory cell transistor. It has been identi ed that the critical dimension (CD) variations of active width and gate length are the major sources for the threshold voltage variation of memory cell transistors. For instance, the threshold voltage variations due to active CD and gate CD variations in 0.18 mm 1 Gb DRAM have been reported to be as much as 150 mv/15 nm and 200 mv/15 nm, respectively [1]. These variations will be further spread out as the feature size decreases. The new memory cell transistor can reduce the threshold voltage variation by suppressing narrow width e ect of the memory cell transistor [20]. The high threshold voltage of memory cell transistor around 1 V imposes much higher voltage (1.5±1.7 times the supply voltage) to be applied to the gate of memory cell transistor than the external supply voltage in order to compensate for the charge loss due to the threshold voltage during reading and writing operations. The high voltage applied to the gate oxide limits the scaling of the gate oxide due to reliability, thereby resulting in thicker gate oxide in DRAM technology than that in logic technology with the same feature size. When DRAM array is integrated in high performance logic, the thicker gate oxide in DRAM array makes integration process di cult. Periphery CMOS transistors can be designed with the guidelines provided by the scaling theories [22,23]. So far, the periphery CMOS transistors used in DRAMs have been developed with focuses on low leakage current and high breakdown voltage rather

8 198 K. Kim / Microelectronics Reliability 40 (2000) 191±206 than high performance such as high driving capability and low parasitic resistances which are more important in logic application. Also the cost e ectiveness of DRAM has driven fabrication of transistors towards simple process. As a result, single poly-silicon gate or single polycide gate has been the standard scheme for DRAM transistors with thick gate oxide. This approach will be continued in the giga-bit scaled DRAMs as long as single gate is allowed. However, recent movement towards merged technology with logic such as logic embedded DRAM or DRAM embedded logic greatly demands transistors with high performance, especially high driving capability. Decreasing the minimum feature size with high pe1rformance and low operating supply voltage shifts the transistor design approach from simple methodologies towards diversi ed and complicated ones. The dual gate transistor and various threshold voltages scheme, for example, become important. Various threshold voltages depending on the natures of circuits will be used for satisfying fast operation under low supply voltage and low standby current. For instance, the low threshold voltage will be used in sensing circuitry to overcome speed delay, and the high threshold voltage will be used in leakage sensitive circuit. At what gate dimension the dual gate should be introduced in DRAM is still controversial, but it is expected to be introduced at 0.10 mm DRAM technology generation with around 0.18 mm PMOS transistor gate length [3]. Beyond the 0.10 mm technology generation, dual gate will be indispensable. delay of word line can be expressed as follows. R WL ˆ r W L Wh ˆ R SW W L W C WL ˆ C p WL R WL C WL ˆ R SW W C p L 2 Here, W, L, and h are the width, length and thickness of the word line. R WL, r W, and R SW W are resistance, resistivity, and sheet resistance of the word line, respectively. C WL and C p are total parasitic capacitance and unit area parasitic capacitance of the word line, respectively. Low resistance metal silicides such as WSi x and TiSi x have been used as typical materials for the word line. It is well known that metal silicide shows an increase of the sheet resistance when the width of metal silicide decreases, which can be explained by the line width e ect. It has been continuously suppressed by eliminating the agglomeration of the metal silicide. For instance, the line width e ect of WSi x has been mitigated with modifying the composition, morphology and grain size of WSi x lm. The line width e ect of TiSi x has also been suppressed by pre-amorphization techniques before silicidation [24]. The line width e ect of various metal silicides and the strategy for the word line technology are shown in Fig. 5. The WSi x can be extended down to the 0.13 mm Word line and bit line technology The word line and bit line technologies are crucial in DRAM because they determine the chip operation speeds such as T RCD and T RP, where T RCD indicates the delay between row address strobe signal and column address strobe signal, and T RP denotes the row precharge time. With small values of these items, fast chip operation is obtained and these items are closely related to the critical path of the random access which increases proportionally to the chip size. The word line delay is the most critical factor for T RCD. When density increases quadruple, length of word line (L ) is also proportionally increased by a factor of 1.22 which is proportional to square root of chip size increasing factor 1.5. Since RC delay of the word line is proportional to the square of the length of word line, word line delay will be increased by a factor of 1.5 when the DRAM density quadruples. The resistance, parasitic capacitance and RC Fig. 5. Word line resistance of various word line technologies vs. DRAM technology generation.

9 K. Kim / Microelectronics Reliability 40 (2000) 191± technology by optimizing the composition, morphology and grain size. TiSi x has received much attention due to its low resistivity, and it was considered as the dominant gate material beyond the 0.15 mm technology generation. However, the severe line width e ect and narrow window of thermal stability of TiSi x make it di cult to be production-worthy technology. As a result, the importance of TiSi x gate diminishes, and it is expected to have short lifetime during the 0.10 mm technology generation at the most. Beyond the 0.1 mm technology generation, metal gate such as W and new metal silicide such as NiSi are indispensable because of extremely high resistance of WSi x and TiSi x. The word line capacitance has been determined by the gate capacitance of word line. However, when the device dimension shrinks, other parasitic capacitance between word line and poly-silicon plug cannot be negligible. Silicon nitride is typically used as the gate spacer for electrical isolation between the word line and poly-silicon plug beyond the 0.18 mm technology generation. This parasitic capacitance will be comparable to gate capacitance of word line at the 0.15 mm technology generation. And it will be the dominant source of word line capacitance beyond 0.13 mm generation. In this regime, it is expected that the unselected word line will be greatly disturbed by selected word line due to the appreciable capacitive coupling noise, thereby causing a great concern for the stable memory cell operation. Bit line resistance is the dominant factor in determining how fast bit line level reaches its predetermined value, so called precharge time. Both WSi x and W have been used as bit line material. Both technologies will be used down to the 0.18 mm technology generation. Beyond the 0.18 mm technology, W bit line technology will be the main technology because of high resistance of WSi x. The parasitic bit line capacitance, on the other hand, is one of the most important parameters to determine DRAM performance such as the sensing speed and data retention time because parasitic bit line capacitance together with memory cell capacitance determines the sensing signal margin as shown in Eq. (1). The smaller bit line capacitance can yield a wider sensing signal margin. The typical value of parasitic bit line capacitance is always set to be around 6±10 times of the memory cell capacitance. The minimum memory cell capacitance of 25fF constrains the parasitic bit line capacitance to be in the range of 150fF±250fF regardless of technology generation. This constraint limits the number of cells to be connected to a bit line. 256 cells are typically connected to a bit line in current DRAMs. Recent advanced DRAM technologies such as the 0.15 mm DRAM technology [4] use self-aligned contact etching technology in order to overcome the small process latitude in giga-bit scaled DRAMs. The self-aligned contact etching technology utilizes etching selectivity of the Si 3 N 4 lm against oxide during the storage node contact hole etching. The self-aligned contact hole etching technology requires word line and bit line fully encapsulated with Si 3 N 4 lms. Fully encapsulated word line and bit line with Si 3 N 4 lms are virtually free from the tight requirement of overlay accuracy and misalignment tolerance, which can not be avoided in the conventional small contact hole etching technology as Fig. 6. An illustration of the small contact etching technology for storage node connection. A 0.15 mm DRAM technology is employed. (a) Shows the SEM image after storage node contact hole etching with small contact etching technology. Contact holes are touched with W-bit line even with small misalignment of 30 nm. (b) Shows the distribution of shortage between the storage node and bit line across the 8 in wafer. More than 50% failure is observed.

10 200 K. Kim / Microelectronics Reliability 40 (2000) 191±206 shown in Fig. 6. Even though the self-aligned contact hole etching technology has bene cial features for the memory cell technology beyond the 0.15 mm DRAM generation, this technology has drawbacks such as large parasitic bit line capacitance due to high dielectric constant of Si 3 N 4. Parasitic bit line capacitance is known to be composed of two components which are the junction capacitance between bit line and substrate (C BL, Sub ) and interlayer capacitances; between the bit line and storage node (C BL, SN ), bit line and word line (C BL, WL ), bit line and plate node (C BL, PN ) and bit line and bit line (C BL, BL ), as illustrated in Fig. 7(a)). The C BL, WL, C BL, SN and C BL, Sub are dominant sources for the total parasitic bit line capacitance in the case of COB stack cell. The C BL, WL and C BL, SN in self-aligned contact hole etching technology are about twice larger than those of small contact hole etching technology, thereby resulting in 40% increase of the total parasitic bit line capacitance as shown in Fig. 7(b). Since the increased parasitic bit line capacitance reduces the sensing signal margin, a novel cell structure having small parasitic bit line capacitance should be invented for giga-bit scaled DRAMs. based on the small contact hole etching. Therefore, this technology can not resolve the issues related to contact hole printing such as overlay accuracy and mis-alignment tolerance, and it resulted in serious yield 6. Memory cell connection technology One of the major critical process steps in fabricating the memory cell for giga-bit scaled DRAMs is to form the memory cell landing pad with which the storage node can be connected to junction of memory cell transistor. In principle, the storage node can be directly connected to the junction of the memory cell transistor without the landing pad. However, the direct connection requires an extremely deep and small contact hole etching technology. Even though deep and small contact hole etching technology has been greatly improved recently, it always su ers from micro-loading e ect and etching stopping phenomenon due to reactive-ion-etching (RIE) lag [25]. The size of contact hole with ensured overlay accuracy and mis-alignment tolerance is smaller than the minimum feature size of technology generation. Furthermore, the direct connection technology can not be free from the tight overlay accuracy and small mis-alignment tolerance. In order to mitigate di culties of direct connection technology, memory cell landing pad technology was introduced at the 0.25 mm technology generation. Poly-silicon plug is formed selectively on the source and drain of the memory cell transistor with this technology. Since then, memory cell landing pad technology has been the mainstream of the subsequent DRAM technology generations. The memory cell landing pad technology introduced at 0.25 mm technology generation was Fig. 7. The schematic diagram of the components of parasitic bit line capacitance in COB stack cell, and parasitic bit line capacitance as a function of technology generation with small contact landing pad and self-aligned landing pad technology. (a) Represents schematic diagram of components of parasitic bit line capacitance. (b) Shows the bit line parasitic bit line capacitance. Here, 256 cell per bit line is used for all evaluations.

11 loss due to the shortage between word line and polysilicon plug when device dimension shrinks down further. In order to overcome this limitation, a new memory cell landing technology based on the selfaligned contact etching as shown in Fig. 8(a)) was developed at the 0.15 mm technology generation [2]. By using this technology, the shortage between word line and polysilicon plug is completely eliminated. It will be the dominant technology beyond the 0.15 mm technology generation. Another big challenge to fabricate the memory cell is to how to form storage node contact hole down to poly-silicon landing pad without severe yield loss. The storage node contact has been formed based on the small contact etching, therefore, it cannot be free from the issues of small contact hole printing as discussed previously. Furthermore, storage node contact requires K. Kim / Microelectronics Reliability 40 (2000) 191± Fig. 9. Storage node contact hole size and aspect ratio of storage node contact hole vs. technology generation with the small contact hole etching technology and the self-aligned contact hole etching. Fig. 8. An illustration of memory cell connection technology for the 0.15 mm DRAM technology generation and beyond with the self-aligned landing pad technology (a) and the selfaligned contact hole etching technology for storage node contact holes (b). deep and small contact hole etching technology because of its high aspect ratio of contact hole. Even though the small contact hole printing has been mitigated by contact size shrinking photoresist process [3], it cannot be free from the tight overlay accuracy and tight control of mis-alignment. The di culty to extend contact size shrinking process and to etch contact holes with the high aspect ratio comes up to limit this process to 0.18 mm technology generation. In order to overcome these challenges, a self-aligned contact hole etching technology as shown in Fig. 8(b) was developed for the 0.15 mm technology generation and beyond. The size of memory cell contact hole and aspect ratio are illustrated as a function of technology generation for small contact etching technology and selfaligned etching technology in Fig. 9. As indicated in Fig. 9, the aspect ratio of the contact hole increases rapidly in case of the small contact etching technology. It will be greater than 10 of the aspect ratio beyond the 0.13 mm technology generation. However, when the self-aligned landing pad technology is employed, the aspect ratio of the contact hole can be reduced because a wider size of contact hole printing is allowed in the self-aligned contact etching technology. Furthermore, the shortage problems between the storage node and bit line and between the storage node and word line are completely eliminated in self-aligned contact hole etching technology. As discussed in previous section, the self-aligned landing pad technology results in an increase parasitic bit line capacitance. Therefore, either new self-aligned etching technology based on low

12 202 K. Kim / Microelectronics Reliability 40 (2000) 191±206 K-dielectric materials or novel cell structure having small parasitic bit line capacitance should be developed for giga-bit scaled DRAMs. 7. Metallization technology with small contact hole technology The importance of metallization process of DRAM has been addressed as the density of DRAM increases. It is also generally known that the metallization scheme determines the chip yield as well as the chip performance in DRAM. In order to obtain su cient cell capacitance for giga-bit scaled DRAMs, the height of MIS cell capacitor around 1 mm with high dielectric material like Ta 2 O 5 must be achieved. Although the owable oxides such as boro-phospho-silicate glass (BPSG), spin-onglass (SOG) and hydrogen silsesquioxane (HSQ) have been used as inter-layer dielectric (ILD) material for reducing the topology di erence between cell array and peripheral region, large topology di erence still remains. When the conventional ILD materials such as BPSG, SOG, or HSQ are applied after capacitor formation, the global topology di erence between cell array and peripheral region is proportional to cell capacitor height because the conventional ILDs only improve local planarity. BPSG which has been used as interlayer dielectric material is well known to require re ow process at high temperature over 8008C, which can be a serious limiting factor in scaling down device because high temperature process after transistor formation makes it di cult to form shallow junction. The high temperature process necessary in BPSG can be eliminated when SOG is used for ILD material. However, etch back process step should be added. Recently, HSQ having high owability has drawn much attention, but HSQ also requires an extra annealing process because HSQ has high etching rate in oxide etching environments. The capacitor height and topology di erence between cell array and periphery region is evaluated with conventional ILD materials in Fig. 10. It can be concluded that globally at surface cannot be obtained with conventional ILD materials because these materials can be only locally planarized. Therefore, CMP process must be applied in order to obtain a globally at surface that is crucial for metallization process in scaled down devices. When CMP process is used for global topology, the issues of conventional ILD materials such as owablity, etch-back, and high temperature annealing process are no longer important because atness can be achieved by CMP process. For instance, low temperature plasma-enhanced-teos Fig. 10. Capacitor stack height and global topology in COB stack cell with DRAM technology generation. (PE-TEOS) material which cannot be used in conventional ILD scheme can be used easily. The globally at surface requires deep and small contact etching technology. As previously described in landing pad technology, the metal contact etching with high aspect ratio has the same issues such as microloading e ect and etch stop as well as tapered contact hole pro le. It has been found that etch stopping and tapered contact hole pro le can be mitigated with low ion ux etching. Etching chemistry is another important factor to be considered in contact etching with high aspect ratio. For instance, when the CHF 3 and CH 3 F gases are used as major etch chemicals, bowed and/or tapered contact hole pro le is obtained because the area of contact hole entrance is decreased during contact hole etching due to hydrocarbon by-product generation at the neck of contact hole. In the case of using C 4 F 8 gas, carbon rich by-product is heavily generated on the bottom of contact hole, resulting in an etch stopping. On the other hand, in the case of using C 2 F 6 gas as the major etch chemical, carbon rich byproduct is conformably deposited on the side-wall and bottom of contact hole. As a result, high aspect ratio contact hole is successfully fabricated without etching stopping. The ratio of carbon to uorine in the plasma, which can be increased by controlling the temperature of silicon roof in plasma chamber, is important in order to improve oxide etch selectivity to silicon and photo resist lm. The contact in memory cell is formed between highly doped n poly-silicon and highly doped n silicon substrate. It does not require the ohmic and barrier layer formation between highly doped n poly-silicon and highly doped n silicon substrate. The contact resistance is not the rst priority in memory cell operation as long as the contact resistance is less than a few per-

13 K. Kim / Microelectronics Reliability 40 (2000) 191± cent of the cell transistor conductance. In contrast, the metal contacts are formed typically between metals such as W and Al and the highly doped n and p + silicon substrates. It does require ohmic and barrier layers between metal and silicon substrate in order to prevent the metal penetration into the silicon substrate. The Ti/TiN layers have been used as ohmic and barrier layers. Here Ti serves as the ohmic layer by forming TiSi x, and TiN serves as the barrier layer. Ti is typically deposited by sputtering and TiN is also deposited by reactive sputtering. The lack of conformality in sputtering deposition has been improved by using collimation method [26], long-through sputtering [27], and ion metal plasma deposition [28]. However, these methods cannot satisfy the requirement of high aspect ratio contact in giga-bit scaled DRAMs which is expected to be more than 6. The ultimate solutions for such deep and small contact hole with high aspect ratio will be CVD deposition for both ohmic and barrier layer deposition. The metallization scheme in DRAMs has been changed from single metal scheme to double metal scheme at 16 Mb DRAM generation. The double metal scheme has been dominant technology for metallization of stand-alone DRAM up to 256 Mb DRAM. The further extension of double metal scheme in gigabit scaled DRAMs will faces di culty due to increased interconnection delay and power line noise. The triple metallization will be introduced at 4 Gb DRAM based on the 0.13 mm technology generation. The triple metallization will be extended up to 16 Gb DRAM. Beyond this generation, multiple level metallization will be necessary for high performance. In multiple level metallization [29], Cu and low dielectric technologies become important in order to reduce the power consumption, speed delay, cross-talk, and IR drop. These e ects will be a great concern in high performance and high density giga-bit scaled DRAMs. Cu technology has many issues which are brought from the material characteristics of Cu such as fast di usion in oxide and silicon substrate [30] and di culty in RIE etching [31]. the issues beyond the 0.10 mm technology generation seem to be generated from technology migration itself. For instance, the increased parasitic bit line capacitance in self-aligned contact hole etching technology and increased coupling capacitance of word line in memory cell landing pad technology make capacitor technology more di cult. Therefore, new cell concepts or novel cell structures are needed. One of the novel cell structures is proposed in this section. This cell is intended to have extremely small parasitic bit line capacitance. The schematic diagram of this novel cell is shown in Fig. 11. In this cell structure, the word line and memory cell capacitor is underneath the thin silicon lm. Therefore, the bit line is physically and electrically isolated from the word line, storage node and plate node by thin silicon. As a result, interlayer capacitances of the bit line to word line, bit line to storage node and bit line to plate node are no longer exist. In order to prove small parasitic bit line capacitance of this novel cell, COB stack cell, trench cell and a novel cell structure proposed in this paper are investigated with the 0.13 mm DRAM technology. The results for the parasitic bit line capacitance are summarized in the Table 1. Among the capacitor structures, COB stack cell has the largest parasitic bit line capacitance. The value of the parasitic bit line capacitance of trench cell is in the middle between COB stack cell and novel structure because C BL, SN can be eliminated. The novel structure has the smallest bit line capacitance because C BL, SN, C BL, WL and C BL, Sub are eliminated because the bit line is com- 8. Novel memory cell structure for beyond 0.10 mm technology generation Down to the 0.10 mm technology generation, the challenges for each technology generation can be speci cally de ned, and the ways to overcome these obstacles can be established based on the current COB cell structure with technology migrations. The technology migration has been discussed up to here, and optimal selection for technology migration is also suggested for each technology generation. However, Fig. 11. A novel cell structure to have extremely small parasitic bit line capacitance.