HI-546, HI-547, HI-548, HI-549

Transcription

1 Data Sheet June 15, 2016 F Single 16 and 8, Differential 8-Channel and 4-Channel CMOS nalog MUXs with ctive Overvoltage rotection The HI-546, HI-547, HI-548 and HI-549 are analog multiplexers with active overvoltage protection and guaranteed r O matching. nalog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. ctive protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. nalog inputs can withstand constant 70V - levels with 15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1k of resistance under this condition. These features make the HI-546, HI-547, HI-548 and HI-549 ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. ll devices are fabricated with 44V Dielectrically Isolated CMOS technology. The HI-546 is a single 16-Channel, the HI-547 is an 8-Channel differential, the HI-548 is a single 8-Channel and the HI-549 is a 4-Channel differential device. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see pplication otes 520 and 521. Features nalog Overvoltage rotection V - o Channel Interaction During Overvoltage Guaranteed r O Matching Maximum ower Supply V Break-Before-Make Switching nalog Signal Range V ccess Time (Typical) ns Standby ower (Typical) mW b-free lus nneal vailable (RoHS Compliant) pplications Data cquisition Industrial Controls Telemetry For MIL-STD-883 compliant parts, request the HI-546/883, HI-547/883, HI-548/883 and HI-549/883 datasheets. 1 CUTIO: These devices are sensitive to electrostatic discharge; follow proper IC Handling rocedures ITERSIL or Intersil (and design) is a registered trademark of Intersil mericas LLC Copyright Intersil mericas LLC 2003, 2005, ll Rights Reserved ll other trademarks mentioned are the property of their respective owners.

2 Ordering Information RT UMBER RT MRKIG TEM. RGE ( o C) CKGE KG. DWG. # HI HI to Ld CERDI F28.6 HI Z (ote) (o longer available, recommended replacement: HI Z, HI Z) HI Z 0 to Ld DI* (b-free) E28.6 HI Z (ote) HI4546-5Z 0 to Ld LCC (b-free) HI Z** (ote) HI9546-9Z -40 to Ld SOIC (b-free) M28.3 HI Z (ote) HI Z 0 to Ld DI* (b-free) E28.6 HI Z (ote) (o longer available, recommended replacement: HI Z) HI4547-5Z 0 to Ld LCC (b-free) HI Z** (ote) HI9547-9Z -40 to Ld SOIC (b-free) M28.3 HI HI to Ld CERDI F16.3 HI Z (ote) HI Z 0 to LED DI (b-free) E16.3 HI Z** (ote) HI9548-5Z 0 to Ld SOIC (b-free) M16.15 HI Z (ote) HI9548-9Z -40 to Ld SOIC (b-free) M16.15 HI HI to Ld CERDI F16.3 HI (o longer available or supported) HI to Ld DI E16.3 HI Z (ote) HI Z 0 to Ld DI (b-free E16.3 HI Z (ote) (o longer available or supported) HI4549-5Z 0 to Ld LCC (b-free) HI Z (ote) HI9549-9Z -40 to Ld SOIC (b-free) M16.15 *b-free DIs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. **dd 96 suffix for tape and reel. OTE: Intersil b-free plus anneal products employ special b-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both Snb and b-free soldering operations. Intersil b-free products are MSL classified at b-free peak reflow temperatures that meet or exceed the b-free requirements of IC/JEDEC J STD-020. inouts HI-546 (CERDI, DI, SOIC) TO VIEW HI-547 (CERDI, DI, SOIC) TO VIEW +V SULY V SULY 1 28 C V SULY B V SULY C 3 26 I 8 C 3 26 I 8 I I 7 I 8B 4 25 I 7 I I 6 I 7B 5 24 I 6 I I 5 I 6B 6 23 I 5 I I 4 I 5B 7 22 I 4 I I 3 I 4B 8 21 I 3 I I 2 I 3B 9 20 I 2 I I 1 I 2B I 1 I EBLE I 1B EBLE GD DDRESS 0 GD DDRESS 0 V REF DDRESS 1 V REF DDRESS 1 DDRESS DDRESS 2 C DDRESS 2 2

3 inouts (Continued) HI-546 (LCC) TO VIEW HI-547 (LCC) TO VIEW I 16 C C +V SULY -V SULY I I 8B C B +V SULY -V SULY I I I 7 I 7B 5 25 I 7 I I 6 I 6B 6 24 I 6 I I 5 I 5B 7 23 I 5 I I 4 I 4B 8 22 I 4 I I 3 I 3B 9 21 I 3 I I 2 I 2B I 2 I I 1 I 1B I GD V REF EBLE GD V REF C EBLE HI-548 (CERDI, DI, SOIC) TO VIEW HI-549 (CERDI, DI, SOIC) TO VIEW EBLE EBLE 2 15 GD -V SULY 3 14 GD -V SULY V SULY I V SULY I I 1B I I 5 I I 2B I I 6 I I 3B I I 7 I I 4B 8 9 I B HI-548 (LCC) TO VIEW HI-549 (LCC) TO VIEW -V SULY I 1 C I 2 I EBLE 0 C GD +V SULY C I 5 I 6 -V SULY I 1 C I 2 I EBLE 0 C GD 19 O LOGER VILBLE OR SUORTED V SULY I 1B C I 2B I 3B I 4 C I 8 I I 4 C B I 4B 3

4 TRUTH TBLE HI E O CHEL X X X X L one L L L L H 1 L L L H H 2 L L H L H 3 TRUTH TBLE HI-547 (Continued) E O CHEL IR H L L H 5 H L H H 6 H H L H 7 H H H H 8 L L H H H 4 L H L L H 5 L H L H H 6 L H H L H 7 L H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 H H L L H 13 H H L H H 14 H H H L H 15 TRUTH TBLE HI E O CHEL X X X L one L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 H H H H H 16 TRUTH TBLE HI-549 TRUTH TBLE HI E O CHEL IR X X X L one L L L H 1 L L H H 2 L H L H E O CHEL IR X X L one L L H 1 L H H 2 H L H 3 H H H 4 L H H H 4 Functional Diagrams HI-546 HI-547 I 1 I 1 I 2 I 16 DECODER/ DRIVER I 8 I 1B I 8B DECODER/ DRIVER B OVERVOLTGE CLM D SIGL ISOLTIO 5V REF LEVEL SHIFT OVERVOLTGE CLM D SIGL ISOLTIO 5V REF LEVEL SHIFT DIGITL IUT ROTECTIO DIGITL IUT ROTECTIO V REF E V REF E 4

5 Functional Diagrams (Continued) HI-548 HI-549 I 1 I 1 I 2 I 8 DECODER/ DRIVER I 4 I 1B I 4B DECODER/ DRIVER B OVERVOLTGE CLM D SIGL ISOLTIO 5V REF LEVEL SHIFT OVERVOLTGE CLM D SIGL ISOLTIO 5V REF LEVEL SHIFT DIGITL IUT ROTECTIO DIGITL IUT ROTECTIO E 0 1 E Schematic Diagrams DDRESS DECODER V+ TO -CHEL DEVICE OF THE SWITCH 0 OR 0 2 OR 2 1 OR 1 TO -CHEL DEVICE OF THE SWITCH 3 OR 3 EBLE DELETE 3 OR 3 IUT FOR HI-547, HI-548, HI-549 DELETE 2 OR 2 IUT FOR HI-549 V- 5

6 Schematic Diagrams (Continued) MULTILEX SWITCH FROM DECODE OVERVOLTGE ROTECTIO V+ Q5 I R11 D6 D7 D4 D5 Q6 V- FROM DECODE 6

7 Schematic Diagrams (Continued) DDRESS IUT BUFFER D LEVEL SHIFTER TTL REFERECE CIRCUIT V+ R10 V REF Q1 R9 Q4 D3 GD LEVEL SHIFTER V+ OVERVOLTGE ROTECTIO D2 V+ R2 R3 R4 R5 R6 R7 R8 LEVEL SHIFTED DDRESS TO DECODE R1 200 D1 V- GD V- DD I 7

8 bsolute Maximum Ratings V+ to V V V+ to GD V V- to GD V Digital Input Voltage (V E, V ) (V-) -4V to (V+) +4V nalog Signal (V I, V ) (V-) -20V to (V+) +20V or 20m, Whichever Occurs First Continuous Current, I or m eak Current, I or (ulsed 1ms, 10% Duty Cycle Max).. 40m Operating Conditions Temperature Ranges HI-546/548/ o C to 125 o C HI-546/547/548/ o C to 75 o C HI-546/547/548/ o C to 85 o C Thermal Information Thermal Resistance (Typical, ote 1) J ( o C/W) JC ( o C/W) 16 Ld CERDI ackage Ld CERDI ackage Ld DI ackage* / 16 Ld DI ackage / 28 Ld LCC ackage / 20 Ld LCC ackage / 28 Ld SOIC ackage / 16 Ld SOIC ackage / Maximum Junction Temperature Ceramic ackages o C lastic ackages o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (LCC, SOIC - Lead Tips Only) *b-free DIs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CUTIO: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. OTE: 1. J is measured with the component mounted on an evaluation C board in free air. Electrical Specifications Supplies = +15V, -15V; V REF in = Open; V H (Logic Level High) = 4V; V L (Logic Level Low) = 0.8V; Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section RMETER SWITCHIG CHRCTERISTICS TEST CODITIOS TEM ( o C) -2-5, -9 MI TY MX MI TY MX UITS ccess Time, t s Full s Break-Before Make Delay, t OE ns Enable Delay (O), t O(E) ns Full ns Enable Delay (OFF), t OFF(E) ns Full ns Settling Time To 0.1% s To 0.01% s Off Isolation ote db Channel Input Capacitance, C S(OFF) pf Channel Output Capacitance C D(OFF) HI pf HI pf HI pf HI pf Input to Output Capacitance, C DS(OFF) pf DIGITL IUT CHRCTERISTICS Input Low Threshold, TTL Drive, V L Full V Input High Threshold, V H (ote 8) Full V MOS Drive, V L (HI-546/547 Only) V REF = 10V V 8

9 Electrical Specifications Supplies = +15V, -15V; V REF in = Open; V H (Logic Level High) = 4V; V L (Logic Level Low) = 0.8V; Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) RMETER TEST CODITIOS TEM ( o C) -2-5, -9 MOS Drive, V H (HI-546/547 Only) V REF = 10V V Input Leakage Current (High or Low), I ote 5 Full LOG CHEL CHRCTERISTICS nalog Signal Range, V I Full V On Resistance, r O ote k Full k r O, (ny Two Channels) % Off Input Leakage Current, I S(OFF) ote n Full n Off Output Leakage Current, I D(OFF) ote n HI-546 Full n HI-547 Full n HI-548 Full n HI-549 Full n I D(OFF) With Input Overvoltage pplied ote n Full On Channel Leakage Current, I D(O) ote n HI-546 Full n HI-547 Full n HI-548 Full n HI-549 Full n Differential Off Output Leakage Current I DIFF (HI-547, HI-549 Only) Full n OWER SULY CHRCTERISTICS ower Dissipation, D Full mw Current, I+ ote 7 Full m Current, I- ote 7 Full m OTES: 2. V = 10V, I = n is the practical lower limit for high speed measurement in the production test environments. 4. nalog Overvoltage = 33V. 5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1n at 25 o C. 6. V E = 0.8V, R L =, C L = 15pF, V S = 7V RMS, f = 100kHz. 7. V E, V = 0V or 4V. 8. To drive from DTL/TTLCircuits, 1k pull-up resistors to +5V supply are recommended. MI TY MX MI TY MX UITS 9

10 Test Circuits and Waveforms T = 25 o C, V SULY = 15V, V H = 4V, V L = 0.8V, V REF = Open, Unless Otherwise Specified 100 V 2 I V I ro = V FIGURE 1. O RESISTCE TEST CIRCUIT 1.4 O RESISTCE (k o C 25 o C -55 o C ORMLIZED O RESISTCE (REFERRED TO VLUE T 15V) LOG IUT (V) SULY VOLTGE (V) FIGURE 1C. ORMLIZED O RESISTCE vs SULY FIGURE 1B. O RESISTCE vs LOG IUT VOLTGE VOLTGE FIGURE 1. O RESISTCE 100n 10n LEKGE CURRET 1n O LEKGE CURRET I D(O) OFF UT CURRET I D(OFF) 10V E +0.8V I D(OFF) 10V 100p OFF IUT LEKGE CURRET I S(OFF) 10p TEMERTURE ( o C) FIGURE 2. LEKGE CURRET vs TEMERTURE FIGURE 2B. I D(OFF) TEST CIRCUIT (OTE 9) 10

11 Test Circuits and Waveforms T = 25 o C, V SULY = 15V, V H = 4V, V L = 0.8V, V REF = Open, Unless Otherwise Specified I S(OFF) E +0.8V E I D(O) 10V 10V 10V 10V 4V FIGURE 2C. I S(OFF) TEST CIRCUIT (OTE 9) FIGURE 2D. I D(O) TEST CIRCUIT (OTE 9) OTE: 9. Two measurements per channel: 10V and 10V. (Two measurements per device for I D(OFF) : 10V and 10V.) FIGURE 2. LEKGE CURRETS 18 LOG IUT CURRET (m) LOG IUT CURRET (I I ) UT OFF LEKGE CURRET ID (OFF) LOG IUT OVERVOLTGE (V) UT OFF LEKGE CURRET (n) I I V I I D(OFF) FIGURE 3. LOG IUT CURRET D UT OFF LEKGE CURRET vs LOG IUT OVER-VOLTGE FIGURE 3. LOG IUT OVERVOLTGE CHRCTERISTICS FIGURE 3B. TEST CIRCUIT o C 25 o C SWITCH CURRET (m) o C V I VOLTGE CROSS SWITCH (V) FIGURE 4. O CHEL CURRET vs VOLTGE FIGURE 4. O CHEL CURRET FIGURE 4B. TEST CIRCUIT 11

12 Test Circuits and Waveforms T = 25 o C, V SULY = 15V, V H = 4V, V L = 0.8V, V REF = Open, Unless Otherwise Specified 8 +15V/+10V +I SULY SULY CURRET (m) V SULY = 15V V SULY = 10V 10K 100K 1M 10M TOGGLE FREQUECY (Hz) FIGURE 5. SULY CURRET vs TOGGLE FREQUECY FIGURE 5. DYMIC SULY CURRET V 50 +4V E GD V+ 3 I 1 HI I 2 THRU 1 I 15 0 I 16 V- Similar connection for HI-547/HI-548/HI V/-10V FIGURE 5B. TEST CIRCUIT -I SULY 10M 10V/5V 10V/ 5V 14pF CCESS TIME (ns) V REF = OE FOR LOGIC HIGH LEVEL 6V V REF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V V 50 +4V +15V V REF V+ 3 I 1 2 I 2 THRU I 15 1 HI E I 16 GD V- 10V 10V 10k 50pF LOGIC LEVEL (HIGH) (V) -15V Similar connection for HI-547/HI-548/HI-549. FIGURE 6. CCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 6B. TEST CIRCUIT 50% V H = 4.0V DDRESS DRIVE (V ) 0V V IUT 2V/DIV. S 1 O +10V t 10% UT -10V UT 5V/DIV. S 16 O 200ns/DIV. FIGURE 6C. MESUREMET OITS FIGURE 6. CCESS TIME FIGURE 6D. WVEFORMS 12

13 Test Circuits and Waveforms T = 25 o C, V SULY = 15V, V H = 4V, V L = 0.8V, V REF = Open, Unless Otherwise Specified 3 2 HI-546 I 1 +5V V H = 4V V 50 +4V I 2 THRU 1 I 15 0 I 16 E GD 1k V 50pF 0V 50% 50% DDRESS DRIVE (V ) UT t OE Similar connection for HI-547/HI-548/HI-549 FIGURE 7. TEST CIRCUIT FIGURE 7B. MESUREMET OITS V IUT 2V/DIV. S 1 O S 16 O UT 0.5V/DIV. 100ns/DIV. FIGURE 7C. WVEFORMS FIGURE 7. BREK-BEFORE-MKE DELY 3 HI I 1 I 2 THRU I16 +10V 50% V H = 4V 50% EBLE DRIVE (V ) 0V V 50 0 E GD 1k V 50pF 90% UT 10% 0V Similar connection for HI-547/HI-548/HI-549 t O(E) t OFF(E) FIGURE 8. TEST CIRCUIT FIGURE 8B. MESUREMET OITS 13

14 Test Circuits and Waveforms T = 25 o C, V SULY = 15V, V H = 4V, V L = 0.8V, V REF = Open, Unless Otherwise Specified EBLE DRIVE 2V/DIV. DISBLED UT 2V/DIV. EBLED (S 1 O) 100ns/DIV. FIGURE 8C. WVEFORMS FIGURE 8. EBLE DELYS 14

15 Die Characteristics DIE DIMESIOS: 83.9 mils x 159 mils METLLIZTIO: Type: Cul Thickness: 16kÅ 2kÅ SUBSTRTE OTETIL (OTE): -V SULY SSIVTIO: Type: itride Over Silox itride Thickness: 3.5kÅ 1kÅ Silox Thickness: 12kÅ 2kÅ WORST CSE CURRET DESITY: 1.4 x 10 5 /cm 2 TRSISTOR C: 485 ROCESS: CMOS-DI OTE: The substrate appears resistive to the -V SULY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -V SULY potential. Metallization Mask Layouts HI-546 E V REF GD (18) (17) (16) (15) (14) (13) (12) HI-547 E C V REF GD (18) (17) (16) (15) (14) (13) (12) I 1 (19) I 2 (20) I 9 (11) I 10 (10) I 1 (19) I 2 (20) I 1B (11) I 2B (10) I 3 (21) I 4 (22) I 11 (9) I 12 (8) I 3 (21) I 4 (22) I 3B (9) I 4B (8) I 5 (23) I 6 (24) I 13 (7) I 14 (6) I 5 (23) I 6 (24) I 5B (7) I 6B (6) I 7 (25) I 15 (5) I 8 I 16 (26) (4) I 7 (25) I 7B (5) I 8 I 8B (26) (4) V- (27) (28) +V (1) C (2) V- (27) (28) +V (1) B(2) 15

16 Die Characteristics DIE DIMESIOS: 83 mils x 108 mils METLLIZTIO: Type: Cul Thickness: 16kÅ 2kÅ SUBSTRTE OTETIL (OTE): -V SULY SSIVTIO: Type: itride Over Silox itride Thickness: 3.5kÅ 1kÅ Silox Thickness: 12kÅ 2kÅ WORST CSE CURRET DESITY: 1.4 x 10 5 /cm TRSISTOR C: 253 ROCESS: CMOS-DI OTE: The substrate appears resistive to the -V SULY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -V SULY potential. Metallization Mask Layouts HI-548 I 6 I 7 I 8 I 4 I 3 (11) (10) (9) (8) (7) (6) HI-549 I 3B I 4B B I 4 I 3 (11) (10) (9) (8) (7) (6) I 5 (12) +V (13) GD (14) I 2 (5) I 1 (4) -V (3) I 2B (12) I 1B (13) +V (14) I 2 (5) I 1 (4) -V (3) E (15) (16) (1) (2) GD 1 0 E (15) (16) (1) (2) 16

17 Revision History HI-546, HI-547, HI-548, HI-549 The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. lease go to the web to make sure that you have the latest revision. DTE REVISIO CHGE June 15, 2016 F Updated ordering information table on page 2. October 1, 2015 F Updated Ordering Information Table on page 2. - dded Revision History. - dded bout Intersil Verbiage. - Updated OD M28.3 to latest revision changes are as follow: dded land pattern -dded ackage Outline Drawing M16.15 to the latest revision. bout Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at ll Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. o license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 17

18 Ceramic Dual-In-Line Frit Seal ackages (CERDI) BSE LE SETIG LE S1 b2 ccc M bbb S b C - B Q -C- -B- C - B S D e D S -D- -- OTES: 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1,, /2, and /2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. is the maximum number of terminal positions. 9. Dimensioning and tolerancing per SI Y14.5M Controlling dimension: ICH. E L M c1 e/2 S D S aaa M C - B LED FIISH BSE METL b1 M (b) SECTIO - S e c D S (c) F28.6 MIL-STD-1835 GDI1-T28 (D-10, COFIGURTIO ) 28 LED CERMIC DUL-I-LIE FRIT SEL CKGE ICHES MILLIMETERS SYMBOL MI MX MI MX OTES b b b b c c D E e BSC 2.54 BSC - e BSC BSC - e/ BSC 7.62 BSC - L Q S o 105 o 90 o 105 o - aaa bbb ccc M , Rev. 0 4/94 18

19 Dual-In-Line lastic ackages (DI) HI-546, HI-547, HI-548, HI-549 IDEX RE BSE LE SETIG LE D1 B1 -C /2 B D e D1 E1 OTES: 1. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per SI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of ublication o Dimensions, 1 and L are measured with the package seated in JEDEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. is the maximum number of terminal positions. 10. Corner leads (1,, /2 and /2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). -B (0.25) M C 2 L B S e C E C L e C e B E28.6 (JEDEC MS-011-B ISSUE B) 28 LED DUL-I-LIE LSTIC CKGE ICHES MILLIMETERS SYMBOL MI MX MI MX OTES B B C D D E E e BSC 2.54 BSC - e BSC BSC 6 e B L Rev. 1 12/00 19

20 lastic Leaded Chip Carrier ackages (LCC) (1.07) (1.22) I (1) IDETIFIER D1 D (0.51) MX 3 LCS (0.66) (0.81) C L (1.07) (1.42) (1.27) T E1 E C L (0.33) (0.53) (0.10) C (0.64) (1.14) R D2/E2 D2/E2 VIEW OTES: 1. Controlling dimension: ICH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per SI Y14.5M Dimensions D1 and E1 do not include mold protrusions. llowable mold protrusion is inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. is the number of terminal positions. -C (0.51) MI SETIG LE (JEDEC MS-018B ISSUE ) 28 LED LSTIC LEDED CHI CRRIER CKGE ICHES MILLIMETERS SYMBOL MI MX MI MX OTES D D D , 5 E E E , Rev. 2 11/ (1.14) MI VIEW TY (0.64) MI 20

21 Small Outline lastic ackages (SOIC) HI-546, HI-547, HI-548, HI-549 IDEX RE D e B 0.25(0.010) M C M E -B- -- -C- SETIG LE B S H 0.25(0.010) M B 1 a 0.10(0.004) L M h x 45o C M28.3 (JEDEC MS-013-E ISSUE C) 28 LED WIDE BODY SMLL LIE LSTIC CKGE ICHES MILLIMETERS SYMBOL MI MX MI MX OTES B C D E e 0.05 BSC 1.27 BSC - H h L o 8 o 0 o 8 o - Rev. 1, 1/13 TYICL RECOMMEDED LD TTER (1.50mm) (9.38mm) (1.27mm TY) (0.51mm TY) OTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of ublication umber Dimensioning and tolerancing per SI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 21

22 Ceramic Dual-In-Line Frit Seal ackages (CERDI) BSE LE SETIG LE S1 b2 ccc M bbb S b C - B Q -C- -B- C - B S D e D S -D- -- OTES: 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1,, /2, and /2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. is the maximum number of terminal positions. 9. Dimensioning and tolerancing per SI Y14.5M Controlling dimension: ICH. E L M c1 e/2 S D S aaa M C - B LED FIISH BSE METL b1 M (b) SECTIO - S e c D S (c) F16.3 MIL-STD-1835 GDI1-T16 (D-2, COFIGURTIO ) 16 LED CERMIC DUL-I-LIE FRIT SEL CKGE ICHES MILLIMETERS SYMBOL MI MX MI MX OTES b b b b c c D E e BSC 2.54 BSC - e BSC 7.62 BSC - e/ BSC 3.81 BSC - L Q S o 105 o 90 o 105 o - aaa bbb ccc M , Rev. 0 4/94 22

23 Dual-In-Line lastic ackages (DI) HI-546, HI-547, HI-548, HI-549 IDEX RE /2 -B- -- D E BSE LE 2 -C- SETIG LE L C L D1 1 e D1 B1 e e C C B e B (0.25) M C B S OTES: 1. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per SI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of ublication o Dimensions, 1 and L are measured with the package seated in JE- DEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. is the maximum number of terminal positions. 10. Corner leads (1,, /2 and /2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). E1 E16.3 (JEDEC MS-001-BB ISSUE D) 16 LED DUL-I-LIE LSTIC CKGE ICHES MILLIMETERS SYMBOL MI MX MI MX OTES B B , 10 C D D E E e BSC 2.54 BSC - e BSC 7.62 BSC 6 e B L Rev. 0 12/93 23

24 lastic Leaded Chip Carrier ackages (LCC) (1.07) (1.22) I (1) IDETIFIER D1 D (0.51) MX 3 LCS (0.66) (0.81) C L (1.07) (1.42) (1.27) T E1 E C L (0.33) (0.53) (0.10) C (0.64) (1.14) R D2/E2 D2/E2 VIEW (0.51) MI SETIG LE (JEDEC MS-018 ISSUE ) 20 LED LSTIC LEDED CHI CRRIER CKGE ICHES MILLIMETERS SYMBOL MI MX MI MX OTES D D D , 5 E E E , Rev. 2 11/ (1.14) MI VIEW TY (0.64) MI -C- OTES: 1. Controlling dimension: ICH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per SI Y14.5M Dimensions D1 and E1 do not include mold protrusions. llowable mold protrusion is inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. is the number of terminal positions. 24

25 Small Outline lastic ackages (SOIC) HI-546, HI-547, HI-548, HI-549 IDEX RE e D B 0.25(0.010) M C M E -B- -- -C- SETIG LE B S H 0.25(0.010) M B (0.004) OTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of ublication umber Dimensioning and tolerancing per SI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x 45 C M16.15 (JEDEC MS-012-C ISSUE C) 16 LED RROW BODY SMLL LIE LSTIC CKGE ICHES MILLIMETERS SYMBOL MI MX MI MX OTES B C D E e BSC 1.27 BSC - H h L Rev. 1 6/05 25