Low-Leakage, CMOS Analog Multiplexers

Transcription

1 / General Description The / are monolithic, CMOS analog multiplexers (muxes). The 8-channel is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 4Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 2pA at +2 C), and extremely low on-channel leakages (less than pa at +2 C). The new design offers guaranteed low charge injection (.pc typ) and electrostatic discharge (ESD) protection greater than 2V, per method 3.7. These improved muxes are pin-compatible upgrades for the industry-standard DG8A and DG9A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329. The / operate from a single +4.V to +3V supply or from dual supplies of ±4.V to ±2V. All control inputs (whether address or enable) are TTL compatible (+.8V to +2.4V) over the full specified temperature range and over the ±4.V to ±8V supply range. These parts are fabricated with Maxim s 44V silicon-gate process. Applications Data-Acquisition Systems Sample-and-Hold Circuits Test Equipment Heads-Up Displays Military Radios Communications Systems Guidance and Control PBX, PABX Systems Features On-Resistance, <4Ω max Transition Time, <ns On-Resistance Match, <Ω NO-Off Leakage Current, <2pA at +2 C.pC Charge Injection Single-Supply Operation (+4.V to +3V) Bipolar-Supply Operation (±4.V to ±2V) Plug-In Upgrade for Industry-Standard DG8A/DG9A Rail-to-Rail Signal Handling TTL/CMOS-Logic Compatible ESD Protection >2V, per Method 3.7 Ordering Information PART TEMP RANGE PIN-PACKAGE CEE+ C to +7 C 6 QSOP CPE+ C to +7 C 6 PDIP CSE+ C to +7 C 6 Narrow SO C/D C to +7 C Dice* EEE+ -4 C to +8 C 6 QSOP ETE+ -4 C to +8 C 6 TQFN-EP** (mm x mm) Ordering Information continued at end of data sheet. *Contact factory for dice specifications. **EP = Exposed Pad ***Contact factory for availability. +Denotes a lead(pb)-free/rohs-compliant package. Pin Configurations/Functional Diagrams/Truth Tables TOP VIEW A NO NO2 NO A GND NO NO6 NO NO2 NO3 NO4 NO NO6 GND NO4 7 NO7 NO7 8 9 DIP/SO/QSOP Pin Configurations/Functional Diagrams/Truth Tables continued at end of data sheet. CMOS DECODE LOGIC A A 8-CHANNEL SINGLE-DED MULTIPLEXER 9-272; Rev ; /7

2 / Absolute Maximum Ratings Voltage Referenced to V...-.3V, 44V GND...-.3V, 2V Digital Inputs, NO, (Note )... ( - 2V) to ( + 2V) or 3mA (whichever occurs first) Continuous Current (any terminal)...3ma Peak Current, NO or (pulsed at ms, % duty cycle max)...ma Continuous Power Dissipation (T A = +7 C) Plastic DIP (derate.3mw/ C above +7 C)...842mW Narrow SO (derate 8.7mW/ C above +7 C)...696mW 6 QSOP (derate 8.3mW/ C above +7 C) mW 6-Pin TQFN (derate 2.8mW/ C above +7 C) mW CERDIP (derate.mw/ C above +7 C)...8mW Operating Temperature Ranges MAX33_C... C to +7 C MAX33_E C to +8 C MAX33_MJE, MSE... - C to +2 C Storage Temperature Range C to + C Lead Temperature (soldering, sec)...+3 C Soldering Temperature (reflow) Lead(Pb)-free packages C Packages containing lead(pb) C Note : Signals on NO,,, A, A, or exceeding or are clamped by internal diodes. Limit forward current to maximum current ratings. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics Dual Supplies ( = +V, = -V, V GND = V, V AH = +2.4V, V AL = +.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Analog Signal Range On-Resistance R ON I NO =.2mA, V = ±V On-Resistance Matching Between Channels NO-Off Leakage Current (Note ) -Off Leakage Current (Note ) -On Leakage Current (Note ) MIN TYP MAX (Note 2) V NO, V (Note 3) - V ΔR ON I NO(OFF) I (OFF) I (ON) I NO =.2mA, V = ±V (Note 4) V = +V, V NO = ±V, V = V V NO = ±V, V = +V, V = V V = +V, V NO = ±V, V = V V = ±V, V NO = ±V, Sequence each switch on C, E C, E C, E C, E T A = +2 C 22 4 T A = T MIN to T MAX T A = +2 C 4 T A = T MIN to T MAX T A = +2 C T A = T MIN C, E to T MAX M -2 2 T A = +2 C -... T A = T MIN to T MAX M -4 4 T A = +2 C -... T A = T MIN to T MAX M -2 2 T A = +2 C T A = T MIN to T MAX M -4 4 T A = +2 C T A = T MIN to T MAX M -2 2 UNITS Ω Ω na na na Maxim Integrated 2

3 / Electrical Characteristics Dual Supplies (continued) ( = +V, = -V, V GND = V, V AH = +2.4V, V AL = +.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX (Note 2) INPUT Input Current with Input Voltage High I AH V A = 2.4V or V -... µa Input Current with V I = V or 2.4V, Input Voltage Low AL V A = V -.. µa SUPPLY Power-Supply Range ±4. ±2 V Positive Supply Current I+ T A = +2 C V = V A = V µa T A = T MIN to T MAX V = 2.4V, T A = +2 C 29 µa V A(ALL) = 2.4V T A = T MIN to T MAX 6 Negative Supply Current I- V = V or 2.4V, T A = +2 C - V A(ALL) = V, 2.4V or V T A = T MIN to T MAX - µa DYNAMIC Transistion Time t TRANS Figure 2 T A = +2 C 2 ns Break-Before-Make Interval t OP Figure 4 T A = +2 C 4 ns Enable Turn-On Time t ON() Figure 3 T A = +2 C 6 T A = T MIN to T MAX 7 ns Enable Turn-Off Time t OFF() Figure 3 T A = +2 C T A = T MIN to T MAX 7 ns Charge Injection (Note 3) Q C L = pf, V NO = V, R S = Ω, Figure 6 UNITS T A = +2 C. pc Off Isolation (Note 6) V ISO V = V, R L = kω, f = khz T A = +2 C -7 db Crosstalk Between Channels V CT V = 2.4V, f = khz, V G = V P-P, R L = kω, Figure 7 T A = +2 C -92 db Logic Input Capacitance C IN f = MHz T A = +2 C 2 pf NO-Off Capacitance C NO(OFF) V = V NO = V, T A = +2 C 3 pf f = MHz, Figure 8 -Off Capacitance C (OFF) V =.8V, V = V, f = MHz, Figure 8 -On Capacitance C (ON) V = 2.4V, V = V, f = MHz, Figure 8 T A = +2 C 6 6 T A = +2 C 9 pf pf Maxim Integrated 3

4 / Electrical Characteristics Single Supply ( = +2V, = V, V GND = V, V AH = +2.4V, V AL = +.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Analog Signal Range I On-Resistance R NO =.2mA ON V = 3V or V DYNAMIC Transition Time (Note 3) Enable Turn-On Time (Note 3) Enable Turn-Off Time (Note 3) MIN TYP MAX (Note 2) V NO, V (Note 3) 2 V t TRANS V NO = 8V, V = V, V IN = 2.4V, Figure t ON() t OFF() V INH = 2.4V, V INL = V, V NO = V, Figure 3 V INH = 2.4V, V INL = V, V NO = V, Figure 3 UNITS T A = +2 C 46 6 Ω T A = +2 C 2 ns T A = +2 C 28 ns T A = +2 C ns Charge Injection (Note 3) Q C L = pf, V NO = V, R S = Ω T A = +2 C.8 ns Note 2: The algebraic convention where the most negative value is a minimum and the most positive value a maximum is used in this data sheet. Note 3: Guaranteed by design. Note 4: ΔR ON = R ON(MAX) - R ON(MIN). Note : Leakage parameters are % tested at the maximum rated hot temperature and guaranteed by correlation at +2 C. Note 6: Worst-case isolation is on channel 4 because of its proximity to the drain pin. Off isolation = 2log V /V NO, where V = output and V NO = input to off switch. Maxim Integrated 4

5 / Typical Operating Characteristics (T A = +2 C, unless otherwise noted.) RON (Ω) ON-RESISTANCE vs. V (DUAL SUPPLIES) ±V ±V ±V ±2V /9 toc RON (Ω) ON-RESISTANCE vs. V OVER TEMPERATURE (DUAL SUPPLIES) = +V = -V - C +2 C +2 C +8 C /9 toc2 RON (Ω) ON-RESISTANCE vs. V (SINGLE SUPPLY) +V +2V +V +2V /9 toc V (V) V (V) V (V) 2 RON (Ω) ON-RESISTANCE vs. V OVER TEMPERATURE (SINGLE SUPPLY) = +V = V +2 C +8 C +2 C - C /9 toc4 OFF LEAKAGE (na).. OFF LEAKAGE vs. TEMPERATURE = +V = -V I (OFF) /9 toc ON LEAKAGE (na).. ON LEAKAGE vs. TEMPERATURE = +V = -V I (ON) /9 toc6. I NO (OFF). V (V) TEMPERATURE ( C) TEMPERATURE ( C) Qj (pc) CHARGE INJECTION vs. V C L = pf = V V (V) V +V +2V /9 toc7 I+, I- (µa).. SUPPLY CURRT vs. TEMPERATURE I+, V A(ALL) = 2.4V I+, V A = V I TEMPERATURE ( C) /9 toc8 ttrans (ns) R L = kω TRANSITION TIME vs. POWER SUPPLIES DUAL SUPPLIES SINGLE SUPPLY ± OR V (SINGLE) ± OR V (SINGLE) ± ±2 SUPPLY VOLTAGE (V) /9 TOC-9 Maxim Integrated

6 / Pin Description PIN NAME FUNCTION DIP/SO/QSOP TQFN-EP DIP/SO/QSOP TQFN-EP,, 6,, 4, 3 A,, A Address Inputs, 6, 4 A, A Address Inputs Enable 3 3 Negative-Supply Voltage Input NO NO4 Analog Inputs Bidirectional NOA NO4A Analog Inputs Bidirectional 8 6 Analog Output Bidirectional 8, 9 6, 7 A, B Analog Outputs Bidirectional NO Analog Inputs Bidirectional 3 8 NO4B NOB Analog Inputs Bidirectional Positive-Supply Voltage Input GND Ground Exposed Pad Exposed Pad (TQFN only). Connect EP to. Applications Information Operation with Supply Voltages Other than V Using supply voltages less than ±V will reduce the analog signal range. The / switches operate with ±4.V to ±2V bipolar supplies or with a +4.V to +3V single supply. Connect to GND when operating with a single supply. Both device types can also operate with unbalanced supplies such as +24V and -V. The Typical Operating Characteristics graphs show typical on-resistance with 2V, V, V, and V supplies. (Switching times increase by a factor of two or more for operation at V.) Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings, because stresses beyond the listed ratings may cause permanent damage to the devices. Always sequence on first, then, followed by the logic inputs NO and. If power-supply sequencing is not possible, add two small signal diodes in series with supply pins for overvoltage protection (Figure ). Adding diodes reduces the analog signal range to V below and V above, but does not affect the devices low switch resistance and low leakage characteristics. Device operation is unchanged, and the difference between and should not exceed 44V. V g NO Figure. Overvoltage Protection Using External Blocking Diodes Maxim Integrated 6

7 / Test Circuits/Timing Diagrams +V Ω NO A NO2-NO7 A GND kω ±V +V pf LOGIC INPUT +3V V % tr < 2ns t f < 2ns Ω -V +V A NOB A NOA-NO4A NO4B B GND kω ±V +V pf V NO OUTPUT V V t TRANS ON 9% ON 9% t TRANS -V Figure 2. Transition Time +V Ω A A GND NO NO2- kω -V pf LOGIC INPUT +3V V % tr < 2ns t f < 2ns Ω A A GND -V +V NOB NOA-NO4A, NO2B-NO4B, A B kω -V 3pF OUTPUT V O t ON() V 9% % t OFF() -V Figure 3. Enable Switching Time Maxim Integrated 7

8 / Test Circuits/Timing Diagrams (continued) +V +2.4V Ω NO- A A GND -V kω +V pf LOGIC INPUT OUTPUT +3V V V % 8% t OP tr < 2ns t f < 2ns Figure 4. Break-Before-Make Interval +V R S V S CHANNEL SELECT NO A A GND -V C L = pf LOGIC INPUT +3V V OFF ON OFF IS THE MEASURED VOLTAGE DUE TO CHARGE TRANSFER ERROR Q WH THE CHANNEL TURNS OFF. Q = C L x Figure. Charge Injection Maxim Integrated 8

9 / Test Circuits/Timing Diagrams (continued) +V nf +V nf V IN NO NO NO2 R S = Ω A A R L = kω R S = Ω A R L kω A GND GND nf -V nf -V OFF ISOLATION = 2log V IN CROSSTALK = 2log V IN Figure 6. Off-Isolation Figure 7. Crosstalk +V CHANNEL SELECT A NO A GND METER IMPEDANCE ANALYZER f = MHz -V Figure 8. NO/ Capacitance Maxim Integrated 9

10 / Pin Configurations/Functional Diagrams/Truth Tables (continued) GND TOP VIEW A NOA NO2A NO3A NO4A A A GND NOB NO2B NO3B N4B B NOA NO2A NO3A NO4A NOB NO2B NO3B NO4B CMOS DECODE LOGIC A B DIP/SO/QSOP A A DUAL 4-CHANNEL MULTIPLEXER A A X X X ON None LOGIC V AL.8V, LOGIC V AH 2.4V A A X X ON None LOGIC V AL.8V, LOGIC V AH 2.4V Maxim Integrated

11 / Pin Configurations/Functional Diagrams/Truth Tables (continued) TOP VIEW A A A A GND LOGIC 2 GND LOGIC 2 NO 2 NOA 2 NOB NO2 3 NO NO2A 3 NO2B NO3 4 9 NO6 NO3A 4 9 NO3B *EP *EP NO4 NO7 NO4A A B NO4B *CONNECT EP TO TQFN-EP TQFN-EP Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE EPE+ -4 C to +8 C 6 PDIP ESE+ -4 C to +8 C 6 Narrow SO EJE -4 C to +8 C 6 CERDIP MJE - C to +2 C 6 CERDIP*** MSE/PR3+ - C to +2 C 6 Narrow SO CEE+ C to +7 C 6 QSOP CPE+ C to +7 C 6 PDIP CSE+ C to +7 C 6 Narrow SO PART TEMP RANGE PIN-PACKAGE EEE+ -4 C to +8 C 6 QSOP ETE+ -4 C to +8 C 6 TQFN-EP** (mm x mm) EPE+ -4 C to +8 C 6 PDIP ESE+ -4 C to +8 C 6 Narrow SO EJE -4 C to +8 C 6 CERDIP MJE - C to +2 C 6 CERDIP*** MSE/PR3+ - C to +2 C 6 Narrow SO C/D C to +7 C Dice* *Contact factory for dice specifications. **EP = Exposed Pad ***Contact factory for availability. +Denotes a lead(pb)-free/rohs-compliant package. Maxim Integrated

12 / Package Information For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 6 PDIP P Narrow SO S QSOP E TQFN-EP T CDIP J Maxim Integrated 2

13 / Revision History REVISION NUMBER REVISION DATE 4 4/2 DESCRIPTION Added the CEE+ / EEE+/ MSE /PR3 / CEE+ / EEE+ part and packaging information PAGES CHANGED, 2, 6,, /7 Updated Ordering Information table For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim Integrated s website at Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 27 Maxim Integrated Products, Inc. 3