Website: ECE 260B CSE 241A Parasitic Estimation 1

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1 ECE260B CSE241A Winter 2007 Parasitic Estimation Website: ECE 260B CSE 241A Parasitic Estimation 1

2 Outline Parasitic Estimation Wirelength Estimation ECE 260B CSE 241A Parasitic Estimation 2

3 Parasitic Estimation: Why do we need it? Example: to produce RC tree network for elmore delay analysis s R 1 C 1 1 R 2 R 3 C C 2 R 4 R i 4 C 4 i C i Example: to produce RC tree network for capacitive cross-talk analysis ECE 260B CSE 241A Parasitic Estimation 3 Slide courtesy L. Daniel

4 Parasitic Estimation (Two Basic Steps) Electromagnetic Analysis thin volume filaments with constant current small surface panels with constant charge million of elements Model Order Reduction tens of elements ECE 260B CSE 241A Parasitic Estimation 4 Slide courtesy L. Daniel

5 Why Layout Parasitic Extraction? Must do this after routing Account for non-ideal nature of interconnect Wire capacitance Wire and via resistance Parasitic information is used in post-layout verification Timing verification of synchronous circuits Functional verification of asynchronous circuits Design performance is ultimately limited by parasitics ECE 260B CSE 241A Parasitic Estimation 5

6 1-D and 2-D Estimation Above 0.5µm feature size, wire cross-section was rectangular Interconnect modeled as parallel plate over ground plane Parallel plate capacitance Fringe capacitance 2-D extraction accurate enough: Area + Fringe C_parallel C_fringe C_fringe ECE 260B CSE 241A Parasitic Estimation 6

7 LEF Coefficients (See Your LEF/DEF Reference) LEF capacitance values are 2-D CPERSQDIST EDGECAPACITANCE Capacitance coefficients are statistical in DSM Effective area and edge capacitance dependent on surrounding routing Congested blocks have higher effective capacitance Need to route design during floorplanning to generate LEF coefficient data Need to modify the LEF coefficients on block by block basis ECE 260B CSE 241A Parasitic Estimation 7

8 Net to Net Capacitances Crosstalk analysis Requires coupling knowledge Net to net capacitances Extraction to floating metal Similar to extraction for xtalk Net to net capacitances Effective capacitance to floating metal depends on potential of floating metal E.g., Cadence HyperExtract models floating metal as grounded If we model floating metal as grounded, this is pessimistic Below 0.18µm, fill metal can impact timing ECE 260B CSE 241A Parasitic Estimation 8

9 Capacitance Extraction Given a collection of N conductors (of any shape and dimension), Q = CV Find the coupling capacitance matrix C fringing parallel C =? v = q ECE 260B CSE 241A Parasitic Estimation 9 Slide courtesy L. Daniel

10 Capacitance Extraction 2-D extraction Wire cap includes parallel plate (area), fringing, and coupling cap C = k 1 Area + k 2 Perimeter + k 3 Coupling_length / Coupling_spacing These coefficients are fit in for an average environment of a wire Table Lookup Intra-layer capacitances are not well modeled 3-D extraction Solve for real 3-D geometries of wiring 2.5-D extraction Compromise between speed and accuracy Models 3-D effects by a combination of two orthogonal 2-D structures E.g., two cross-section views on the x-z and y-z planes, z is the vertical axis going through layers ECE 260B CSE 241A Parasitic Estimation 10

11 How 2.5-D Capacitance Extractor Works Technology pre-characterization generates coefficients through solving the 3-D equations for representative sample of topologies Really, cross-sections through tunnel that contains a section of the victim net Creates look-up table Time consuming, but only done once Each layer of interconnect added to the cross-section roughly doubles time for coefficient generation Pattern compression Reduces the total number of pre-characterization patterns Geometric parameter extraction Reduce the number of geometric parameters considering the shielding effect Extraction matches topologies to entries in look-up table ECE 260B CSE 241A Parasitic Estimation 11

12 Future Flows Involve Manufacturing Simulation Original SPEF Modified SPEF Litho Simulation Incremental RCX Reshape Engine Original GDSII Modified GDSII RCX ECE 260B CSE 241A Parasitic Estimation 12

13 Example Impact of Manufacturing Variation Capacitance Impact Print Image 90nm technology M2 Wires % of Segments 70.00% 60.00% 50.00% 40.00% 30.00% 20.00% 10.00% 0.00% -2~0% 0~2% 2~4% 4~6% 6~8% 8~10% 10~12% Capacitance Variation (%) (a) Resistance Impact % of Segments 25% 20% 15% 10% 5% 0% -5~-7% -9~-11% -13~-15% -17~-19% Resistance Variation (%) (b) ECE 260B CSE 241A Parasitic Estimation 13

14 Interconnect Sidewall Angle Manufacturing non-idealities can occur along the sidewall of a wire due to etch To accurately account for interconnect parasitics these geometric changes needs to be modeled Min-width =( min spacing) Metal thickness ILD thickness 0.20 um 0.35 um 0.35 um Theta (degrees) C NT : Capacitance with non-zero sidewall angle Total Interconnect Capacitance C T : Capacitance with zero sidewall angle C NT /C T Sidewall angles can decrease the total capacitance by more than 10% ECE 260B CSE 241A Parasitic Estimation 14

15 Simple Equivalent-Width Methodology Non-vertical sidewalls imply a capacitance between non-parallel (sidewall) plates w w h Cond_a θ l θ r Cond_b Ideal Real Comparison of ideal and real Interconnect cross-section. Capacitance between non-parallel plates can be calculated according to the following equation: ECE 260B CSE 241A Parasitic Estimation 15 εl(ln( d + h(tan tan h C = dc = 0 d εldx + xtan + xtan θl θl θl θr = + tanθr )) ln( d )) + tanθr d (1)

16 Interconnect Sidewall Angle We use the average of the top and bottom width of the wire as its new equivalent width w eq = Simulation Configuration w top + w 2 bottom L M + L L M M 1 1 C left C c C Right % Error Configurations Total Cap. % Error % Error Configurations Coupling Cap. % Error ECE 260B CSE 241A Parasitic Estimation 16

17 Impact of CMP Fill on Interconnect Capacitance To enhance uniformity of post-cmp wafer topography, dummy fill is inserted In addition to improving feature density uniformity, dummy fill also changes coupling and total capacitance of functional interconnects Different fill/wire geometries have different impact on interconnect capacitance ECE 260B CSE 241A Parasitic Estimation 17

18 Basic Simulation Configurations A B A B A B s x s y l f d ko w f w m y (1) (2) (3) x A l f w f dko ECE 260B CSE 241A Parasitic Estimation 18 y x w m

19 Impact of Floating Fill on Interconnect Capacitance Change in coupling capacitance due to changes in fill width Ctot/l (F/um) E E E E E E E-17 w_m=0.2, h_m=0.4 w_m=0.18, h_m=0.32 w_m=0.12, h_m= E E w f (um) Change in total capacitance due to changes in fill width Cc/l (F/um) E E E E E-18 w_m=0.2, h_m=0.4 w_m=0.18, h_m=0.32 w_m=0.12, h_m= E E ECE 260B CSE 241A Parasitic Estimation 19 w f (um)

20 Impact of Floating Fill on Interconnect Capacitance Change in coupling capacitance due to changes in fill length Ctot/l (F/um) E E E E E E E-17 w_m=0.2, h_m=0.4 w_m=0.18, h_m=0.32 w_m=0.12, h_m= E E l f (um) Change in total capacitance due to changes in fill length E E E-18 Cc/l (F/um) E E E E-18 w_m=0.2, h_m=0.4 w_m=0.18, h_m=0.32 w_m=0.12, h_m= E E ECE 260B CSE 241A Parasitic Estimation 20 l f (um)

21 Impact of Grounded Fill on Interconnect Capacitance Change in total capacitance due to changes in fill width dc (F) E E E E E E E E w f (um) w_m=0.2, h_m=0.4 w_m=0.18, h_m=0.32 w_m=0.12, h_m=0.2 Change in total capacitance due to changes in fill length ECE 260B CSE 241A Parasitic Estimation 21 dc (F) E E E E E E E l f (um) w_m=0.2, h_m=0.4 w_m=0.18, h_m=0.32 w_m=0.12, h_m=0.2

22 Impact of Via Fill on Wire Capacitance What is impact of via fill on total wire capacitance? M+2 Change in capacitance with and without via fill is insignificant M+1 M Metals in M+1, M, and M+1 layers already create shielded wall any additional metals, such as vias, do not have any significant additional impact on capacitance M - 1 M - 2 Without Via Fill Metal Layers Vias With Via Fill Case Capacitance (ff) Without Via Fill With Via Fill Change 2.1% ECE 260B CSE 241A Parasitic Estimation 22

23 Outline Parasitic Estimation Wirelength Estimation ECE 260B CSE 241A Parasitic Estimation 23

24 Wire Load Models (WLMs) Synthesis needs placement parasitics Placement needs synthesized netlist Chicken vs. egg WLMs estimate parastics pre-placement (can be custom per block, per bounding box area, etc. limit is set_load per net) Wire cap = f(net fanout) (but WLM picks just ONE value) Cap #Pins ECE 260B CSE 241A Parasitic Estimation 24

25 Cadence PKS (Placement-Knowledgeable Synthesis, ~1998) Flow RTL Generic Netlist Mapped Netlist Placed Netlist Routed Netlist Area opt Technology mapping Timing opt Placement Post-placement timing opt Global routing ECE 260B CSE 241A Parasitic Estimation 25

26 More Modern Flows: Trial Route Based Accurate parasitic information is required for generating correct netlist for timing closure Synthesis tightly integrated with parasitics resulting from physical design (place & route) WLMs used historically for driving synthesis New synthesis flows/tools do not rely on WLMs Estimate netlist embedding from its topology (latest version of design compiler) Some tools are driven by fast place/route/extraction engines that are built into the tool (e.g., Cadence PKS) Need for WLM-based synthesis offset by availability of netlist optimizations during physical implementation Timing optimizations after placement, clock-tree synthesis and routing ECE 260B CSE 241A Parasitic Estimation 26

27 Design Optimization During P&R RTL Design Clocks & Boundary Constraints Placement Post-Place Opt Logic Synthesis Trial-Route + RC Extraction CTS Verify & Add Exceptions (NO) Gate-Level Netlist Meet Timing Requirements Post-CTS Opt Routing Detailed RC Extraction (YES) Place and Route Meet Timing Requirements (YES) GDSII (NO) Verify & Add Exceptions ECE 260B CSE 241A Parasitic Estimation 27 Source: FishTail DA

28 Wirelength Estimation Basic Formulation: What is expected WL of a net N? Fundamental to pre-routing performance analysis Studied in several contexts floorplanning row-based placement hierarchical top-down layout Should match algorithmic, information context ECE 260B CSE 241A Parasitic Estimation 28

29 Types of Wirelength Estimation A priori (before placement) floorplanning and logic optimization low accuracy 15% faster than placement and routing A posteriori (after placement) placement feasibility analysis high accuracy 2% faster than routing On-line (during placement) e.g., top-down move-based placers intermediate accuracy 2-10% very fast ECE 260B CSE 241A Parasitic Estimation 29

30 On-Line WL Estimation R Given k rectangles each containing cells of a net i i N, what is expected WL of N? n Rectangles R i arise during top-down layout Terminals are localized in R i by floorplanning, partitioning Assumption: terminals are uniformly distributed within any given R i ECE 260B CSE 241A Parasitic Estimation 30

31 Classic Techniques for WL Estimation WL rectilinear Steiner minimal tree (RSMT) cost Beardwood et al. (1958): for n points in region R cost(rsmt) area( R) n Chung/Graham (1979): for n points in bounding box R max cost(rsmt) ( n + 1) HP( R)/ 2 Comments I stated the Beardwood result a couple of lectures ago Ron Graham is the former Chief Scientist of Bell Labs who is now on the UCSD CSE faculty (cf. the Steiner ratio in the Euclidean plane) ECE 260B CSE 241A Parasitic Estimation 31

32 Classic Techniques for WL Estimation WL(net) rectilinear Steiner minimal tree (RSMT) cost WL(net) net bounding box half-perimeter efficient updating (move-based placers) center-to-center approximation Cheng s (1994) scaling correction ECE 260B CSE 241A Parasitic Estimation 32

33 Classic Techniques for WL Estimation WL(net) rectilinear Steiner minimal tree (RSMT) cost WL(net) bounding box half-perimeter A priori WL estimations Rent s rule Wire Length Distribution (WLD) - (Donath (1979),, Davis et al. (1998)) neighborhood population technique - (Sechen (1988), Pedram/Preas (1989), Hamada et al. (1992)) ECE 260B CSE 241A Parasitic Estimation 33

34 Inaccuracy of Center-to-Center Bbox Estimator 1/3 Expected bbox for 2-terminal net is underestimated by center-to-center method ECE 260B CSE 241A Parasitic Estimation 34

35 Expected Bounding Box Given N rectangles Ri each with ni random points, find expected bbox of entire point set Treat horizontal and vertical dimensions separately Find expected minimum and maximum in each dimension Given n segments [ a ] each with one random point, find expected i, b i minimum of all points Exact formula (B = min, A = a... a ) b i 1 n E = A + B A (1 t a b a 1 t a n B i 1 1 t a i j ) dt (1 ) 1 i= 2 b j= 1 j a i ai b a j i dt ECE 260B CSE 241A Parasitic Estimation 35

36 RSMT for n Points in Region For n random points chosen uniformly in rectangular region R Old result (1958) : E[c(RSMT)] area( R) n New result (1998) For sufficiently large aspect ratio w(r)/h(r): E[c(RSMT)] HP(bbox) Old result true for n > N, where N=N(AR) depends on aspect ratio ECE 260B CSE 241A Parasitic Estimation 36

37 RSMT Growth Rate c( RSMT) n area.758 AR = 16 AR = 8 AR = 4 Aspect ratio AR = number of points Growth rates of c(rsmt) in rectangles with different aspect ratios ECE 260B CSE 241A Parasitic Estimation 37

38 Knowledge of BBox Helps Maximum relative deviation (%) from E[c(RSMT)] in 90% of all cases n points within square region n points with given square bounding box # points dev(region) dev(bbox) Conclusion: On average, knowledge of bbox halves maximum relative deviation doubles confidence in expected WL ECE 260B CSE 241A Parasitic Estimation 38

39 AR-Dependent Scaling random n-point samples with prescribed AR(bbox) NUMBER OF POINTS TABLE * AR TABLE entries: average values of cost(rsmt)/hp(bbox) E[cost(RSMT)] = TABLE(AR(bbox), n) HP(bbox) ECE 260B CSE 241A Parasitic Estimation 39

40 Reading Assignment, February 9 Read the clocking and clock tree construction references on the class webpage. Read the paper by Caldwell et al., On Wirelength Estimations for Row-Based Placement, paper #J41 at (you can also find the final version on IEEE Explore) ECE 260B CSE 241A Parasitic Estimation 40

41 Homework, February 9 Attention: Question 1 due February 16 Question 2 due February 14 Optimism vs. Pessimism. There is an old trick in synthesis: overconstrain the design timing if you want to make a given frequency goal. But, just as with floorplan area, there is a sweet spot for the target frequency that results in maximum actual frequency of the result. Homework Question #1: Use Cadence PKS to plot a frequency-vs.-area tradeoff curve of netlist implementations using our 90nm library. Homework Question #2: If k numbers are randomly chosen within the interval [0,1] with uniform distribution, what is the expected value of the minimum number? (Explain.) ECE 260B CSE 241A Parasitic Estimation 41